diff options
| author | jinghua <jinghua@marvell.com> | 2017-05-09 10:00:02 +0800 |
|---|---|---|
| committer | Hua Jing <jinghua@marvell.com> | 2017-05-09 11:19:43 +0300 |
| commit | 41a3ec8e13219894e68fd67594301890a9d61bf0 (patch) | |
| tree | 5c95d1226560abac0a9bf5dab92ad3087501bc3b | |
| parent | 13e515390c33384d974db86b5bfa433f774fa2c5 (diff) | |
fix: io-dec: a3700: disable io-decode windows to rWTM
- By default, several IOs have decode window to rWTM:
- SATA: window 2, from 0x1fff0000 to 0x2000ffff.
- SDIO/eMMC: window 2, from 0x1fff0000 to 0x2000ffff.
- USB32: window 2, from 0xC0000000 to 0xC000ffff.
- These windows should be disabled in non-DAS mode, since:
- These IOs should not access rWTM.
- These decode windows overlap with DRAM decode window.
For example, in 512MB DRAM case, SATA and SDIO/eMMC
rWTM window overlap with DRAM decode window in the
last 64KB DRAM address.
- This patch sets these decode window to be used for DRAM,
so software would disable them by default, and configure
them to be DRAM decode window if needed.
- JIRA: A3700-1163
Change-Id: I6d35a98b14f3ddc575930f83ea5e700995a29519
Signed-off-by: jinghua <jinghua@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39247
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
| -rw-r--r-- | plat/marvell/a3700/common/marvell_plat_config.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/a3700/common/marvell_plat_config.c index 05239826..3f6055be 100644 --- a/plat/marvell/a3700/common/marvell_plat_config.c +++ b/plat/marvell/a3700/common/marvell_plat_config.c @@ -38,14 +38,14 @@ struct dec_win_config io_dec_win_conf[] = { /* dec_reg_base win_attr max_dram_win max_remap win_offset */ {0xc000, 0x3d, 2, 0, 0x08}, /* USB */ - {0xc100, 0x3d, 2, 0, 0x10}, /* USB3 */ + {0xc100, 0x3d, 3, 0, 0x10}, /* USB3 */ {0xc200, 0x3d, 2, 0, 0x10}, /* DMA */ {0xc300, 0x3d, 2, 0, 0x10}, /* NETA0 */ {0xc400, 0x3d, 2, 0, 0x10}, /* NETA1 */ {0xc500, 0x3d, 2, 0, 0x10}, /* PCIe */ - {0xc800, 0x3d, 2, 0, 0x10}, /* SATA */ - {0xca00, 0x3d, 2, 0, 0x08}, /* SD */ - {0xcb00, 0x3d, 2, 0, 0x10}, /* eMMC */ + {0xc800, 0x3d, 3, 0, 0x10}, /* SATA */ + {0xca00, 0x3d, 3, 0, 0x08}, /* SD */ + {0xcb00, 0x3d, 3, 0, 0x10}, /* eMMC */ {0xce00, 0x3d, 2, 0, 0x10}, /* EIP97 */ }; |