diff options
| author | jinghua <jinghua@marvell.com> | 2017-04-17 18:42:48 +0800 |
|---|---|---|
| committer | Hua Jing <jinghua@marvell.com> | 2017-04-21 09:35:32 +0300 |
| commit | 4cd5e7a3ee43dcfb56444a9c205bb855ab348f9c (patch) | |
| tree | 12f551ca4a24132fb1f50158c506f6ce6ffee8a3 | |
| parent | 07852d308eb4ba17f152197ed271779fe2f79fc6 (diff) | |
fix: mpp: a3700: switch all SPI pins back from uart download feature
- In UART boot mode initialization, SPI CS and CLK pins are used as
downloading image purpose; But after downloading, these bits should
be switch back to SPI mode. Otherwise SPI functionality is broken.
- This patch sets bit 28 of north_bridge_pin_out_en_high register 13804,
to switch SPI CS and CLK pins back from UART download feature.
Change-Id: I30e2c0202da7f7b0fba3916af121da9017e1cce4
Signed-off-by: jinghua <jinghua@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38690
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
(cherry picked from commit eaa8a65da8af00d3443068418955f9396becd00f)
Reviewed-on: http://vgitil04.il.marvell.com:8080/38691
| -rw-r--r-- | plat/marvell/a3700/a3700/plat_bl31_setup.c | 13 | ||||
| -rw-r--r-- | plat/marvell/a3700/common/include/a3700_plat_def.h | 3 |
2 files changed, 16 insertions, 0 deletions
diff --git a/plat/marvell/a3700/a3700/plat_bl31_setup.c b/plat/marvell/a3700/a3700/plat_bl31_setup.c index 01fee40c..ed66f372 100644 --- a/plat/marvell/a3700/a3700/plat_bl31_setup.c +++ b/plat/marvell/a3700/a3700/plat_bl31_setup.c @@ -60,6 +60,19 @@ static void pass_dram_sys_info(void) static void marvell_bl31_mpp_init(void) { mmio_clrbits_32(MVEBU_NB_GPIO_SEL_REG, 1 << MVEBU_GPIO_TW1_GPIO_EN_OFF); + + /* Set hiden GPIO setting for SPI. + * In north_bridge_pin_out_en_high register 13804, + * bit 28 is the one which enables CS, CLK pins to be + * output, need to set it to 1. + * The initial value of this bit is 1, but in UART boot mode + * initialization, this bit is disabled and the SPI CS and CLK pins + * are used for downloading image purpose; so after downloading, + * we should set this bit to 1 again to enable SPI CS and CLK pins. + * And anyway, this bit value sould be 1 in all modes, + * so here we does not judge boot mode and set this bit to 1 always. + */ + mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); } /* This function overruns the same function in marvell_bl31_setup.c */ diff --git a/plat/marvell/a3700/common/include/a3700_plat_def.h b/plat/marvell/a3700/common/include/a3700_plat_def.h index 4195f4ae..4ad5d51a 100644 --- a/plat/marvell/a3700/common/include/a3700_plat_def.h +++ b/plat/marvell/a3700/common/include/a3700_plat_def.h @@ -88,8 +88,11 @@ /* North Bridge GPIO selection regsiter */ #define MVEBU_NB_GPIO_SEL_REG (MVEBU_NB_GPIO_REG_BASE + 0x30) +#define MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG (MVEBU_NB_GPIO_REG_BASE + 0x04) /* I2C1 GPIO Enable bit offset */ #define MVEBU_GPIO_TW1_GPIO_EN_OFF (10) +/* SPI pins mode bit offset */ +#define MVEBU_GPIO_NB_SPI_PIN_MODE_OFF (28) /******************************************************************************* * DRAM registers related constants |