io-decode: a3700: update IO decode window configuration in ATF

- Now in ATF IO decode windows are configured according to CPU DRAM
  decode window; For 4GB dram board, there are 4 CPU DRAM decode
  windows, the IO decode window number is smaller than 4(some IO has 2
  decode windows while other IOs has 3 decode windows), then 4 CPU DRAM
  windows can not be configured for IO all;
- This patch only fill the first IO decode window with base(0) and size
  (4GB) when CPU DRAM windows number exceeds the IO decode windows max
  number.

Change-Id: Ic386c85fae11c3d6381c738e37ade261382cfce0
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38868
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>

1 files changed, 51 insertions, 31 deletions

diff --git a/plat/marvell/a3700/common/io_addr_dec.c b/plat/marvell/a3700/common/io_addr_dec.c
index 73a5883f..41c5c2b8 100644
--- a/plat/marvell/a3700/common/io_addr_dec.c
+++ b/plat/marvell/a3700/common/io_addr_dec.c
@@ -53,13 +53,49 @@
 /* There are up to 14 IO unit which need address deocode in Armada-3700 */
 #define IO_UNIT_NUM_MAX				(14)
 
+#define MVEBU_MAX_ADDRSS_4GB			(0x100000000ULL)
+
+
+static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, uintptr_t win_size, struct dec_win_config *dec_win)
+{
+	uint32_t ctrl = 0;
+	uint32_t base = 0;
+
+	/* set size */
+	ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << MVEBU_DEC_WIN_CTRL_SIZE_OFF;
+	/* set attr according to IO decode window */
+	ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF;
+	/* set target */
+	ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF;
+	/* set base */
+	base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << MVEBU_DEC_WIN_BASE_OFF;
+
+	/* set base address*/
+	mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base);
+	/* set remap window, some unit does not have remap window */
+	if (win_id < dec_win->max_remap)
+		mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base);
+	/* set control register */
+	mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl);
+	/* enable the address decode window at last to make it effective */
+	ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF;
+	mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl);
+
+	INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)",
+	     win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset)),
+	     mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset)));
+	if (win_id < dec_win->max_remap)
+		INFO(" remap(%x)\n",
+		     mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset)));
+	else
+		INFO("\n");
+}
+
 /* Set io decode window */
 static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config *dec_win)
 {
 	struct dram_win *win;
 	int id;
-	uint32_t ctrl = 0;
-	uint32_t base = 0;
 
 	/* disable all windows first */
 	for (id = 0; id < dec_win->max_win; id++)
@@ -68,37 +104,21 @@ static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config *
 	/* configure IO decode windows for DRAM, inheritate DRAM size, base and target from CPU-DRAM
 	 * decode window, and others from hard coded IO decode window settings array.
 	 */
-	for (id = 0; id < win_map->dram_win_num && id < dec_win->max_win; id++, win++) {
+	if (win_map->dram_win_num > dec_win->max_win) {
+		/*
+		* If cpu dram windows number exceeds the io decode windows max number,
+		* then fill the first io decode window with base(0) and size(4GB).
+		*/
+		set_io_addr_dec_win(0, 0, MVEBU_MAX_ADDRSS_4GB, dec_win);
+
+		return 0;
+	}
+
+	for (id = 0; id < win_map->dram_win_num; id++, win++) {
 		win = &win_map->dram_windows[id];
-		/* set size */
-		ctrl = ((win->win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << MVEBU_DEC_WIN_CTRL_SIZE_OFF;
-		/* set attr according to IO decode window */
-		ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF;
-		/* set target */
-		ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF;
-		/* set base */
-		base = (win->base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << MVEBU_DEC_WIN_BASE_OFF;
-
-		/* set base address*/
-		mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, id, dec_win->win_offset), base);
-		/* set remap window, some unit does not have remap window */
-		if (id < dec_win->max_remap)
-			mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, id, dec_win->win_offset), base);
-		/* set control register */
-		mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset), ctrl);
-		/* enable the address decode window at last to make it effective */
-		ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF;
-		mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset), ctrl);
-
-		INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)",
-		     id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset)),
-		     mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, id, dec_win->win_offset)));
-		if (id < dec_win->max_remap)
-			INFO(" remap(%x)\n",
-			     mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, id, dec_win->win_offset)));
-		else
-			INFO("\n");
+		set_io_addr_dec_win(id, win->base_addr, win->win_size, dec_win);
 	}
+
 	return 0;
 }