diff options
| author | Igal Liberman <igall@marvell.com> | 2017-05-18 18:38:58 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-05-21 09:58:26 +0300 |
| commit | e1cc0406a8c9b0eb0c53b0d75897face535b8496 (patch) | |
| tree | 432b01726cf1d0a1ca6d468ba711b84087cf8c26 | |
| parent | c721c97f7ea0724d3eaed92168897db4fc1b9b03 (diff) | |
fix: pcie: temporarily disable pcie clock fix
After commit "f82b49e fix: pcie: cp110: fix pcie clock selection"
we encountered some instabilities in PCIe.
This patch disables the PCIe clock fix temporarily,
until we figure out the root cause for this this issue.
Change-Id: I521e4495118fab2bcbe1e99e6080d1cbb2b08f39
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39663
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | drivers/marvell/mochi/cp110_setup.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index 579dc9f7..fcbd16ae 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -310,6 +310,12 @@ void cp110_pcie_clk_cfg(int cp_index) mmio_write_32(MVEBU_PCIE_REF_CLK_BUF_CTRL(cp_index), reg); } +#if 0 + /* + * TODO: Some instabilities in PCIe occur after introducing this code. + * Until we understand the root cause of this issue, + * disable it temporarily. + */ /* CP110 revision A1 */ if (cp110_rev_id_get() == MVEBU_CP110_REF_ID_A1) { if (!pcie0_clk || !pcie1_clk) { @@ -323,6 +329,7 @@ void cp110_pcie_clk_cfg(int cp_index) mmio_write_32(MVEBU_CP_MSS_DPSHSR_REG(cp_index), reg); } } +#endif } /* Set a unique stream id for all DMA capable devices */ |