diff options
| author | Igal Liberman <igall@marvell.com> | 2017-07-12 18:20:05 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-07-19 10:10:36 +0300 |
| commit | 1bf6d8d27667efd86d5f811c9d7540d05ff18aff (patch) | |
| tree | d377c31aaad3d535957f4cdd42c50b1d7cbcfb85 | |
| parent | 61ab2e1ea46a8d848e96ab67ad4a4bc50c3f14dc (diff) | |
fix: mvebu: pcie_dw: set preset request vector to preset4
This preset is used during the initial part of the equalization
master phase. According to hardware measurements, our PCIe hardware
can use preset4 or preset6. However, when we try both preset4 and
preset6, we might get timeouts, which may cause failure for PCIe
endpoint operation.
This patch updates the MAC and the PHY to use only preset4.
This solves an issue, observed when A7040 PCAC opernates as NIC
in a PC (inmod of SNIC module fails).
Change-Id: I056cc2ddf93eed937539d3417611f1b16a6aea38
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/41771
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/41814
| -rw-r--r-- | drivers/marvell/dw-pcie-ep.c | 2 | ||||
| -rw-r--r-- | drivers/marvell/pcie-comphy-cp110.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/marvell/dw-pcie-ep.c b/drivers/marvell/dw-pcie-ep.c index b93f3e79..f733e0a9 100644 --- a/drivers/marvell/dw-pcie-ep.c +++ b/drivers/marvell/dw-pcie-ep.c @@ -154,7 +154,7 @@ void dw_pcie_configure(uintptr_t regs_base, uint32_t cap_speed) * presets to evaluate during the link equalization training to preset4. */ reg &= ~GEN3_EQ_PSET_REQ_VEC_MASK; - reg |= 0x50 << GEN3_EQ_PSET_REQ_VEC_OFFSET; + reg |= 0x10 << GEN3_EQ_PSET_REQ_VEC_OFFSET; mmio_write_32(regs_base + PCIE_GEN3_EQU_CTRL, reg); /* diff --git a/drivers/marvell/pcie-comphy-cp110.c b/drivers/marvell/pcie-comphy-cp110.c index e36e7b14..b1b06845 100644 --- a/drivers/marvell/pcie-comphy-cp110.c +++ b/drivers/marvell/pcie-comphy-cp110.c @@ -410,7 +410,7 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw) mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; - data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; + data |= 0x1 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); if (!hw->is_end_point) { |