fix: pcie: cp110: update analog parameters according to latest ETP

Add PCIE analog parameters initialization values according to
latest ETP.

Change-Id: I3f5892702610e46ebaba7485e3cef5817f1518b5
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/36995
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39411
Reviewed-on: http://vgitil04.il.marvell.com:8080/39490

2 files changed, 109 insertions, 5 deletions

diff --git a/drivers/marvell/comphy.h b/drivers/marvell/comphy.h
index 67807c49..b58fc071 100644
--- a/drivers/marvell/comphy.h
+++ b/drivers/marvell/comphy.h
@@ -159,7 +159,13 @@
 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET	10
 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK	(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
 
-#define HPIPE_G2_SETTINGS_1_REG			0x040
+#define HPIPE_G2_SET_1_REG			0x040
+#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET	0
+#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK	(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET	3
+#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK	(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET	6
+#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK	(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
 
 #define HPIPE_G3_SETTINGS_1_REG			0x048
 #define HPIPE_G3_RX_SELMUPI_OFFSET		0
@@ -178,6 +184,8 @@
 #define HPIPE_INTERFACE_REG			0x94
 #define HPIPE_INTERFACE_GEN_MAX_OFFSET		10
 #define HPIPE_INTERFACE_GEN_MAX_MASK		(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
+#define HPIPE_INTERFACE_DET_BYPASS_OFFSET	12
+#define HPIPE_INTERFACE_DET_BYPASS_MASK		(0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET	14
 #define HPIPE_INTERFACE_LINK_TRAIN_MASK		(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
 
@@ -195,6 +203,10 @@
 
 #define HPIPE_VTHIMPCAL_CTRL_REG                0x104
 
+#define HPIPE_VDD_CAL_CTRL_REG			0x114
+#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET		5
+#define HPIPE_EXT_SELLV_RXSAMPL_MASK		(0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
+
 #define HPIPE_PCIE_REG0                         0x120
 #define HPIPE_PCIE_IDLE_SYNC_OFFSET		12
 #define HPIPE_PCIE_IDLE_SYNC_MASK		(0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
@@ -247,6 +259,10 @@
 
 #define HPIPE_RX_REG3				0x188
 
+#define HPIPE_FRAME_DET_CONTROL_REG		0x220
+#define HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET	12
+#define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK	(0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET)
+
 #define HPIPE_TX_TRAIN_CTRL_0_REG		0x268
 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET		15
 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK		(0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
@@ -282,6 +298,14 @@
 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET	7
 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK	(0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
 
+#define HPIPE_CDR_CONTROL_REG			0x418
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET	12
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK	(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
+#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET	9
+#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK		(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
+#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET	6
+#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK		(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
+
 #define HPIPE_TX_TRAIN_CTRL_11_REG		0x438
 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET	6
 #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK	(0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
@@ -299,7 +323,10 @@
 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK	(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
 
 #define HPIPE_G2_SETTINGS_3_REG			0x448
+
 #define HPIPE_G2_SETTINGS_4_REG			0x44C
+#define HPIPE_G2_DFE_RES_OFFSET			8
+#define HPIPE_G2_DFE_RES_MASK			(0x3 << HPIPE_G2_DFE_RES_OFFSET)
 
 #define HPIPE_G3_SETTING_3_REG			0x450
 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET	12
@@ -311,6 +338,10 @@
 #define HPIPE_G3_DFE_RES_OFFSET			8
 #define HPIPE_G3_DFE_RES_MASK			(0x3 << HPIPE_G3_DFE_RES_OFFSET)
 
+#define HPIPE_DFE_CONTROL_REG			0x470
+#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET	14
+#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK		(0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
+
 #define HPIPE_DFE_CTRL_28_REG			0x49C
 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET		7
 #define HPIPE_DFE_CTRL_28_PIPE4_MASK		(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
@@ -319,6 +350,10 @@
 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET	0
 #define HPIPE_G1_SETTING_5_G1_ICP_MASK		(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
 
+#define HPIPE_G3_SETTING_5_REG			0x548
+#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET	0
+#define HPIPE_G3_SETTING_5_G3_ICP_MASK		(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
+
 #define HPIPE_LANE_CONFIG0_REG			0x600
 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET	0
 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK	(0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
@@ -336,6 +371,8 @@
 #define HPIPE_LANE_CFG4_REG                     0x620
 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET		0
 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK		(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
+#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET	3
+#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK		(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
 #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET		6
 #define HPIPE_LANE_CFG4_DFE_OVER_MASK		(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
 #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET		7
@@ -349,6 +386,14 @@
 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET	12
 #define HPIPE_CFG_UPDATE_POLARITY_MASK		(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
 
+#define HPIPE_LANE_EQ_REMOTE_SETTING_REG	0x6f8
+#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET	0
+#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK	(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
+#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET	1
+#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK	(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
+#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET	2
+#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK	(0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
+
 #define HPIPE_RST_CLK_CTRL_REG			0x704
 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET	0
 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK	(0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
diff --git a/drivers/marvell/pcie-comphy-cp110.c b/drivers/marvell/pcie-comphy-cp110.c
index cdfb8876..e36e7b14 100644
--- a/drivers/marvell/pcie-comphy-cp110.c
+++ b/drivers/marvell/pcie-comphy-cp110.c
@@ -208,6 +208,8 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw)
 		mask |= HPIPE_MISC_REFCLK_SEL_MASK;
 		data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
 	}
+	mask |= HPIPE_MISC_ICP_FORCE_MASK;
+	data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
 	if (hw->clk_out) { /* output */
 		/* Set reference frequcency select - 0x2 for 25MHz*/
@@ -239,6 +241,9 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw)
 	/* Set Maximal PHY Generation Setting(8Gbps) */
 	mask = HPIPE_INTERFACE_GEN_MAX_MASK;
 	data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
+	/* Bypass frame detection and sync detection for RX DATA */
+	mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
+	data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
 	/* Set Link Train Mode (Tx training control pins are used) */
 	mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
 	data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
@@ -323,9 +328,9 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw)
 	data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
 
-	/* Force DFE resolution (use GEN table value) */
+	/* Use TX/RX training result for DFE */
 	mask = HPIPE_DFE_RES_FORCE_MASK;
-	data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
+	data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
 	reg_set(hpipe_addr + HPIPE_DFE_REG0,  data, mask);
 
 	/* Configure initial and final coefficient value for receiver */
@@ -349,11 +354,65 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw)
 	/* FFE resistor tuning for different bandwidth  */
 	mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
 	data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
-
 	mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
-	data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
+	data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
 
+	/* Pattern lock lost timeout disable */
+	mask = HPIPE_FRAME_DET_LOCK_LOST_TO_MASK;
+	data = 0x0 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET;
+	reg_set(hpipe_addr + HPIPE_FRAME_DET_CONTROL_REG, data, mask);
+
+	/* Configure DFE adaptations */
+	mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
+	data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
+	mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
+	data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
+	mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
+	data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
+	reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
+	mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
+	data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
+	reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
+
+	/* Genration 2 setting 1*/
+	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
+	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
+	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
+	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
+	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
+	reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
+
+	/* DFE enable */
+	mask = HPIPE_G2_DFE_RES_MASK;
+	data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
+	reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
+
+	/* Configure DFE Resolution */
+	mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
+	data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
+
+	/* VDD calibration control */
+	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
+	data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
+	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
+
+	/* Set PLL Charge-pump Current Control */
+	mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
+	data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
+	reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
+
+	/* Set lane rqualization remote setting */
+	mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
+	data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
+	mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
+	data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
+	mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
+	data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
+
 	if (!hw->is_end_point) {
 		/* Set phy in root complex mode */
 		mask = HPIPE_CFG_PHY_RC_EP_MASK;