script: a3700: add static startup scripts for XDB

This patch adds static startup XDB scripts for Armada37x0:
- The DDR will be initialized, but only the first 512MB, which is
  good enough for board recovery
- The first dram cpu decoder window size will be set;
- BL1 and FIP will be loaded and executed by default.

Change-Id: I4ec4cdb7dcded4d9757fa647d00c977ab4de3b63
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39249
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

4 files changed, 466 insertions, 0 deletions

diff --git a/scripts/debugger/a3700/a3700_cpu_decwin.xdb b/scripts/debugger/a3700/a3700_cpu_decwin.xdb
new file mode 100644
index 00000000..9f7e3f0c
--- /dev/null
+++ b/scripts/debugger/a3700/a3700_cpu_decwin.xdb
@@ -0,0 +1,17 @@
+! -----------------------------------------------------------------------
+!  MARVELL INTERNATIONAL LTD., ON BEHALF OF ITSELF AND ITS WORLDWIDE
+! AFFILIATES(COLLECTIVELY, "MARVELL"), MAKES NO WARRANTY OF ANY KIND WITH
+! REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+! OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+! MARVELL ASSUMES NO RESPONSIBILITY FOR ANY ERRORS THAT MAY
+! APPEAR IN THIS DOCUMENT. MARVELL MAKES NO COMMITMENT TO
+! UPDATE NOR TO KEEP CURRENT THE INFORMATION CONTAINED IN THIS DOCUMENT.
+! -----------------------------------------------------------------------
+!
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Set the first dram cpu decoder window size
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:3(0xC000CF00)=0x00000000
+! the window size should be set to 2GB with value of 0x00007FFF if the total dram size is over 2GB.
+SET VALUE /SIZE=LONG CORE:3(0xC000CF04)=0x00001FFF
+SET VALUE /SIZE=LONG CORE:3(0xC000CF00)=0x00000001
diff --git a/scripts/debugger/a3700/a3700_ddr3_cpu_600_ddr_600.xdb b/scripts/debugger/a3700/a3700_ddr3_cpu_600_ddr_600.xdb
new file mode 100644
index 00000000..2e1f1f99
--- /dev/null
+++ b/scripts/debugger/a3700/a3700_ddr3_cpu_600_ddr_600.xdb
@@ -0,0 +1,176 @@
+! -----------------------------------------------------------------------
+!  MARVELL INTERNATIONAL LTD., ON BEHALF OF ITSELF AND ITS WORLDWIDE
+! AFFILIATES(COLLECTIVELY, "MARVELL"), MAKES NO WARRANTY OF ANY KIND WITH
+! REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+! OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+! MARVELL ASSUMES NO RESPONSIBILITY FOR ANY ERRORS THAT MAY
+! APPEAR IN THIS DOCUMENT. MARVELL MAKES NO COMMITMENT TO
+! UPDATE NOR TO KEEP CURRENT THE INFORMATION CONTAINED IN THIS DOCUMENT.
+! -----------------------------------------------------------------------
+!
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Switch all clocks to REFCLOCK
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013010)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0018010)=0x00000000
+
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! TBG-A: SE vco_div)=0x0,
+! DIFF vco_div)=0x1, vco_range)=0xd
+! tbg_N)=0x48 KVCO = 2400 MHz
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00C00091
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00C00121
+SET VALUE /SIZE=LONG CORE:1(0xD0013220)=0x08030803
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x94011401
+SET VALUE /SIZE=LONG CORE:1(0xD0013230)=0x00020002
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x94011401
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x53E556E6
+SET VALUE /SIZE=LONG CORE:1(0xD0013210)=0x014A014D
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x53E556E6
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00C00120
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x94011401
+
+DEFINE SYMBOL /TYPE="unsigned int" /ADDRESS=0xD0013208 TestVal
+
+WHILE TestVal & 0x80008000 != 0x80008000 THEN
+    TCI DELAY 1
+END
+TCI DELAY 1
+
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! TBG-B: SE vco_div)=0x1,
+! DIFF vco_div)=0x1, vco_range)=0xb
+! tbg_N)=0x3c KVCO = 2000 MHz
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00C10120
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F10120
+SET VALUE /SIZE=LONG CORE:1(0xD0013220)=0x08030803
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x14019401
+SET VALUE /SIZE=LONG CORE:1(0xD0013230)=0x00020002
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x14019401
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x56E556E6
+SET VALUE /SIZE=LONG CORE:1(0xD0013210)=0x014B014D
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x56E656E6
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F00120
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x14019401
+
+WHILE TestVal & 0x80008000 != 0x80008000 THEN
+    TCI DELAY 1
+END
+TCI DELAY 1
+
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Set clocks to 600/600 preset
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013014)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0013004)=0x2326202A
+SET VALUE /SIZE=LONG CORE:1(0xD0013008)=0x1A09AAA9
+SET VALUE /SIZE=LONG CORE:1(0xD001300C)=0x208B3482
+SET VALUE /SIZE=LONG CORE:1(0xD0013000)=0x0333C0FE
+SET VALUE /SIZE=LONG CORE:1(0xD0018014)=0x00180000
+SET VALUE /SIZE=LONG CORE:1(0xD0018004)=0x053154C8
+SET VALUE /SIZE=LONG CORE:1(0xD0018008)=0x00307880
+SET VALUE /SIZE=LONG CORE:1(0xD001800C)=0x00000940
+SET VALUE /SIZE=LONG CORE:1(0xD0018000)=0x003F8F40
+SET VALUE /SIZE=LONG CORE:1(0xD0013210)=0x0014B014D
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Switch all clocks to back dividers
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013010)=0x00009FFF
+SET VALUE /SIZE=LONG CORE:1(0xD0018010)=0x000007AA
+
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Running DDR initialization in 600MHz mode
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! DDR MAC init
+SET VALUE /SIZE=LONG CORE:1(0xD0014008)=0x00404500
+SET VALUE /SIZE=LONG CORE:1(0xD0002000)=0x00010000
+SET VALUE /SIZE=LONG CORE:1(0xD0002004)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000340)=0x0f0f0fef
+SET VALUE /SIZE=LONG CORE:1(0xD0000344)=0x100000aa
+SET VALUE /SIZE=LONG CORE:1(0xD0000310)=0x200000
+SET VALUE /SIZE=LONG CORE:1(0xD0000304)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0000308)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0000200)=0xD0001
+SET VALUE /SIZE=LONG CORE:1(0xD0000204)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0000220)=0x13020532
+SET VALUE /SIZE=LONG CORE:1(0xD0000044)=0x30200
+SET VALUE /SIZE=LONG CORE:1(0xD00002c0)=0x6000
+SET VALUE /SIZE=LONG CORE:1(0xD00002c4)=0x00100020
+SET VALUE /SIZE=LONG CORE:1(0xD0000058)=0x143f
+SET VALUE /SIZE=LONG CORE:1(0xD0000048)=0x1
+SET VALUE /SIZE=LONG CORE:1(0xD0000180)=0x00010200
+SET VALUE /SIZE=LONG CORE:1(0xD0000050)=0x1ff
+SET VALUE /SIZE=LONG CORE:1(0xD000004c)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0000054)=0x480
+SET VALUE /SIZE=LONG CORE:1(0xD0000300)=0x708
+SET VALUE /SIZE=LONG CORE:1(0xD0000380)=0x1f5
+SET VALUE /SIZE=LONG CORE:1(0xD0000384)=0x3e9
+SET VALUE /SIZE=LONG CORE:1(0xD0000388)=0x9600043
+SET VALUE /SIZE=LONG CORE:1(0xD000038c)=0x200
+SET VALUE /SIZE=LONG CORE:1(0xD0000390)=0x400100
+SET VALUE /SIZE=LONG CORE:1(0xD0000394)=0x6b03cf
+SET VALUE /SIZE=LONG CORE:1(0xD0000398)=0x720200
+SET VALUE /SIZE=LONG CORE:1(0xD000039c)=0x120707
+SET VALUE /SIZE=LONG CORE:1(0xD00003a0)=0x40511
+SET VALUE /SIZE=LONG CORE:1(0xD00003a4)=0x1
+SET VALUE /SIZE=LONG CORE:1(0xD00003a8)=0xc04
+SET VALUE /SIZE=LONG CORE:1(0xD00003ac)=0x15210919
+SET VALUE /SIZE=LONG CORE:1(0xD00003b0)=0x90b0609
+SET VALUE /SIZE=LONG CORE:1(0xD00003b4)=0x4000600
+SET VALUE /SIZE=LONG CORE:1(0xD00003b8)=0x600
+SET VALUE /SIZE=LONG CORE:1(0xD00003bc)=0x2020404
+SET VALUE /SIZE=LONG CORE:1(0xD00003c0)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00003c4)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00003dc)=0x81239
+SET VALUE /SIZE=LONG CORE:1(0xD00002c8)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0000064)=0x0006
+SET VALUE /SIZE=LONG CORE:1(0xD0000044)=0x00030200
+! DDR PHY init
+SET VALUE /SIZE=LONG CORE:1(0xD0001004)=0x10077779
+SET VALUE /SIZE=LONG CORE:1(0xD0001008)=0x1ff00770
+SET VALUE /SIZE=LONG CORE:1(0xD000100c)=0x3f03fc77
+SET VALUE /SIZE=LONG CORE:1(0xD0001010)=0x100118
+SET VALUE /SIZE=LONG CORE:1(0xD0001028)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0001030)=0x3800000
+SET VALUE /SIZE=LONG CORE:1(0xD0001034)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0001040)=0x400
+SET VALUE /SIZE=LONG CORE:1(0xD00010c0)=0x80000001
+SET VALUE /SIZE=LONG CORE:1(0xD00010d0)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00010e0)=0x11ff0
+SET VALUE /SIZE=LONG CORE:1(0xD0001090)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0001094)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0001098)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD000109c)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00010a0)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00010a4)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00010a8)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00010ac)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD00010b0)=0x0
+SET VALUE /SIZE=LONG CORE:1(0xD0001000)=0x44041
+SET VALUE /SIZE=LONG CORE:1(0xD0001014)=0x80200
+SET VALUE /SIZE=LONG CORE:1(0xD0001038)=0x2
+SET VALUE /SIZE=LONG CORE:1(0xD000103c)=0x10
+SET VALUE /SIZE=LONG CORE:1(0xD0001180)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD0001184)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD0001188)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD000118c)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD0001190)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD0001194)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD0001198)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD000119c)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD00011a0)=0x20a
+SET VALUE /SIZE=LONG CORE:1(0xD0001050)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001054)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001058)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD000105c)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001060)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001064)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001068)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD000106c)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001070)=0x8080000
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x20000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x40000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x80000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000020)=0x11000001
diff --git a/scripts/debugger/a3700/a3700_ddr4_cpu_1000_ddr_800.xdb b/scripts/debugger/a3700/a3700_ddr4_cpu_1000_ddr_800.xdb
new file mode 100644
index 00000000..ad8b613b
--- /dev/null
+++ b/scripts/debugger/a3700/a3700_ddr4_cpu_1000_ddr_800.xdb
@@ -0,0 +1,203 @@
+! -----------------------------------------------------------------------
+!  MARVELL INTERNATIONAL LTD., ON BEHALF OF ITSELF AND ITS WORLDWIDE
+! AFFILIATES(COLLECTIVELY, "MARVELL"), MAKES NO WARRANTY OF ANY KIND WITH
+! REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+! OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+! MARVELL ASSUMES NO RESPONSIBILITY FOR ANY ERRORS THAT MAY
+! APPEAR IN THIS DOCUMENT. MARVELL MAKES NO COMMITMENT TO
+! UPDATE NOR TO KEEP CURRENT THE INFORMATION CONTAINED IN THIS DOCUMENT.
+! -----------------------------------------------------------------------
+!
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Switch all clocks to REFCLOCK
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013010)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0018010)=0x00000000
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! TBG-A: SE vco_div=0x1,
+! DIFF vco_div=0x1, vco_range=0xa
+! tbg_N=0x30 KVCO = 1600 MHz
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F00091
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F000C1
+SET VALUE /SIZE=LONG CORE:1(0xD0013220)=0x08030803
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x94011400
+SET VALUE /SIZE=LONG CORE:1(0xD0013230)=0x00040002
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x94011400
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x56E656E5
+SET VALUE /SIZE=LONG CORE:1(0xD0013210)=0x014B014A
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x56E656E5
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F000C0
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x94011400
+
+DEFINE SYMBOL /TYPE="unsigned int" /ADDRESS=0xD0013208 TestVal
+
+WHILE TestVal & 0x80008000 != 0x80008000 THEN
+    TCI DELAY 1
+END
+TCI DELAY 1
+
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! TBG-B: SE vco_div=0x1,
+! DIFF vco_div=02, vco_range=0xb
+! tbg_N=0x3c KVCO = 2000 MHz
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F100C0
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F100C0
+SET VALUE /SIZE=LONG CORE:1(0xD0013220)=0x08030803
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x14019400
+SET VALUE /SIZE=LONG CORE:1(0xD0013230)=0x00040002
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x14019400
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x56E656E5
+SET VALUE /SIZE=LONG CORE:1(0xD0013210)=0x014B014A
+SET VALUE /SIZE=LONG CORE:1(0xD001320C)=0x56E656E5
+SET VALUE /SIZE=LONG CORE:1(0xD0013204)=0x00F000C0
+SET VALUE /SIZE=LONG CORE:1(0xD0013208)=0x14019400
+
+WHILE TestVal & 0x80008000 != 0x80008000 THEN
+    TCI DELAY 1
+END
+TCI DELAY 1
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Set clocks to 1000/800 preset
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013014)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0013004)=0x1296202C
+SET VALUE /SIZE=LONG CORE:1(0xD0013008)=0x21061AA9
+SET VALUE /SIZE=LONG CORE:1(0xD001300C)=0x20543082
+SET VALUE /SIZE=LONG CORE:1(0xD0013000)=0x03CFCCF2
+SET VALUE /SIZE=LONG CORE:1(0xD0018014)=0x00180000
+SET VALUE /SIZE=LONG CORE:1(0xD0018004)=0x02515508
+SET VALUE /SIZE=LONG CORE:1(0xD0018008)=0x00300880
+SET VALUE /SIZE=LONG CORE:1(0xD001800C)=0x00000540
+SET VALUE /SIZE=LONG CORE:1(0xD0018000)=0x003F8F40
+SET VALUE /SIZE=LONG CORE:1(0xD0013210)=0x0014B014A
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Switch all clocks to back dividers
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+SET VALUE /SIZE=LONG CORE:1(0xD0013010)=0x00009FFF
+SET VALUE /SIZE=LONG CORE:1(0xD0018010)=0x000007AA
+
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Running DDR initialization in 1600MHz mode
+!+++++++++++++++++++++++++++++++++++++++++++++++++
+! Pre-init
+SET VALUE /SIZE=LONG CORE:1(0xD0014008)=0x00404500
+SET VALUE /SIZE=LONG CORE:1(0xD0002000)=0x00010000
+SET VALUE /SIZE=LONG CORE:1(0xD0002004)=0x00000000
+! DDR MAC init
+SET VALUE /SIZE=LONG CORE:1(0xD0000340)=0x00000303
+SET VALUE /SIZE=LONG CORE:1(0xD0000344)=0x0000000A
+SET VALUE /SIZE=LONG CORE:1(0xD0000310)=0x00100000
+SET VALUE /SIZE=LONG CORE:1(0xD0000304)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000308)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000200)=0x000D0001
+SET VALUE /SIZE=LONG CORE:1(0xD0000204)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000220)=0x13020535
+SET VALUE /SIZE=LONG CORE:1(0xD0000044)=0x00030200
+SET VALUE /SIZE=LONG CORE:1(0xD00002C0)=0x00006000
+SET VALUE /SIZE=LONG CORE:1(0xD00002C4)=0x00000030
+SET VALUE /SIZE=LONG CORE:1(0xD0000058)=0x0000143F
+SET VALUE /SIZE=LONG CORE:1(0xD0000048)=0x00000001
+SET VALUE /SIZE=LONG CORE:1(0xD0000180)=0x00010200
+SET VALUE /SIZE=LONG CORE:1(0xD0000050)=0x000001FF
+SET VALUE /SIZE=LONG CORE:1(0xD000004C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000054)=0x00000480
+SET VALUE /SIZE=LONG CORE:1(0xD0000300)=0x00000B0C
+SET VALUE /SIZE=LONG CORE:1(0xD0000380)=0x00000258
+SET VALUE /SIZE=LONG CORE:1(0xD0000384)=0x000004B0
+SET VALUE /SIZE=LONG CORE:1(0xD0000388)=0x00000050
+SET VALUE /SIZE=LONG CORE:1(0xD000038C)=0x00000400
+SET VALUE /SIZE=LONG CORE:1(0xD0000390)=0x00800200
+SET VALUE /SIZE=LONG CORE:1(0xD0000394)=0x00D000C3
+SET VALUE /SIZE=LONG CORE:1(0xD0000398)=0x00D80255
+SET VALUE /SIZE=LONG CORE:1(0xD000039C)=0x00000808
+SET VALUE /SIZE=LONG CORE:1(0xD00003A0)=0x00040500
+SET VALUE /SIZE=LONG CORE:1(0xD00003A4)=0x00000001
+SET VALUE /SIZE=LONG CORE:1(0xD00003A8)=0x00001808
+SET VALUE /SIZE=LONG CORE:1(0xD00003AC)=0x17280C1C
+SET VALUE /SIZE=LONG CORE:1(0xD00003B0)=0x0C0C060C
+SET VALUE /SIZE=LONG CORE:1(0xD00003B4)=0x05040602
+SET VALUE /SIZE=LONG CORE:1(0xD00003B8)=0x00000600
+SET VALUE /SIZE=LONG CORE:1(0xD00003BC)=0x02020404
+SET VALUE /SIZE=LONG CORE:1(0xD00003C0)=0x00020205
+SET VALUE /SIZE=LONG CORE:1(0xD00003C4)=0x00000003
+SET VALUE /SIZE=LONG CORE:1(0xD00003DC)=0x00081239
+SET VALUE /SIZE=LONG CORE:1(0xD00002C8)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000064)=0x00000006
+! DDR PHY init
+SET VALUE /SIZE=LONG CORE:1(0xD0001014)=0x00080200
+SET VALUE /SIZE=LONG CORE:1(0xD0001038)=0x00000003
+SET VALUE /SIZE=LONG CORE:1(0xD000103C)=0x00000020
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x80000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001000)=0x00004032
+SET VALUE /SIZE=LONG CORE:1(0xD0001004)=0xD0277AA9
+SET VALUE /SIZE=LONG CORE:1(0xD0001008)=0xC770055D
+SET VALUE /SIZE=LONG CORE:1(0xD000100C)=0x5061DF77
+SET VALUE /SIZE=LONG CORE:1(0xD0001010)=0x00100100
+SET VALUE /SIZE=LONG CORE:1(0xD0001014)=0x00080200
+SET VALUE /SIZE=LONG CORE:1(0xD000101C)=0x90118011
+SET VALUE /SIZE=LONG CORE:1(0xD0001028)=0x00000011
+SET VALUE /SIZE=LONG CORE:1(0xD0001030)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001034)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001038)=0x72150002
+SET VALUE /SIZE=LONG CORE:1(0xD0001040)=0x00000607
+SET VALUE /SIZE=LONG CORE:1(0xD00010C0)=0x51000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001140)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001144)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001148)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000114C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001150)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001154)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001158)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000115C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001180)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001184)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001188)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000118C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001190)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001194)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001198)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000119C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001050)=0x15150000
+SET VALUE /SIZE=LONG CORE:1(0xD0001054)=0x20100000
+SET VALUE /SIZE=LONG CORE:1(0xD0001074)=0x15150000
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x20000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x40000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001020)=0x80000000
+SET VALUE /SIZE=LONG CORE:1(0xD0000020)=0x13000001
+SET VALUE /SIZE=LONG CORE:1(0xD0000024)=0x13000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010E0)=0x00010010
+SET VALUE /SIZE=LONG CORE:1(0xD00010D0)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010D4)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010D8)=0x0006BDAF
+SET VALUE /SIZE=LONG CORE:1(0xD00010DC)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010E0)=0x00010020
+SET VALUE /SIZE=LONG CORE:1(0xD00010D0)=0x06BC0000
+SET VALUE /SIZE=LONG CORE:1(0xD00010D4)=0x000001AF
+SET VALUE /SIZE=LONG CORE:1(0xD00010D8)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010DC)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001090)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001094)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001098)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000109C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010A0)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010A4)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010A8)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010AC)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD00010B0)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001058)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000105C)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001060)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001064)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD0001068)=0x00000000
+SET VALUE /SIZE=LONG CORE:1(0xD000106C)=0x00000000
+! Trigger DDR init for channel 0
+SET VALUE /SIZE=LONG CORE:1(0xD0000020)=0x11000001
+
+!WAIT_FOR_BIT_SET: 0xD0000008 0x00000001 0x00001000
+DEFINE SYMBOL /TYPE="unsigned int" /ADDRESS=0xD0000008 DdrInit
+
+WHILE DdrInit & 0x00000001 != 0x00000001 THEN
+    TCI DELAY 1
+END
diff --git a/scripts/debugger/a3700/a3700_static.xdb b/scripts/debugger/a3700/a3700_static.xdb
new file mode 100644
index 00000000..9b89c95a
--- /dev/null
+++ b/scripts/debugger/a3700/a3700_static.xdb
@@ -0,0 +1,70 @@
+! -----------------------------------------------------------------------
+!  MARVELL INTERNATIONAL LTD., ON BEHALF OF ITSELF AND ITS WORLDWIDE
+! AFFILIATES(COLLECTIVELY, "MARVELL"), MAKES NO WARRANTY OF ANY KIND WITH
+! REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+! OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+! MARVELL ASSUMES NO RESPONSIBILITY FOR ANY ERRORS THAT MAY
+! APPEAR IN THIS DOCUMENT. MARVELL MAKES NO COMMITMENT TO
+! UPDATE NOR TO KEEP CURRENT THE INFORMATION CONTAINED IN THIS DOCUMENT.
+! -----------------------------------------------------------------------
+! creation date: Mon June 26 10:00:00 2016
+
+
+! Run DDR initialization, need to set full path in Windows
+set val /size=byte @DDR_INIT_SCRIPT_PATH="EMPTY"
+! set val /size=byte @DDR_INIT_SCRIPT_PATH="a3700_ddr3_cpu_600_ddr_600.xdb"
+! set val /size=byte @DDR_INIT_SCRIPT_PATH="a3700_ddr4_cpu_1000_ddr_800.xdb"
+if (@strcmp(@DDR_INIT_SCRIPT_PATH,"EMPTY")==0) then
+	set value @DDR_INIT_SCRIPT_PATH = @queryinputfile("select DDR init file", "all files (*.*)|*.*");
+end
+BATCH @DDR_INIT_SCRIPT_PATH
+
+! Set the first dram cpu decoder window size;
+BATCH "a3700_cpu_decwin.xdb"
+
+! Load FIP, Need update full image path if do not want to select FIP by GUI window
+set val /size=byte @ATF_FIP_BIN_PATH="EMPTY"
+! set val /size=byte @ATF_FIP_BIN_PATH="fip.bin"
+if (@strcmp(@ATF_FIP_BIN_PATH,"EMPTY")==0) then
+	set value @ATF_FIP_BIN_PATH = @queryinputfile("select FIP bin file", "all files (*.*)|*.*");
+end
+! load fip.bin (loaded by BL1 from 0x4120000)
+LOAD /BINARY /ADDRESS=0x4120000 OF @ATF_FIP_BIN_PATH
+
+
+! Load BL1, Need update full image path if do not want to select BL1 by GUI window
+set val /size=byte @ATF_BL1_BIN_PATH="EMPTY"
+! set val /size=byte @ATF_BL1_BIN_PATH="bl1.bin"
+if (@strcmp(@ATF_BL1_BIN_PATH,"EMPTY")==0) then
+	set value @ATF_BL1_BIN_PATH = @queryinputfile("select BL1 bin file", "all files (*.*)|*.*");
+end
+! load BL1.bin (run from 0x4100000)
+LOAD /BINARY /ADDRESS=0x4100000 OF @ATF_BL1_BIN_PATH
+
+
+! load single boot image including BL1 and FIP (run from 0x4100000), open it when need
+! set val /size=byte @ATF_BOOT_IMG_PATH="EMPTY"
+! set val /size=byte @ATF_BOOT_IMG_PATH="boot-image.bin"
+! if (@strcmp(@ATF_BOOT_IMG_PATH,"EMPTY")==0) then
+!	set value @ATF_BOOT_IMG_PATH = @queryinputfile("select boot image file", "all files (*.*)|*.*");
+! end
+! LOAD /BINARY /ADDRESS=0x04100000 OF @ATF_BOOT_IMG_PATH
+
+
+! Load symbols examples, set correct path and enable them when need
+! Load u-boot symbols
+! LOAD /SEGMENT /DEBUG /GLOBAL /NOLOAD OF "u-boot"
+! Load ATF BL31 symbols
+! LOAD /SEGMENT /DEBUG /GLOBAL /NOLOAD OF "bl31.elf"
+
+
+! Break point examples, set and enable them when need
+! Break at BL1 start
+! SET BREAKPOINT AT CORE:1(0x04100000)
+! Break at BL1 entry point
+! SET BREAKPOINT AT CORE:1(&a3700_pwr_domain_on) HARD 1
+
+
+! Start from BL1
+SET REGISTER PC=0x4100000
+RUN