diff options
| author | Igal Liberman <igall@marvell.com> | 2017-07-17 19:09:50 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-07-19 10:10:20 +0300 |
| commit | 61ab2e1ea46a8d848e96ab67ad4a4bc50c3f14dc (patch) | |
| tree | d9f1d84c28e4509c29efe97778776e53eaeda3de | |
| parent | 46ddc17ce940cbdf216f3db66a69107fa4af1f95 (diff) | |
fix: mvebu: pcie_dw: set correct hints to lane equalization register
Currently, we don't modify the default preset values in lane
equalization register which may cause issues with some PCIe GEN3
devices which fail to link up.
According to hardware measurements, we must modify the preset values
to improve PCIe GEN3 link establishment.
Change-Id: Ib93656ee75e6125c0a270550d1fb384111f406f6
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/41770
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/41813
| -rw-r--r-- | drivers/marvell/dw-pcie-ep.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/marvell/dw-pcie-ep.c b/drivers/marvell/dw-pcie-ep.c index 63bccd49..b93f3e79 100644 --- a/drivers/marvell/dw-pcie-ep.c +++ b/drivers/marvell/dw-pcie-ep.c @@ -93,6 +93,10 @@ #define PCIE_SPCIE_NEXT_OFFSET_MASK 0xfff00000 #define PCIE_SPCIE_NEXT_OFFSET_OFFSET 20 +#define PCIE_LANE_EQ_CTRL01_REG 0x164 +#define PCIE_LANE_EQ_CTRL23_REG 0x168 +#define PCIE_LANE_EQ_SETTING 0x55555555 + #define PCIE_TPH_EXT_CAP_HDR_REG 0x1b8 #define PCIE_TPH_REQ_NEXT_PTR_MASK 0xfff00000 #define PCIE_TPH_REQ_NEXT_PTR_OFFSET 20 @@ -107,6 +111,30 @@ void dw_pcie_configure(uintptr_t regs_base, uint32_t cap_speed) { uint32_t reg; + /* + * Set the correct hints for lane equalization. + * + * These registers consist of the following fields: + * - Downstream Port Transmitter Preset - Used for equalization by + * this port when the Port is operating as a downstream Port. + * - Downstream Port Receiver Preset Hint - May be used as a hint + * for receiver equalization by this port when the Port is + * operating as a downstream Port. + * - Upstream Port Transmitter Preset - Field contains the + * transmit preset value sent or received during link + * equalization. + * - Upstream Port Receiver Preset Hint - Field contains the + * receiver preset hint value sent or received during link + * equalization. + * + * The default values for this registers aren't optimal for our + * hardware, so we set the optimal values according to HW measurements. + */ + mmio_write_32(regs_base + PCIE_LANE_EQ_CTRL01_REG, + PCIE_LANE_EQ_SETTING); + mmio_write_32(regs_base + PCIE_LANE_EQ_CTRL23_REG, + PCIE_LANE_EQ_SETTING); + /* Set link to GEN 3 */; reg = mmio_read_32(regs_base + PCIE_LINK_CTL_2); reg &= ~TARGET_LINK_SPEED_MASK; |