diff options
| author | Igal Liberman <igall@marvell.com> | 2017-05-14 18:01:56 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-05-16 10:48:55 +0300 |
| commit | 7b3edce139d92fa6fedabde782a6ccc87e6d8b98 (patch) | |
| tree | 08537fdf86c5d8a5ed237496bb9afcaaa460c6bd | |
| parent | 2a3950769bf2b6f9fb212b699cf8089f655ada54 (diff) | |
fix: mvebu: pcie: set correct preset4 value
Currently, incorrect preset4 value is used.
This patch fixes the preset4 according to HW measurments.
Change-Id: I839a6c843e912182bb0c71e3ab836dac27ce8a97
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39421
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39491
| -rw-r--r-- | drivers/marvell/dw-pcie-ep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/marvell/dw-pcie-ep.c b/drivers/marvell/dw-pcie-ep.c index 7bc40dfd..63bccd49 100644 --- a/drivers/marvell/dw-pcie-ep.c +++ b/drivers/marvell/dw-pcie-ep.c @@ -126,7 +126,7 @@ void dw_pcie_configure(uintptr_t regs_base, uint32_t cap_speed) * presets to evaluate during the link equalization training to preset4. */ reg &= ~GEN3_EQ_PSET_REQ_VEC_MASK; - reg |= 0x10 << GEN3_EQ_PSET_REQ_VEC_OFFSET; + reg |= 0x50 << GEN3_EQ_PSET_REQ_VEC_OFFSET; mmio_write_32(regs_base + PCIE_GEN3_EQU_CTRL, reg); /* |