diff options
| author | Marcin Wojtas <mw@semihalf.com> | 2017-05-06 00:58:05 +0200 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-05-11 15:43:33 +0300 |
| commit | 90f2a7016857cc4f2f94b23a4431263dc8212346 (patch) | |
| tree | 107a4aecf0813fcddd3c2ee0a367522d927b1267 | |
| parent | 308adbec82334125a2c3ff1a808ffe9a1c9f0801 (diff) | |
fix: ap806: enable 48-bit virtual address
Issue found when enable 48-bit Virtual Address in kernel
In ARMv8 the CPU can work with 48-bit virtual address,
at this case for propagating TLB maintenance 44-bit of
Physical address are needed.
Marvell interconnect is configured to be 40-bit address
by default, therefore AxAddr[43:40] are not propagated
so the DVM is not working.
Change-Id: I7b8a3ec7960697814079f2c932fd06962bfa4c75
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39185
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
| -rw-r--r-- | drivers/marvell/mochi/apn806_setup.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 95dff189..03ba5872 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -52,6 +52,9 @@ #define CCU_LTC_CR (MVEBU_CCU_BASE + 0x300) #define CCU_CLEAN_INV_WRITE_OFFSET 8 +#define DSS_CR0 (MVEBU_RFU_BASE + 0x100) +#define DVM_48BIT_VA_ENABLE (1 << 21) + /* Secure MoChi incoming access */ #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) #define SEC_MOCHI_IN_ACC_IHB0_EN (1) @@ -176,6 +179,12 @@ void apn806_axi_attr_init(void) return; } +void dss_setup(void) +{ + /* Enable 48-bit VA */ + mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); +} + void misc_soc_configurations(void) { uint32_t reg; @@ -202,6 +211,9 @@ void apn806_init(void) /* configure CCU windows */ init_ccu(); + /* configure DSS */ + dss_setup(); + /* configure the SMMU */ setup_smmu(); |