diff options
| author | Omri Itach <omrii@marvell.com> | 2017-05-16 13:44:29 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-05-22 14:21:09 +0300 |
| commit | dd944afcd948a00f881554a41a93fa0242d8b370 (patch) | |
| tree | 95d3f1dcef955c73358ed65509fa13a42b4a987d | |
| parent | 380119d739002a7f9cdc7f730fcaa42f89f8e44b (diff) | |
fix: mci: Fine tune of MCI parameters
At AP and CP
//reg[15:8] – RX NQ threshold reduced to 0x7
//reg[23:16] – RX PQ threshold reduced to 0x7
//reg[31:24] – RX RQ threshold reduced to 0x7
//reg[7:4] – RX delta threshold reduced to 0x2
At AP:
//reg[4:0] – WR outstanding reduced to 0x6 (0x5 written to reg)
//reg[10:6] – RD outstanding reduced to 0x6 (0x5 written to reg)
At CP:
//reg[10:6] – RD outstanding reduced to d’14 (d’13 written to reg)
Change-Id: I00d1f22501d22171015873a1b12224e0c0443fbe
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39526
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
(cherry picked from commit cbcf48899360940826678e370d5c247bb782938d)
Reviewed-on: http://vgitil04.il.marvell.com:8080/39797
| -rw-r--r-- | drivers/marvell/mci.c | 11 | ||||
| -rw-r--r-- | include/drivers/marvell/mci.h | 14 |
2 files changed, 12 insertions, 13 deletions
diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c index 81d7d5ea..7bf36d4f 100644 --- a/drivers/marvell/mci.c +++ b/drivers/marvell/mci.c @@ -399,8 +399,8 @@ static int mci_axi_set_fifo_rx_tx_thresh_a1(int mci_index) /* AP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | - MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(7) | - MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(7)); + MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(5) | + MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(5)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | @@ -410,8 +410,8 @@ static int mci_axi_set_fifo_rx_tx_thresh_a1(int mci_index) /* CP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | - MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(15) | - MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(15)); + MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(13) | + MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(31)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | @@ -506,8 +506,7 @@ int mci_configure_a1(int mci_index) rval = mci_enable_simultaneous_transactions(mci_index); if (rval) ERROR("Failed to set MCI for simultaneous read/write transactions\n"); - } - else + } else VERBOSE("MCI is used for boot source: skipping MCI ID assignment\n"); /* enable PHY register mode read/write access */ diff --git a/include/drivers/marvell/mci.h b/include/drivers/marvell/mci.h index 3a46f1e4..1b6c3003 100644 --- a/include/drivers/marvell/mci.h +++ b/include/drivers/marvell/mci.h @@ -101,10 +101,10 @@ #define MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(val) (((val) & 0xF) << 4) #define MCI_CTRL_RX_TX_MEM_CFG_RTC(val) (((val) & 0x3) << 2) #define MCI_CTRL_RX_TX_MEM_CFG_WTC(val) (((val) & 0x3) << 0) -#define MCI_CTRL_RX_MEM_CFG_REG_DEF_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x8) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x8) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x8) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(3) | \ +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x7) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x7) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x7) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(2) | \ MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) @@ -186,15 +186,15 @@ /* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Window 0 Destination Register */ #define MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM 0x3 #define MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(val) (((val) & 0x1) << 16) -#define MCI_HB_CTRL_WIN0_DEST_ID(val) (((val) & 0xfF) << 0) +#define MCI_HB_CTRL_WIN0_DEST_ID(val) (((val) & 0xFF) << 0) /* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Tx Control Register */ #define MCI_HB_CTRL_TX_CTRL_REG_NUM 0xD #define MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET 24 #define MCI_HB_CTRL_TX_CTRL_PCIE_MODE (1 << MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET) #define MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(val) (((val) & 0xF) << 12) -#define MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(val) (((val) & 0xF) << 6) -#define MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(val) (((val) & 0xF) << 0) +#define MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(val) (((val) & 0x1F) << 6) +#define MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(val) (((val) & 0x1F) << 0) /* HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB PHY Idle Control Register */ #define MCI_PHY_P0_IDLE_CTRL_REG_NUM 0x6 |