diff options
| author | Marcin Wojtas <mw@semihalf.com> | 2017-10-04 16:13:27 +0200 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-11-23 11:42:59 +0200 |
| commit | 15015079206a0373ac81d09626d92618d5969724 (patch) | |
| tree | be5c2db8e2f19f6f547dc483693e6d3a02ed8673 | |
| parent | 903f24d78c1e2b6e20839f7c532b00befb1d08a4 (diff) | |
plat/marvell: a80x0_mcbin: configure Direct Mode window for SPI flash
In order to be able to support UEFI variables, direct mode access
to the SPI flash is required. The variables will be placed at
4MB - 256KB offset. For this purpose at offset 0xf9000000 configure
new window pointing to the CP1 SPI1 CS0 device. Because the platform
supports maximum amount of 6 IO windows, CP1 PCIE0 window had to be
be extended to cover the SPI area as well.
Change-Id: I125ebfb5259549e2ea0d0d2c76296e4167c6ca45
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/46711
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c index a1b7b863..b7448f99 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c @@ -76,7 +76,10 @@ int marvell_gpio_config(void) /******************************************************************************* * AMB Configuration ******************************************************************************/ -struct amb_win *amb_memory_map; +struct amb_win amb_memory_map[] = { + /* CP1 SPI1 CS0 Direct Mode access */ + {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, +}; uintptr_t marvell_get_amb_reg_offs(int cp_index) { @@ -101,8 +104,8 @@ int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size) struct io_win io_win_memory_map[] = { /* CP1 (MCI0) internal regs */ {0x0, 0xf4000000, 0x0, 0x2000000, MCI_0_TID}, - /* PCIe0 on CP1*/ - {0x0, 0xfa000000, 0x0, 0x1000000, MCI_0_TID}, + /* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/ + {0x0, 0xf9000000, 0x0, 0x2000000, MCI_0_TID}, /* PCIe1 on CP1*/ {0x0, 0xfb000000, 0x0, 0x1000000, MCI_0_TID}, /* PCIe2 on CP1*/ @@ -153,6 +156,8 @@ struct iob_win iob_memory_map_cp0[] = { struct iob_win iob_memory_map_cp1[] = { /* CP1 */ + /* SPI1_CS0 (RUNIT) window */ + {0x0, 0xf9000000, 0x0, 0x1000000, RUNIT_TID}, /* PEX1_X1 window */ {0x0, 0xfb000000, 0x0, 0x1000000, PEX1_TID}, /* PEX2_X1 window */ |