diff options
| author | Omri Itach <omrii@marvell.com> | 2017-06-28 14:54:32 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-08-31 18:00:27 +0300 |
| commit | 9fcfc8e53ed4d51a39dc72bd177f988c225be3d6 (patch) | |
| tree | 5ff45b28f64077df43c28f8acf1b4d1baef726cc | |
| parent | 72392ef6b448c80e68793586c9e7f1f46731c139 (diff) | |
fix: mci: adjust backoff thresholds and the outstanding transactions limits
update parameters for various backoff thresholds and the limits
of the outstanding transactions.
This is to prevent backoff at all the queues, except for the PQ of AP
(writes from CP to AP), which cannot be prevented.
Changes list:
1) Global RX backoff threshold changed from 0xB to 0x3f
(bits 22:16 of register 25 of IHB on both ends)
2) PQ backoff threshold at AP side changed from 0x7 to 0x6
(IHB register 0 of AP, bits 22:16)
3) RX Delta changed from 0x2 to 0xf (IHB register 0 on both sides, bits 7:4)
4) set AP read & write oustanding limits to 4.
5) set CP write oustanding limit to 18, and CP read oustanding to 12.
Change-Id: I31869f134a368f681ac769caae880d2e45e37c21
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/40930
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | drivers/marvell/mci.c | 12 | ||||
| -rw-r--r-- | include/drivers/marvell/mci.h | 17 |
2 files changed, 18 insertions, 11 deletions
diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c index 4918b9c1..22b31755 100644 --- a/drivers/marvell/mci.c +++ b/drivers/marvell/mci.c @@ -383,7 +383,7 @@ static int mci_axi_set_fifo_rx_tx_thresh_a1(int mci_index) /* AP RX thresholds and delta configurations (IHB_reg 0x0) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), - MCI_CTRL_RX_MEM_CFG_REG_DEF_VAL); + MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_RX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); @@ -391,7 +391,7 @@ static int mci_axi_set_fifo_rx_tx_thresh_a1(int mci_index) /* CP RX thresholds and delta configurations (IHB_reg 0x0) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), - MCI_CTRL_RX_MEM_CFG_REG_DEF_VAL); + MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_RX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); @@ -400,8 +400,8 @@ static int mci_axi_set_fifo_rx_tx_thresh_a1(int mci_index) /* AP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | - MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(5) | - MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(5)); + MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(3) | + MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(3)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | @@ -411,8 +411,8 @@ static int mci_axi_set_fifo_rx_tx_thresh_a1(int mci_index) /* CP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | - MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(13) | - MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(31)); + MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(0xB) | + MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(0x11)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | diff --git a/include/drivers/marvell/mci.h b/include/drivers/marvell/mci.h index 1b6c3003..63654638 100644 --- a/include/drivers/marvell/mci.h +++ b/include/drivers/marvell/mci.h @@ -101,10 +101,17 @@ #define MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(val) (((val) & 0xF) << 4) #define MCI_CTRL_RX_TX_MEM_CFG_RTC(val) (((val) & 0x3) << 2) #define MCI_CTRL_RX_TX_MEM_CFG_WTC(val) (((val) & 0x3) << 0) -#define MCI_CTRL_RX_MEM_CFG_REG_DEF_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x7) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x7) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x7) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(2) | \ +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x07) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) + +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x03) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) @@ -168,7 +175,7 @@ #define MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL_A1 (MCI_CTRL_IHB_MODE_HBCLK_DIV(6) | \ MCI_CTRL_IHB_MODE_FWD_MOD | \ MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(0xF) | \ - MCI_CTRL_IHB_MODE_RX_COMB_THRESH(0x0b) | \ + MCI_CTRL_IHB_MODE_RX_COMB_THRESH(0x3f) | \ MCI_CTRL_IHB_MODE_TX_COMB_THRESH(0x40)) /* AXI_HB registers */ #define MCI_AXI_ACCESS_DATA_REG_NUM 0x0 |