pcie: a8040_ocp: pcie stabilization configurations

This patch optimizes the pcie comphy receiver and transmitter configuration.
It includes the following optimizations:
RX - Force FFE constant values instead of trained values
TX - Increase the full swing value and update all presets
     (p0 - p10) accordingly

Change-Id: I6e48d543eb343b453ed804d9b48bcfec86c30225
Signed-off-by: Ofir Fedida <ofedida@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/43426
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

3 files changed, 256 insertions, 1 deletions

diff --git a/drivers/marvell/comphy.h b/drivers/marvell/comphy.h
index b58fc071..9b0f4e5b 100644
--- a/drivers/marvell/comphy.h
+++ b/drivers/marvell/comphy.h
@@ -329,6 +329,12 @@
 #define HPIPE_G2_DFE_RES_MASK			(0x3 << HPIPE_G2_DFE_RES_OFFSET)
 
 #define HPIPE_G3_SETTING_3_REG			0x450
+#define HPIPE_G3_FFE_CAP_SEL_OFFSET		0
+#define HPIPE_G3_FFE_CAP_SEL_MASK		(0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
+#define HPIPE_G3_FFE_RES_SEL_OFFSET		4
+#define HPIPE_G3_FFE_RES_SEL_MASK		(0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
+#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET	7
+#define HPIPE_G3_FFE_SETTING_FORCE_MASK		(0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET	12
 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK		(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET	14
@@ -379,6 +385,10 @@
 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK		(0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
 
 #define HPIPE_LANE_EQU_CONFIG_0_REG		0x69C
+#define HPIPE_CFG_EQ_FS_OFFSET			0
+#define HPIPE_CFG_EQ_FS_MASK			(0x3f << HPIPE_CFG_EQ_FS_OFFSET)
+#define HPIPE_CFG_EQ_LF_OFFSET			6
+#define HPIPE_CFG_EQ_LF_MASK			(0x3f << HPIPE_CFG_EQ_LF_OFFSET)
 #define HPIPE_CFG_PHY_RC_EP_OFFSET		12
 #define HPIPE_CFG_PHY_RC_EP_MASK		(0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
 
@@ -386,6 +396,114 @@
 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET	12
 #define HPIPE_CFG_UPDATE_POLARITY_MASK		(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
 
+#define HPIPE_LANE_PRESET_CFG0_REG		0x6a8
+#define HPIPE_CFG_CURSOR_PRESET0_OFFSET		0
+#define HPIPE_CFG_CURSOR_PRESET0_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET)
+#define HPIPE_CFG_CURSOR_PRESET1_OFFSET		6
+#define HPIPE_CFG_CURSOR_PRESET1_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG1_REG		0x6ac
+#define HPIPE_CFG_CURSOR_PRESET2_OFFSET		0
+#define HPIPE_CFG_CURSOR_PRESET2_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET)
+#define HPIPE_CFG_CURSOR_PRESET3_OFFSET		6
+#define HPIPE_CFG_CURSOR_PRESET3_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG2_REG		0x6b0
+#define HPIPE_CFG_CURSOR_PRESET4_OFFSET		0
+#define HPIPE_CFG_CURSOR_PRESET4_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET)
+#define HPIPE_CFG_CURSOR_PRESET5_OFFSET		6
+#define HPIPE_CFG_CURSOR_PRESET5_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG3_REG		0x6b4
+#define HPIPE_CFG_CURSOR_PRESET6_OFFSET		0
+#define HPIPE_CFG_CURSOR_PRESET6_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET)
+#define HPIPE_CFG_CURSOR_PRESET7_OFFSET		6
+#define HPIPE_CFG_CURSOR_PRESET7_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG4_REG		0x6b8
+#define HPIPE_CFG_CURSOR_PRESET8_OFFSET		0
+#define HPIPE_CFG_CURSOR_PRESET8_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET)
+#define HPIPE_CFG_CURSOR_PRESET9_OFFSET		6
+#define HPIPE_CFG_CURSOR_PRESET9_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG5_REG		0x6bc
+#define HPIPE_CFG_CURSOR_PRESET10_OFFSET	0
+#define HPIPE_CFG_CURSOR_PRESET10_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET)
+#define HPIPE_CFG_CURSOR_PRESET11_OFFSET	6
+#define HPIPE_CFG_CURSOR_PRESET11_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG6_REG		0x6c0
+#define HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET0_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG7_REG		0x6c4
+#define HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET1_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG8_REG		0x6c8
+#define HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET2_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG9_REG		0x6cc
+#define HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET3_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG10_REG		0x6d0
+#define HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET4_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG11_REG		0x6d4
+#define HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET5_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG12_REG		0x6d8
+#define HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET6_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG13_REG		0x6dc
+#define HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET7_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG14_REG		0x6e0
+#define HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET8_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG15_REG		0x6e4
+#define HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET9_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG16_REG		0x6e8
+#define HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET10_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET)
+
+#define HPIPE_LANE_PRESET_CFG17_REG		0x6ec
+#define HPIPE_CFG_PRE_CURSOR_PRESET11_OFFSET	0
+#define HPIPE_CFG_PRE_CURSOR_PRESET11_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET11_OFFSET)
+#define HPIPE_CFG_POST_CURSOR_PRESET11_OFFSET	6
+#define HPIPE_CFG_POST_CURSOR_PRESET11_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET11_OFFSET)
+
 #define HPIPE_LANE_EQ_REMOTE_SETTING_REG	0x6f8
 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET	0
 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK	(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
diff --git a/drivers/marvell/pcie-comphy-cp110.c b/drivers/marvell/pcie-comphy-cp110.c
index b1b06845..329f32f6 100644
--- a/drivers/marvell/pcie-comphy-cp110.c
+++ b/drivers/marvell/pcie-comphy-cp110.c
@@ -356,8 +356,137 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw)
 	data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
 	mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
 	data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
+
+#ifdef OCP_COMPHY_TUNE
+	/* FFE-res tuning and cap select  */
+	mask |= HPIPE_G3_FFE_CAP_SEL_MASK;
+	data |= 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
+	mask |= HPIPE_G3_FFE_CAP_SEL_MASK;
+	data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
+	mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
+	data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
+#endif
 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
 
+#ifdef OCP_COMPHY_TUNE
+	/* preset0,1 main cursor fine Tune*/
+	mask = HPIPE_CFG_CURSOR_PRESET0_MASK;
+	data = 0x23 << HPIPE_CFG_CURSOR_PRESET0_OFFSET;
+	mask |= HPIPE_CFG_CURSOR_PRESET1_MASK;
+	data |= 0x28 << HPIPE_CFG_CURSOR_PRESET1_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG0_REG, data, mask);
+
+	/* preset2,3 main cursor fine Tune*/
+	mask = HPIPE_CFG_CURSOR_PRESET2_MASK;
+	data = 0x26 << HPIPE_CFG_CURSOR_PRESET2_OFFSET;
+	mask |= HPIPE_CFG_CURSOR_PRESET3_MASK;
+	data |= 0x2a << HPIPE_CFG_CURSOR_PRESET3_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG1_REG, data, mask);
+
+	/* preset4,5 main cursor fine Tune*/
+	mask = HPIPE_CFG_CURSOR_PRESET4_MASK;
+	data = 0x30 << HPIPE_CFG_CURSOR_PRESET4_OFFSET;
+	mask |= HPIPE_CFG_CURSOR_PRESET5_MASK;
+	data |= 0x2c << HPIPE_CFG_CURSOR_PRESET5_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG2_REG, data, mask);
+
+	/* preset6,7 main cursor fine Tune*/
+	mask = HPIPE_CFG_CURSOR_PRESET6_MASK;
+	data = 0x2a << HPIPE_CFG_CURSOR_PRESET6_OFFSET;
+	mask |= HPIPE_CFG_CURSOR_PRESET7_MASK;
+	data |= 0x22 << HPIPE_CFG_CURSOR_PRESET7_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG3_REG, data, mask);
+
+	/* preset8,9 main cursor fine Tune*/
+	mask = HPIPE_CFG_CURSOR_PRESET8_MASK;
+	data = 0x24 << HPIPE_CFG_CURSOR_PRESET8_OFFSET;
+	mask |= HPIPE_CFG_CURSOR_PRESET9_MASK;
+	data |= 0x28 << HPIPE_CFG_CURSOR_PRESET9_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG4_REG, data, mask);
+
+	/* preset10,11 main cursor fine Tune*/
+	mask = HPIPE_CFG_CURSOR_PRESET10_MASK;
+	data = 0x21 << HPIPE_CFG_CURSOR_PRESET10_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG5_REG, data, mask);
+
+	/* preset0 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET0_MASK;
+	data = 0x0 << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET0_MASK;
+	data |= 0xd << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG6_REG, data, mask);
+
+	/* preset1 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET1_MASK;
+	data = 0x0 << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET1_MASK;
+	data |= 0x8 << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG7_REG, data, mask);
+
+	/* preset2 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET2_MASK;
+	data = 0x0 << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET2_MASK;
+	data |= 0xa << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG8_REG, data, mask);
+
+	/* preset3 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET3_MASK;
+	data = 0x0 << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET3_MASK;
+	data |= 0x6 << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG9_REG, data, mask);
+
+	/* preset4 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET4_MASK;
+	data = 0x0 << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET4_MASK;
+	data |= 0x0 << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG10_REG, data, mask);
+
+	/* preset5 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET5_MASK;
+	data = 0x4 << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET5_MASK;
+	data |= 0x0 << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG11_REG, data, mask);
+
+	/* preset6 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET6_MASK;
+	data = 0x6 << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET6_MASK;
+	data |= 0x0 << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG12_REG, data, mask);
+
+	/* preset7 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET7_MASK;
+	data = 0x4 << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET7_MASK;
+	data |= 0xa << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG13_REG, data, mask);
+
+	/* preset8 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET8_MASK;
+	data = 0x6 << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET8_MASK;
+	data |= 0x6 << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG14_REG, data, mask);
+
+	/* preset9 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET9_MASK;
+	data = 0x8 << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET9_MASK;
+	data |= 0x0 << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG15_REG, data, mask);
+
+	/* preset10 pre and post cursor fine Tune*/
+	mask = HPIPE_CFG_PRE_CURSOR_PRESET10_MASK;
+	data = 0x0 << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET;
+	mask |= HPIPE_CFG_POST_CURSOR_PRESET10_MASK;
+	data |= 0xf << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_PRESET_CFG16_REG, data, mask);
+#endif /* OCP_COMPHY_TUNE */
+
 	/* Pattern lock lost timeout disable */
 	mask = HPIPE_FRAME_DET_LOCK_LOST_TO_MASK;
 	data = 0x0 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET;
@@ -420,8 +549,15 @@ int comphy_pcie_power_up(uint32_t lane, struct pci_hw_cfg *hw)
 		reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
 	}
 
-	INFO("stage: Comphy power up\n");
+#ifdef OCP_COMPHY_TUNE
+	mask = HPIPE_CFG_EQ_FS_MASK;
+	data = 0x30 << HPIPE_CFG_EQ_FS_OFFSET;
+	mask |= HPIPE_CFG_EQ_LF_MASK;
+	data |= 0x10 << HPIPE_CFG_EQ_LF_OFFSET;
+	reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
+#endif /* OCP_COMPHY_TUNE */
 
+	INFO("stage: Comphy power up\n");
 	/* for PCIe by4 or by2 - release from reset only after finish to configure all lanes */
 	if ((hw->lane_width == 1) || (lane == (hw->lane_width - 1))) {
 		uint32_t i, start_lane, end_lane;
diff --git a/plat/marvell/a8k/a80x0_ocp/plat_def.h b/plat/marvell/a8k/a80x0_ocp/plat_def.h
index 132f507f..788eb4d6 100644
--- a/plat/marvell/a8k/a80x0_ocp/plat_def.h
+++ b/plat/marvell/a8k/a80x0_ocp/plat_def.h
@@ -38,6 +38,7 @@
 #include <a8k_plat_def.h>
 
 #define CP_COUNT		2	/* A80x0 has both CP0 & CP1 */
+#define OCP_COMPHY_TUNE
 
 /* Force disable of LLC, regardless of LLC_DISABLE compilation flag
  * this is due to an issue observed while running iperf with