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authorHanna Hawa <hannah@marvell.com>2018-05-08 16:12:20 +0300
committerKostya Porotchkin <kostap@marvell.com>2018-05-10 12:02:12 +0300
commit25eabfd25d2d81cfaa03d67874545684bfb79ade (patch)
tree070bd053a387b08964d43b87fa401be320500a2d
parente8a02a755056290b95176d84979ea37c158de61a (diff)
fix: ap810: update Aurora2 configuration and set all reads to be unique
Change-Id: I1c74c240e384fd3743c5f30531c73f2472f60a26 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54740 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54842
-rw-r--r--plat/marvell/a8k-p/common/plat_bl31_setup.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/plat/marvell/a8k-p/common/plat_bl31_setup.c b/plat/marvell/a8k-p/common/plat_bl31_setup.c
index 8d541867..2b2c6c77 100644
--- a/plat/marvell/a8k-p/common/plat_bl31_setup.c
+++ b/plat/marvell/a8k-p/common/plat_bl31_setup.c
@@ -25,7 +25,9 @@
#define GSPMU_CPU_CONTROL (0x1 << 0)
#define CCU_HTC_CR(ap) (MVEBU_CCU_BASE(ap) + 0x200)
+#define CCU_READ_UNIQ_ENABLE 19
#define CCU_SET_POC_OFFSET 5
+#define CCU_PASS_DIRTY_ENABLE 1
#define GEVENT_CR_PORTx_EVENT_MASK(ap, port) (MVEBU_AR_RFU_BASE(ap) + 0x500 + port * 0x4)
@@ -222,10 +224,19 @@ static void ap810_init_aurora2(int ap_id)
llc_enable(ap_id, 1);
#endif /* !LLC_DISABLE */
+ reg = mmio_read_32(CCU_HTC_CR(ap_id));
+ /* Configure all reads snoop to be read unique
+ ** relevant for A0 revision & single AP only
+ ** */
+ if ((ap810_rev_id_get(ap_id) == MVEBU_AP810_REV_ID_A0) &&
+ (ap810_get_ap_count() == 1)) {
+ reg &= ~(0x1 << CCU_READ_UNIQ_ENABLE | 0x1 << CCU_PASS_DIRTY_ENABLE);
+ reg |= (0x1 << CCU_READ_UNIQ_ENABLE);
+ }
+
/* Set point of coherency to DDR. This is
* required by units which have SW cache coherency
*/
- reg = mmio_read_32(CCU_HTC_CR(ap_id));
reg |= (0x1 << CCU_SET_POC_OFFSET);
mmio_write_32(CCU_HTC_CR(ap_id), reg);