summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorOfir Fedida <ofedida@marvell.com>2018-04-11 10:27:41 +0300
committerKostya Porotchkin <kostap@marvell.com>2018-04-22 11:54:20 +0300
commit767607ceffe974385e6d2e77ebdbdb96f2e5db9b (patch)
tree2fcf6f5dc280486415efa4b8faee8e90de70f443
parent6d0f4afa1eb114609af673db7394acf299625c88 (diff)
ble: ap810: remove unused functions
Remove functions: - plat_dram_addr_decode_insert - plat_dram_addr_decode_remove These functions sets (and clear) the address decoding in order to execute DRAM scrubbing by ble DRAMS scrubbing will be executed by DRAM driver and ble will set (and clear) the address decooding when executing DRAM training. Also sets the address decoding DRAM window to the default window opneed by BootROM Change-Id: Id17327e1d52796cc754a1c754488763d356b2026 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53094 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
-rw-r--r--plat/marvell/a8k-p/common/plat_dram.c59
1 files changed, 8 insertions, 51 deletions
diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c
index 666853e6..7f376f9a 100644
--- a/plat/marvell/a8k-p/common/plat_dram.c
+++ b/plat/marvell/a8k-p/common/plat_dram.c
@@ -336,36 +336,6 @@ static void plat_dram_interfaces_update(void)
}
}
-static void plat_dram_addr_decode_insert(uint32_t ap_id, uint32_t dram_tgt,
- struct addr_map_win *gwin_temp_win,
- struct addr_map_win *ccu_dram_win)
-{
- const uint32_t ap_cnt = ap810_get_ap_count();
-
- /* Add a single GWIN entry to AP0 for enabling remote APs access
- * There is no need to open GWIN on other APs, since only AP0
- * is involved at this stage.
- */
- if (ap_id != 0) {
- gwin_temp_win->base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt);
- gwin_temp_win->win_size = AP_DRAM_SIZE(ap_cnt);
- gwin_temp_win->target_id = ap_id;
- gwin_temp_win_insert(0, gwin_temp_win, 1);
- }
- /* Add CCU window for DRAM access:
- * Single DIMM on this AP, CCU target = DRAM 0/1
- * Multiple DIMMs on this AP, CCU target = RAR
- * The RAR target allows access to both DRAM interfaces
- * in parallel, increasing the total memory bandwidth.
- */
- ccu_dram_win->base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt);
- ccu_dram_win->win_size = AP_DRAM_SIZE(ap_cnt);
- ccu_dram_win->target_id = dram_tgt;
-
- /* Create a memory window with the approriate target in CCU */
- ccu_dram_win_config(ap_id, ccu_dram_win);
-}
-
static void plat_dram_temp_addr_decode_cfg(uint32_t ap_id, struct mv_ddr_iface *iface)
{
struct addr_map_win ccu_dram_win;
@@ -393,19 +363,6 @@ static void plat_dram_temp_addr_decode_cfg(uint32_t ap_id, struct mv_ddr_iface *
plat_dram_mca_remap(0, ccu_dram_win.target_id, iface->iface_byte_size, 3 * _1GB_, _1GB_);
}
-static void plat_dram_addr_decode_remove(uint32_t ap_id,
- struct addr_map_win *gwin_temp_win,
- struct addr_map_win *ccu_dram_win)
-{
- if (ap_id == 0) {
- ccu_dram_win->win_size = AP0_BOOTROM_DRAM_SIZE;
- ccu_dram_win_config(0, ccu_dram_win);
- } else {
- /* Remove the earlier configured GWIN entry from AP0 */
- gwin_temp_win_remove(0, gwin_temp_win, 1);
- }
-}
-
int plat_dram_init(void)
{
struct mv_ddr_iface *iface = NULL;
@@ -419,7 +376,7 @@ int plat_dram_init(void)
/* Go over DRAM interfaces, run remapping and scrubbing */
for (ap_id = 0; ap_id < ap_cnt; ap_id++) {
- struct addr_map_win gwin_temp_win, ccu_dram_win;
+ struct addr_map_win ccu_dram_win;
iface_cnt = 0;
ap_dram_size = 0;
ap_dram_tgt = DRAM_0_TID;
@@ -496,15 +453,15 @@ int plat_dram_init(void)
if (ap_dram_tgt == RAR_TID)
plat_dram_rar_mode_set(ap_id);
- /* Open access to AP DRAM and run scrubbing */
- plat_dram_addr_decode_insert(ap_id, ap_dram_tgt,
- &gwin_temp_win, &ccu_dram_win);
-
- /* Restore the original DRAM size on AP0 before returning to the BootROM.
- * Access to entire DRAM is required only during DDR initialization and scrubbing.
+ /* Restore the original DRAM size before returning to the BootROM.
* The correct DRAM size will be set back by init_ccu() at later stage.
*/
- plat_dram_addr_decode_remove(ap_id, &gwin_temp_win, &ccu_dram_win);
+ ccu_dram_win.base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt);
+ ccu_dram_win.win_size = AP0_BOOTROM_DRAM_SIZE;
+ ccu_dram_win.target_id = ap_dram_tgt;
+
+ /* Create a memory window with the appropriate target in CCU */
+ ccu_dram_win_config(ap_id, &ccu_dram_win);
}
debug_exit();