summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorOfir Fedida <ofedida@marvell.com>2018-04-10 17:53:51 +0300
committerKostya Porotchkin <kostap@marvell.com>2018-04-15 16:43:22 +0300
commit7c3a542da2128e4c2d09c191b00b6e00c3c4fc50 (patch)
tree672e31ee5c52bd32380fc82c9bc238566ada56ce
parente10d5a63973639a5f78fa6b4f3bac4e5bdcddba5 (diff)
fix: ble: ap810: change flow and fix dram target id
in case of not using RAR the dram target id is set for the second interface instead of the first also fixed the flow to be more readable Change-Id: I27d149ee0db27339e7e661d362a0a3af739cd082 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53079 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
-rw-r--r--plat/marvell/a8k-p/common/plat_dram.c28
1 files changed, 13 insertions, 15 deletions
diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c
index ea72f692..666853e6 100644
--- a/plat/marvell/a8k-p/common/plat_dram.c
+++ b/plat/marvell/a8k-p/common/plat_dram.c
@@ -456,20 +456,13 @@ int plat_dram_init(void)
ap_dram_size += iface->iface_byte_size;
}
- if (iface_cnt == DDR_MAX_UNIT_PER_AP) {
- ap_dram_tgt = RAR_TID;
- } else {
- if (iface->id == 1)
- ap_dram_tgt = DRAM_1_TID;
- else
- ap_dram_tgt = DRAM_0_TID;
- }
-
- if (ap_dram_tgt == RAR_TID) {
- plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size);
- for (i = 0; i < ifaces_size; i++, iface++) {
- plat_dram_iface_set(iface);
+ plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size);
+ for (i = 0; i < iface_cnt; i++, iface++) {
+ plat_dram_iface_set(iface);
+ /* If the number of interfaces equal to MAX (enable RAR) */
+ if (iface_cnt == DDR_MAX_UNIT_PER_AP) {
VERBOSE("AP-%d set DRAM%d into RAR mode\n", ap_id, i);
+ ap_dram_tgt = RAR_TID;
/* If the base address not 0x0, need to divide
** the base address, the dram region will be
** splited into dual DRAMs
@@ -478,9 +471,14 @@ int plat_dram_init(void)
/* TODO: add EERATA */
if (iface->id == 1)
iface->iface_base_addr |= 1UL << 43;
- /* Update dram memory mapping */
- dram_mmap_config();
+ } else {
+ if (iface->id == 1)
+ ap_dram_tgt = DRAM_1_TID;
+ else
+ ap_dram_tgt = DRAM_0_TID;
}
+ /* Update dram memory mapping */
+ dram_mmap_config();
}
INFO("AP-%d DRAM size is 0x%lx (%lldGB)\n",