mss: add support for firmware load to CP2 and CP3

Currently, firmware load is supported only for APx and CP0/1.
In Armada8084 there are 4 CPs so we need support for firmware load
for CP2/3 too.

Changes in this patch:
- Add new firmware types to cm3_t (MSS_CP2 and MSS_CP3).
- Updates load_img_to_cm3() to support 4 images and reduce code
  duplication.
- Configure MSS_AIBR for each CP
	CP0 MSS_AIBR = 810
	CP1 MSS_AIBR = 880
	CP2 MSS_AIBR = 8f0
	CP3 MSS_AIBR = 960

Change-Id: Id8ad90a0b7ff38fe8da30a49f293cd8acd2b49e8
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/51566
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

3 files changed, 44 insertions, 16 deletions

diff --git a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
index bacb1a24..59d5aad7 100644
--- a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
@@ -146,7 +146,31 @@ uint32_t bl2_plat_get_ap_count(void)
 
 void bl2_plat_configure_mss_windows(uintptr_t mss_regs)
 {
-	/* Configure the AEBR to enable access 256MB for AP config space */
+	/* CP address are bigger than 32 bits:
+	 * CPx on AP0 0x8100000000 + 0x700000000 * x
+	 * CPx on AP1 0x9e00000000 + 0x700000000 * x
+	 *
+	 * AP address is 32 bit.
+	 *
+	 * Shifting mss_regs >> 32 tells us if it's CP or AP.
+	 */
+	if (mss_regs >> 32) {
+		/* Configure AIBR (AXI Internal Address Bus extension) to map
+		 * CP base address. This allows each CP to access it's
+		 * own memory space.
+		 */
+		mmio_write_32(MSS_AIBR(mss_regs), mss_regs >> 28);
+	} else {
+		/* Configure AIBR (AXI Internal Address Bus extension) to allow AP
+		 * to access it's own memory space
+		 */
+		mmio_write_32(MSS_AIBR(mss_regs),
+			      ((0xf0000000 >> MSS_INTERNAL_ACCESS_BIT) & MSS_AIBR_MASK));
+	}
+
+	/* Configure AEBR (AXI Internal Address Bus extension) to map access:
+	 * CP: Access from CP to AP
+	 * AP: Access from AP to DRAM
+	 */
 	mmio_write_32(MSS_AEBR(mss_regs), ((0xe0000000 >> MSS_EXTERNAL_ACCESS_BIT) & MSS_AEBR_MASK));
-	mmio_write_32(MSS_AIBR(mss_regs), ((0xf0000000 >> MSS_INTERNAL_ACCESS_BIT) & MSS_AIBR_MASK));
 }
diff --git a/plat/marvell/common/mss/mss_scp_bl2_format.h b/plat/marvell/common/mss/mss_scp_bl2_format.h
index cda22909..4db3a336 100644
--- a/plat/marvell/common/mss/mss_scp_bl2_format.h
+++ b/plat/marvell/common/mss/mss_scp_bl2_format.h
@@ -53,6 +53,8 @@ enum cm3_t {
 	MSS_AP,
 	MSS_CP0,
 	MSS_CP1,
+	MSS_CP2,
+	MSS_CP3,
 	MG_CP0,
 	MG_CP1,
 };
diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c
index d7d053d0..006d688d 100644
--- a/plat/marvell/common/mss/mss_scp_bootloader.c
+++ b/plat/marvell/common/mss/mss_scp_bootloader.c
@@ -205,7 +205,7 @@ static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t
 /* Load CM3 image (single_img) to CM3 pointed by cm3_type */
 static int load_img_to_cm3(enum cm3_t cm3_type, uintptr_t single_img, uint32_t image_size)
 {
-	int ret, ap_idx;
+	int ret, ap_idx, cp_index;
 	uint32_t ap_count = bl2_plat_get_ap_count();
 
 	switch (cm3_type) {
@@ -218,24 +218,26 @@ static int load_img_to_cm3(enum cm3_t cm3_type, uintptr_t single_img, uint32_t i
 		}
 		break;
 	case MSS_CP0:
-		for (ap_idx = 0; ap_idx  < ap_count; ap_idx++) {
-			NOTICE("Load image to CP0 MSS AP%d\n", ap_idx);
-			ret = mss_image_load(single_img, image_size, bl2_plat_get_cp_mss_regs(ap_idx, 0));
-			if (ret != 0) {
-				ERROR("SCP Image load failed\n");
-				return -1;
-			}
-		}
-		break;
 	case MSS_CP1:
+	case MSS_CP2:
+	case MSS_CP3:
+		/* MSS_AP = 0
+		 * MSS_CP1 = 1
+		 * .
+		 * .
+		 * MSS_CP3 = 4
+		 * Actual CP index is MSS_CPX - 1
+		 */
+		cp_index = cm3_type - 1;
 		for (ap_idx = 0; ap_idx < ap_count; ap_idx++) {
-			if (bl2_plat_get_cp_count(ap_idx) == 1) {
-				NOTICE("Skipping MSS CP1 related image\n");
+			/* Check if we should load this image according to number of CPs */
+			if (bl2_plat_get_cp_count(ap_idx) <= cp_index) {
+				NOTICE("Skipping MSS CP%d related image\n", cp_index);
 				break;
 			}
 
-			NOTICE("Load image to CP1 MSS AP%d\n", ap_idx);
-			ret = mss_image_load(single_img, image_size, bl2_plat_get_cp_mss_regs(ap_idx, 1));
+			NOTICE("Load image to CP%d MSS AP%d\n", cp_index, ap_idx);
+			ret = mss_image_load(single_img, image_size, bl2_plat_get_cp_mss_regs(ap_idx, cp_index));
 			if (ret != 0) {
 				ERROR("SCP Image load failed\n");
 				return -1;