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authorHanna Hawa <hannah@marvell.com>2018-03-06 14:36:15 +0200
committerKostya Porotchkin <kostap@marvell.com>2018-03-06 15:01:08 +0200
commitae498814cbd58750fcc11cd4322772a9e633b503 (patch)
tree6ec48c5f08bea17b88706ed5ae50413e48426a4c
parent54a2af321fa36fb88c4eccd51dc5677e3f7358d5 (diff)
fix: ap810: plat_dram: re-init dram target window in for loop
Issue found when no DDR DIMM found on AP1, the ap_dram_tgt configured with old value from AP0. Change-Id: Ifd52a8dd7dfd8c899601d5d0f261ec249dcd5e52 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/51385 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
-rw-r--r--plat/marvell/a8k-p/common/plat_dram.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c
index 0ccb05ae..d9985f41 100644
--- a/plat/marvell/a8k-p/common/plat_dram.c
+++ b/plat/marvell/a8k-p/common/plat_dram.c
@@ -399,7 +399,7 @@ int plat_dram_init(void)
uint32_t ifaces_size, i, ap_id, ret;
const uint32_t ap_cnt = ap810_get_ap_count();
uint64_t ap_dram_size;
- uint32_t ap_dram_tgt = DRAM_0_TID;
+ uint32_t ap_dram_tgt;
/* Update DRAM topology for all interfaces */
plat_dram_interfaces_update();
@@ -409,6 +409,7 @@ int plat_dram_init(void)
struct addr_map_win gwin_temp_win, ccu_dram_win;
ap_dram_size = 0;
+ ap_dram_tgt = DRAM_0_TID;
/* Get interfaces of AP-ID */
plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size);
/* Go over the interfaces of AP and initialize them */