a3900: pm: poweroff unused CPUs at early boot stage

- bootloader flow uses only CPU0 and CPU1-3 remain
  in reset (not powered off) which leads to more unnecessary
  power consuming and in some cases might increase SoC
  temperature.

- this patch powers off CPU1-3 in early BLE stage,
  and powered back on during Linux PSCI calls to
  a8k_pwr_domain_on.

- since the offsets in power register differs in ap806
  and ap807, the offsets are defined per platform
  and not the common driver.

Change-Id: Iae72577fc532be0bdb7f0899eb77b7ea1bb078ba
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53007
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

2 files changed, 24 insertions, 21 deletions

diff --git a/plat/marvell/a8k/a3900_z2/plat_def.h b/plat/marvell/a8k/a3900_z2/plat_def.h
index d7d62410..075ea9da 100644
--- a/plat/marvell/a8k/a3900_z2/plat_def.h
+++ b/plat/marvell/a8k/a3900_z2/plat_def.h
@@ -12,5 +12,6 @@
 
 /* A3900 has single CP0 */
 #define CP_COUNT		1
+#define MVEBU_SOC_AP807		1
 
 #endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
index 2e4eab7e..60c9486d 100644
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -102,12 +102,18 @@ enum CPU_ID {
 #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET	4
 #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK		(0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET)
 
+#ifdef MVEBU_SOC_AP807
+	#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET		1
+	#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET	0
+#else
+	#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET		0
+	#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET	31
+#endif
+
 #define PWRC_CPUN_CR_REG(cpu_id)		(MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10))
-#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET		0
 #define PWRC_CPUN_CR_PWR_DN_RQ_MASK		(0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET)
 #define PWRC_CPUN_CR_ISO_ENABLE_OFFSET		16
 #define PWRC_CPUN_CR_ISO_ENABLE_MASK		(0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)
-#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET	31
 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK	(0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
 
 #define CCU_B_PRCRN_REG(cpu_id)			(MVEBU_REGS_BASE + 0x1A50 + \
@@ -115,6 +121,12 @@ enum CPU_ID {
 #define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET	0
 #define CCU_B_PRCRN_CPUPORESET_STATIC_MASK	(0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET)
 
+/* power switch fingers */
+#define AP807_PWRC_LDO_CR0_REG			(MVEBU_REGS_BASE + 0x680000 + 0x100)
+#define AP807_PWRC_LDO_CR0_OFFSET		16
+#define AP807_PWRC_LDO_CR0_MASK			(0xff << AP807_PWRC_LDO_CR0_OFFSET)
+#define AP807_PWRC_LDO_CR0_VAL			0xfd
+
 /*
  * Power down CPU:
  * Used to reduce power consumption, and avoid SoC unnecessary temperature rise.
@@ -123,14 +135,6 @@ static int plat_marvell_cpu_powerdown(int cpu_id)
 {
 	uint32_t	reg_val;
 	int		exit_loop = REG_WR_VALIDATE_TIMEOUT;
-	unsigned int chip_rev_id;
-
-	chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG);
-	chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET);
-
-	/* TODO: support for ap807 needs to be added */
-	if (chip_rev_id == CHIP_ID_AP807)
-		return 0;
 
 	INFO("Powering down CPU%d\n", cpu_id);
 
@@ -234,23 +238,21 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr)
 	uint32_t	reg_val;
 	int	cpu_id = MPIDR_CPU_GET(mpidr), cluster = MPIDR_CLUSTER_GET(mpidr);
 	int	exit_loop = REG_WR_VALIDATE_TIMEOUT;
-	unsigned int chip_rev_id;
-
-	/* TODO: support for ap807 needs to be added */
-	chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG);
-	chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET);
-
-	/* Power up CPU (CPUs 1-3 are powered off at start of BLE) for AP806
-	 * only.
-	 */
-	if (chip_rev_id == CHIP_ID_AP807)
-		return 0;
 
 	/* calculate absolute CPU ID */
 	cpu_id = cluster * PLAT_MARVELL_CLUSTER_CORE_COUNT + cpu_id;
 
 	INFO("Powering on CPU%d\n", cpu_id);
 
+#ifdef MVEBU_SOC_AP807
+	/* Activate 2 power switch fingers */
+	reg_val = mmio_read_32(AP807_PWRC_LDO_CR0_REG);
+	reg_val &= ~(AP807_PWRC_LDO_CR0_MASK);
+	reg_val |= (AP807_PWRC_LDO_CR0_VAL << AP807_PWRC_LDO_CR0_OFFSET);
+	mmio_write_32(AP807_PWRC_LDO_CR0_REG, reg_val);
+	udelay(100);
+#endif
+
 	/* 1. Switch CPU power ON */
 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
 	reg_val |= 0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET;