diff options
| author | Christine Gharzuzi <chrisg@marvell.com> | 2018-03-26 20:15:04 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2018-03-28 10:03:28 +0300 |
| commit | d173258d9d8cfe2ff689f3d6cb27c62d4c9890c7 (patch) | |
| tree | 5303648d7ae8864225f02a71a003ae55e2ad5c85 | |
| parent | e887e8f1cdcb6440f455c256e26d99a1e9c6449a (diff) | |
plat_pm: ap807: disable PM options for Armada-AP-807
Disabled CPUs early powerdown and powerup in Linux boot, for AP807
Change-Id: I69f935719772e0ba1619931557b94b63cea5fe58
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/52588
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
| -rw-r--r-- | plat/marvell/a8k/common/include/a8k_plat_def.h | 5 | ||||
| -rw-r--r-- | plat/marvell/a8k/common/plat_pm.c | 19 |
2 files changed, 24 insertions, 0 deletions
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h index 34a1acd4..ce95d6c6 100644 --- a/plat/marvell/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/a8k/common/include/a8k_plat_def.h @@ -44,6 +44,11 @@ #define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC) #define GWD_IIDR2_REV_ID_OFFSET 12 #define GWD_IIDR2_REV_ID_MASK 0xF +#define GWD_IIDR2_CHIP_ID_OFFSET 20 +#define GWD_IIDR2_CHIP_ID_MASK (0xFFF << GWD_IIDR2_CHIP_ID_OFFSET) + +#define CHIP_ID_AP806 0x806 +#define CHIP_ID_AP807 0x807 #if PALLADIUM #define COUNTER_FREQUENCY 7000 diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index 2b982334..2e4eab7e 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -123,6 +123,14 @@ static int plat_marvell_cpu_powerdown(int cpu_id) { uint32_t reg_val; int exit_loop = REG_WR_VALIDATE_TIMEOUT; + unsigned int chip_rev_id; + + chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); + chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); + + /* TODO: support for ap807 needs to be added */ + if (chip_rev_id == CHIP_ID_AP807) + return 0; INFO("Powering down CPU%d\n", cpu_id); @@ -226,6 +234,17 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr) uint32_t reg_val; int cpu_id = MPIDR_CPU_GET(mpidr), cluster = MPIDR_CLUSTER_GET(mpidr); int exit_loop = REG_WR_VALIDATE_TIMEOUT; + unsigned int chip_rev_id; + + /* TODO: support for ap807 needs to be added */ + chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); + chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); + + /* Power up CPU (CPUs 1-3 are powered off at start of BLE) for AP806 + * only. + */ + if (chip_rev_id == CHIP_ID_AP807) + return 0; /* calculate absolute CPU ID */ cpu_id = cluster * PLAT_MARVELL_CLUSTER_CORE_COUNT + cpu_id; |