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authorGrzegorz Jaszczyk <jaz@semihalf.com>2018-04-04 14:21:41 +0200
committerKostya Porotchkin <kostap@marvell.com>2018-04-08 15:24:55 +0300
commitdf407f59f30fb11f849db82cd03e756bd5588f5b (patch)
treee2c6b5d7f84f7e6be28aebe3ab437c9a3495d580
parent59630545ceeb9473611b8e03fddeb65de99c19d5 (diff)
mvebu: cp110: add support for AP comphy configuration
Change-Id: I906e6cc740ba0cde3bced07b117da7dd3aad767e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52903 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
-rw-r--r--drivers/marvell/comphy/phy-comphy-cp110.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 1dfc165c..8b446183 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -2058,6 +2058,34 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
return ret;
}
+/* During AP the proper mode is auto-negotiated and the mac, pcs and serdes
+ * configuration are done by the firmware loaded to the MG's CM3 for appropriate
+ * negotiated mode. Therefore there is no need to configure the mac, pcs and
+ * serdes from u-boot. The only thing that need to be setup is powering up
+ * the comphy, which is done through Common PHY<n> Configuration 1 Register
+ * (CP0: 0xF2441000, CP1: 0xF4441000). This step can't be done by MG's CM3,
+ * since it doesn't have an access to this register-set (but it has access to
+ * the network registers like: MG, AP, MAC, PCS, Serdes etc.)
+ */
+static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base,
+ uint8_t comphy_index)
+{
+ uint32_t mask, data;
+ uintptr_t comphy_addr = comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
+
+ debug_enter();
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+ debug_exit();
+
+ return 0;
+}
+
int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index, uint64_t comphy_mode)
{
int mode = COMPHY_GET_MODE(comphy_mode);
@@ -2087,6 +2115,9 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index, uin
case (COMPHY_USB3D_MODE):
err = mvebu_cp110_comphy_usb3_power_on(comphy_base, comphy_index, comphy_mode);
break;
+ case (COMPHY_AP_MODE):
+ err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index);
+ break;
default:
ERROR("comphy%ld: unsupported comphy mode\n", comphy_index);
err = -EINVAL;