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authorKen Ma <make@marvell.com>2018-04-26 12:16:52 +0800
committerKostya Porotchkin <kostap@marvell.com>2018-05-10 10:15:03 +0300
commite8a02a755056290b95176d84979ea37c158de61a (patch)
tree081164c09cba88954f607d0088dbbbe1756d020f
parentb0ffaaf9399a71dc7f1df5f4447ff8348c3ddd5e (diff)
fix: a3700: correct the offset between eip continuous decode windows
The offset between eip continuous decode windows is 8 bytes but not 16(0x10) bytes, this patch fixes it. Change-Id: I1e42c80bcdb621c5701ac72191c112bef106db8e Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53849 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54839
-rw-r--r--plat/marvell/a3700/common/marvell_plat_config.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/a3700/common/marvell_plat_config.c
index 3f6055be..9cf1c0dd 100644
--- a/plat/marvell/a3700/common/marvell_plat_config.c
+++ b/plat/marvell/a3700/common/marvell_plat_config.c
@@ -46,7 +46,7 @@ struct dec_win_config io_dec_win_conf[] = {
{0xc800, 0x3d, 3, 0, 0x10}, /* SATA */
{0xca00, 0x3d, 3, 0, 0x08}, /* SD */
{0xcb00, 0x3d, 3, 0, 0x10}, /* eMMC */
- {0xce00, 0x3d, 2, 0, 0x10}, /* EIP97 */
+ {0xce00, 0x3d, 2, 0, 0x08}, /* EIP97 */
};
int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size)