diff options
| author | Igal Liberman <igall@marvell.com> | 2018-03-27 18:19:28 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2018-04-25 10:14:50 +0300 |
| commit | ef28246fed76de7556fa500248b699a4124bc64a (patch) | |
| tree | 7b9f70d1f2068256bebf669f683dbc32f1420c05 | |
| parent | a2e7e99145b7f820d763694fa6d00f494af23fa6 (diff) | |
marvell: psci: disable cache in el3
Currently, there's an open issue is some setups when
cpuidle is enabled - after sometime, one of the cores
might fail to come up after suspend.
This issue is under debug but generally it caused by
cache operations performed on the el3 stack.
For now, as a workaround, disable el3 cache,
in order to enable cpuidle feature.
Change-Id: Icf7dafeab701b34b23b6bcde78f0b8dc8d727e28
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/52671
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | lib/psci/aarch64/psci_helpers.S | 2 | ||||
| -rw-r--r-- | plat/marvell/common/marvell_bl31_setup.c | 6 |
3 files changed, 16 insertions, 0 deletions
@@ -64,6 +64,13 @@ CP_NUM := 2 endif endif +# Disable BL31 cache for Power-Managment +ifeq ($(PLAT),$(filter $(PLAT),a70x0)) +BL31_CACHE_DISABLE := 1 +else +BL31_CACHE_DISABLE := 0 +endif + # Marvell images BOOT_IMAGE := boot-image.bin BOOT_ENC_IMAGE := boot-image-enc.bin @@ -647,6 +654,7 @@ $(eval $(call add_define,ARO_ENABLE)) $(eval $(call add_define,LLC_DISABLE)) $(eval $(call add_define,PCI_EP_SUPPORT)) $(eval $(call add_define,CP_NUM)) +$(eval $(call add_define,BL31_CACHE_DISABLE)) ################################################################################ # Include BL specific makefiles diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S index afe21ebe..713cac8b 100644 --- a/lib/psci/aarch64/psci_helpers.S +++ b/lib/psci/aarch64/psci_helpers.S @@ -106,6 +106,7 @@ func psci_do_pwrup_cache_maintenance mov x0, sp bl inv_dcache_range +#if !BL31_CACHE_DISABLE /* --------------------------------------------- * Enable the data cache. * --------------------------------------------- @@ -114,6 +115,7 @@ func psci_do_pwrup_cache_maintenance orr x0, x0, #SCTLR_C_BIT msr sctlr_el3, x0 isb +#endif ldp x29, x30, [sp], #16 ret diff --git a/plat/marvell/common/marvell_bl31_setup.c b/plat/marvell/common/marvell_bl31_setup.c index 9008ca64..e1b8b99f 100644 --- a/plat/marvell/common/marvell_bl31_setup.c +++ b/plat/marvell/common/marvell_bl31_setup.c @@ -264,7 +264,13 @@ void marvell_bl31_plat_arch_setup(void) BL_COHERENT_RAM_END #endif ); + +#if BL31_CACHE_DISABLE + enable_mmu_el3(DISABLE_DCACHE); + INFO("Cache is disabled in BL3\n"); +#else enable_mmu_el3(0); +#endif } void bl31_plat_arch_setup(void) |