clocks: a8k-p: add PLL registers and values for clocks configurations

- preparations to switch default mode to PLL mode

- adding PLL registers and PLL values to clock driver

Change-Id: I3c06e10f9f24e43c4ba516cf17432d9c01a6c6af
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/52646
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>

1 files changed, 33 insertions, 19 deletions

diff --git a/plat/marvell/a8k-p/common/ap810_init_clocks.c b/plat/marvell/a8k-p/common/ap810_init_clocks.c
index 2207ab95..04150545 100644
--- a/plat/marvell/a8k-p/common/ap810_init_clocks.c
+++ b/plat/marvell/a8k-p/common/ap810_init_clocks.c
@@ -16,6 +16,8 @@
 #include <stdio.h>
 
 /* PLL's registers with local base address since each AP has its own EAWG*/
+#define PLL_CLUSTER_1_0_ADDRES	(MVEBU_DFX_SAR_LOCAL_AP + 0x2E0)
+#define PLL_CLUSTER_2_3_ADDRES	(MVEBU_DFX_SAR_LOCAL_AP + 0x2E8)
 #define PLL_RING_ADDRESS	(MVEBU_DFX_SAR_LOCAL_AP + 0x2F0)
 #define PLL_IO_ADDRESS		(MVEBU_DFX_SAR_LOCAL_AP + 0x2F8)
 #define PLL_PIDI_ADDRESS	(MVEBU_DFX_SAR_LOCAL_AP + 0x310)
@@ -24,7 +26,9 @@
 /* frequencies values */
 #define PLL_FREQ_3000		0x2D477001 /* 3000 */
 #define PLL_FREQ_2700		0x2B06B001 /* 2700 */
+#define PLL_FREQ_2500		0x2B063001 /* 2500 */
 #define PLL_FREQ_2400		0x2AE5F001 /* 2400 */
+#define PLL_FREQ_2200		0x2AC57001 /* 2200 */
 #define PLL_FREQ_2000		0x2FC9F002 /* 2000 */
 #define PLL_FREQ_1800		0x2D88F002 /* 1800 */
 #define PLL_FREQ_1600		0x2D47F002 /* 1600 */
@@ -38,6 +42,12 @@
 #define PLL_FREQ_1000		0x2AC4F002 /* 1000 */
 #define PLL_FREQ_800		0x2883F002 /* 800 */
 
+/* PLL device control registers */
+#define PLL_CONTROL_0_REG	0xEC6F8D34
+#define PLL_CONTROL_1_REG	0xEC6F8D40
+#define PLL_CONTROL_2_REG	0xEC6F8D3C
+#define PLL_CONTROL_3_REG	0xEC6F8D44
+
 /* EAWG functionality */
 #define SCRATCH_PAD_LOCAL_REG	(MVEBU_REGS_BASE_LOCAL_AP + 0x6F43E0)
 #define CPU_WAKEUP_COMMAND(ap)	(MVEBU_CCU_LOCL_CNTL_BASE(ap) + 0x80)
@@ -56,6 +66,8 @@ enum pll_type {
 	IO,
 	PIDI,
 	DSS,
+	PLL_CLUSTER_0_FREQ, /* PLL for cluster0 and cluster1 */
+	PLL_CLUSTER_2_FREQ, /* PLL for cluster2 and cluster3 */
 	PLL_LAST,
 	CPU_FREQ,
 	DDR_FREQ,
@@ -65,42 +77,42 @@ unsigned int pll_freq_tables[SAR_SUPPORTED_TABLES]
 			    [SAR_SUPPORTED_OPTIONS]
 			    [PLL_LAST + 2] = {
 	{
-		/* RING, IO, PIDI, DSS, CPU_FREQ*/
+		/* RING, IO, PIDI, DSS, PLL_CLUSTER_0_FREQ, PLL_CLUSTER_2_FREQ, CPU_FREQ */
 		{PLL_FREQ_1200, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_800,
-		 TARGET_FREQ_1600, DDR_FREQ_800},
+		 PLL_FREQ_1600, PLL_FREQ_1600, TARGET_FREQ_1600, DDR_FREQ_800},
 		{PLL_FREQ_1200, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2000, DDR_FREQ_1200},
+		 PLL_FREQ_2000, PLL_FREQ_2000, TARGET_FREQ_2000, DDR_FREQ_1200},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2000, DDR_FREQ_1200},
+		 PLL_FREQ_2000, PLL_FREQ_2000, TARGET_FREQ_2000, DDR_FREQ_1200},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2200, DDR_FREQ_1200},
+		 PLL_FREQ_2200, PLL_FREQ_2200, TARGET_FREQ_2200, DDR_FREQ_1200},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1333,
-		 TARGET_FREQ_2200, DDR_FREQ_1333},
+		 PLL_FREQ_2200, PLL_FREQ_2200, TARGET_FREQ_2200, DDR_FREQ_1333},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2500, DDR_FREQ_1200},
+		 PLL_FREQ_2500, PLL_FREQ_2500, TARGET_FREQ_2500, DDR_FREQ_1200},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1466,
-		 TARGET_FREQ_2500, DDR_FREQ_1466},
+		 PLL_FREQ_2500, PLL_FREQ_2500, TARGET_FREQ_2500, DDR_FREQ_1466},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1600,
-		 TARGET_FREQ_2700, DDR_FREQ_1600},
+		 PLL_FREQ_2700, PLL_FREQ_2700, TARGET_FREQ_2700, DDR_FREQ_1600},
 	},
 	{
-		/* RING, IO, PIDI, DSS, CPU_FREQ*/
+		/* RING, IO, PIDI, DSS, PLL_CLUSTER_0_FREQ, PLL_CLUSTER_2_FREQ, CPU_FREQ */
 		{PLL_FREQ_800, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_800,
-		 TARGET_FREQ_1200, DDR_FREQ_800},
+		 PLL_FREQ_1200, PLL_FREQ_1200, TARGET_FREQ_1200, DDR_FREQ_800},
 		{PLL_FREQ_1000, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_1800, DDR_FREQ_1200},
+		 PLL_FREQ_1800, PLL_FREQ_1800, TARGET_FREQ_1800, DDR_FREQ_1200},
 		{PLL_FREQ_1100, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_1800, DDR_FREQ_1200},
+		 PLL_FREQ_1800, PLL_FREQ_1800, TARGET_FREQ_1800, DDR_FREQ_1200},
 		{PLL_FREQ_1200, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_1800, DDR_FREQ_1200},
+		 PLL_FREQ_1800, PLL_FREQ_1800, TARGET_FREQ_1800, DDR_FREQ_1200},
 		{PLL_FREQ_1400, PLL_FREQ_1000, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_1800, DDR_FREQ_1200},
+		 PLL_FREQ_1800, PLL_FREQ_1800, TARGET_FREQ_1800, DDR_FREQ_1200},
 		{PLL_FREQ_1100, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2000, DDR_FREQ_1200},
+		 PLL_FREQ_2000, PLL_FREQ_2000, TARGET_FREQ_2000, DDR_FREQ_1200},
 		{PLL_FREQ_1200, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2000, DDR_FREQ_1200},
+		 PLL_FREQ_2000, PLL_FREQ_2000, TARGET_FREQ_2000, DDR_FREQ_1200},
 		{PLL_FREQ_1300, PLL_FREQ_800, PLL_FREQ_1000, PLL_FREQ_1200,
-		 TARGET_FREQ_2000, DDR_FREQ_1200},
+		 PLL_FREQ_2000, PLL_FREQ_2000, TARGET_FREQ_2000, DDR_FREQ_1200},
 	},
 };
 
@@ -109,6 +121,8 @@ unsigned int pll_base_address[PLL_LAST] = {
 	PLL_IO_ADDRESS, /* IO */
 	PLL_PIDI_ADDRESS, /* PIDI */
 	PLL_DSS_ADDRESS, /* DSS */
+	PLL_CLUSTER_1_0_ADDRES, /* PLL for cluster0 and cluster1 */
+	PLL_CLUSTER_2_3_ADDRES, /* PLL for cluster2 and cluster3 */
 };
 
 /* read efuse value which device if it's low/high frequency
@@ -242,7 +256,7 @@ int ap810_clocks_init(int ap_count)
 
 	/* write transactions to each APs' EAWG FIFO */
 	for (ap = 0 ; ap < ap_count ; ap++) {
-		if (eawg_load_transactions(trans_array, (PLL_LAST * TRANS_PER_PLL), ap)) {
+		if (eawg_load_transactions(trans_array, ((DSS + 1) * TRANS_PER_PLL), ap)) {
 			printf("couldn't load all transactions to AP%d EAWG FIFO\n", ap);
 			return -1;
 		}