diff options
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2018-07-16 12:18:03 +0200 |
|---|---|---|
| committer | Konstantin Porotchkin <kostap@marvell.com> | 2018-09-03 14:45:20 +0300 |
| commit | 0172dc9917ef19f3d7a5f80bb8c0ac1ca24cd0c6 (patch) | |
| tree | 4795eb63fb568ab193cc4abe36a4d30d44618e35 | |
| parent | 2dfe2c019f03b47eaeca800898e24f5b53d42d69 (diff) | |
mvebu: cp110: fix spelling in register definition
Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).
Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/58023
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
| -rw-r--r-- | drivers/marvell/comphy/comphy-cp110.h | 8 | ||||
| -rw-r--r-- | drivers/marvell/comphy/phy-comphy-cp110.c | 24 |
2 files changed, 16 insertions, 16 deletions
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h index 4fd4d0b5..6f5a6f0d 100644 --- a/drivers/marvell/comphy/comphy-cp110.h +++ b/drivers/marvell/comphy/comphy-cp110.h @@ -176,8 +176,8 @@ #define HPIPE_G1_SET_1_REG 0x38 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3 +#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 @@ -200,8 +200,8 @@ #define HPIPE_G2_SET_1_REG 0x40 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3 +#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index b94435e0..89c7d612 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -466,8 +466,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* G1 settings */ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; @@ -491,8 +491,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* G2 settings */ mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; @@ -1006,13 +1006,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, if (speed == COMPHY_SPEED_5_15625G) { mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; } else { mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data |= xfi_static_values->g1_rx_selmupi << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= xfi_static_values->g1_rx_selmupf << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= xfi_static_values->g1_rx_selmupf << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; data |= xfi_static_values->g1_rx_selmufi << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; @@ -1539,8 +1539,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, /* Genration 2 setting 1*/ mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); @@ -1772,8 +1772,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, /* 0xE-G1_Setting_1 */ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); |