mvebu: llc: allow llc enablement in runtime using smccc call

This patch allows to enable LLC from Linux Kernel using
smccc call. In addition, perform other required operation
for correct LLC functionally:
	- Set POC to DDR.
	- Enable L2 UniqueClean evictions.

Change-Id: Ia293dc1d1615d9872d153204bb8ffd55bc3efa11
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/56663
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

3 files changed, 46 insertions, 1 deletions

diff --git a/drivers/marvell/cache_llc.c b/drivers/marvell/cache_llc.c
index f56f68bc..b2ce5bfa 100644
--- a/drivers/marvell/cache_llc.c
+++ b/drivers/marvell/cache_llc.c
@@ -4,12 +4,16 @@
  * SPDX-License-Identifier:     BSD-3-Clause
  * https://spdx.org/licenses
  */
- 
+
 #include <assert.h>
 #include <cache_llc.h>
+#include <ccu.h>
 #include <mmio.h>
 #include <plat_def.h>
 
+#define CCU_HTC_CR(ap_index)		(MVEBU_CCU_BASE(ap_index) + 0x200)
+#define CCU_SET_POC_OFFSET		5
+
 void llc_cache_sync(int ap_index)
 {
 	mmio_write_32(LLC_CACHE_SYNC(ap_index), 0);
@@ -77,3 +81,33 @@ void llc_resume(int ap_index)
 {
 	/* TBD */
 }
+
+void llc_runtime_enable(int ap_index)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(LLC_CTRL(ap_index));
+	if (reg & LLC_CTRL_EN)
+		return;
+
+	INFO("Enabling LLC\n");
+
+	/*
+	 * Enable L2 UniqueClean evictions
+	 *  Note: this configuration assumes that LLC is configured
+	 *	  in exclusive mode.
+	 *	  Later on in the code this assumption will be validated
+	 */
+	__asm__ volatile ("mrs %0, s3_1_c15_c0_0" : "=r" (reg));
+	reg |=  (1 << 14);
+	__asm__ volatile ("msr s3_1_c15_c0_0, %0" : : "r" (reg));
+
+	llc_enable(ap_index, 1);
+
+	/* Set point of coherency to DDR.
+	 * This is required by units which have SW cache coherency
+	 */
+	reg = mmio_read_32(CCU_HTC_CR(ap_index));
+	reg |= (0x1 << CCU_SET_POC_OFFSET);
+	mmio_write_32(CCU_HTC_CR(ap_index), reg);
+}
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index 81330f44..ea7298ce 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -33,6 +33,7 @@ void llc_enable(int, int excl_mode);
 int llc_is_exclusive(int);
 void llc_save(int);
 void llc_resume(int);
+void llc_runtime_enable(int ap_index);
 #endif
 
 #endif /* _CACHE_LLC_H_ */
diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c
index aab74316..4d79cd0d 100644
--- a/plat/marvell/common/mrvl_sip_svc.c
+++ b/plat/marvell/common/mrvl_sip_svc.c
@@ -5,6 +5,8 @@
  * https://spdx.org/licenses
  */
 
+#include <ap_setup.h>
+#include <cache_llc.h>
 #include <debug.h>
 #include <runtime_svc.h>
 #include <smcc.h>
@@ -27,6 +29,7 @@
 
 /* Miscellaneous FID's' */
 #define MV_SIP_DRAM_SIZE	0x82000010
+#define MV_SIP_LLC_ENABLE	0x82000011
 
 #define MAX_LANE_NR		6
 #define MVEBU_COMPHY_OFFSET	0x441000
@@ -47,6 +50,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
 			       u_register_t flags)
 {
 	u_register_t ret;
+	int i;
 
 	debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
 						 __func__, smc_fid, x1, x2, x3);
@@ -98,6 +102,12 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
 		/* x1:  ap_base_addr */
 		ret = mvebu_get_dram_size(x1);
 		SMC_RET1(handle, ret);
+	case MV_SIP_LLC_ENABLE:
+		for (i = 0; i < ap_get_count(); i++)
+			llc_runtime_enable(i);
+
+		SMC_RET1(handle, 0);
+
 	default:
 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
 		SMC_RET1(handle, SMC_UNK);