mvebu: add unified api to get number of APs

This is usefull to make drivers that server different
types of APs: 810/806/807 more generic.

Change-Id: I7a24b8a80e2b3eed0b77a95b5a2f40b7cad4180c
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/57166
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

12 files changed, 53 insertions, 38 deletions

diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c
index 96025099..b3f5fa3b 100644
--- a/drivers/marvell/mochi/ap807_setup.c
+++ b/drivers/marvell/mochi/ap807_setup.c
@@ -215,3 +215,9 @@ void ap_ble_init(void)
 	ap807_dram_phy_access_config();
 }
 
+int ap_get_count(void)
+{
+	return 1;
+}
+
+
diff --git a/drivers/marvell/mochi/ap810_setup.c b/drivers/marvell/mochi/ap810_setup.c
index d67f9175..6f1aadad 100644
--- a/drivers/marvell/mochi/ap810_setup.c
+++ b/drivers/marvell/mochi/ap810_setup.c
@@ -42,7 +42,7 @@ void ap810_enumeration_algo(void)
 	int ap_id;
 
 	/* In case of single AP, no need to configure MRI-xbar */
-	if (ap810_get_ap_count() == 1)
+	if (ap_get_count() == 1)
 		return;
 
 	debug_enter();
@@ -83,10 +83,10 @@ void ap810_enumeration_algo(void)
 	 *      AP0.PORT0_ROUTING0: {3,0}
 	 *      AP1.PORT0_ROUTING0: {0,1}
 	 */
-	if (ap810_get_ap_count() == 2) {
+	if (ap_get_count() == 2) {
 		mmio_write_32(MRI_XBAR_PORTx_ROUTING0(0, 0), 0x30);
 		mmio_write_32(MRI_XBAR_PORTx_ROUTING0(1, 0), 0x1);
-	} else if (ap810_get_ap_count() == 4) {
+	} else if (ap_get_count() == 4) {
 		mmio_write_32(MRI_XBAR_PORTx_ROUTING0(0, 0), 0x1340);
 		mmio_write_32(MRI_XBAR_PORTx_ROUTING0(1, 0), 0x1302);
 		mmio_write_32(MRI_XBAR_PORTx_ROUTING0(2, 0), 0x4013);
@@ -97,10 +97,10 @@ void ap810_enumeration_algo(void)
 	mmio_write_32(CCU_B_LTC_CR(0), reg);
 
 	/* Test AP access */
-	if (ap810_get_ap_count() == 2) {
+	if (ap_get_count() == 2) {
 		/* Read status from AP1 */
 		INFO("Test AP1: 0x%x\n", mmio_read_32(MRI_XBAR_PORTx_ROUTING0(1, 0)));
-	} else if (ap810_get_ap_count() == 4) {
+	} else if (ap_get_count() == 4) {
 		/* Read status from AP1 */
 		INFO("Test AP1: 0x%x\n", mmio_read_32(MRI_XBAR_PORTx_ROUTING0(1, 0)));
 		/* Read status from AP2 */
@@ -110,7 +110,7 @@ void ap810_enumeration_algo(void)
 	}
 
 	/* Update AP-ID of every AP die in the system */
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++)
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++)
 		mmio_write_32(MVEBU_CCU_GUID(ap_id), ap_id);
 	debug_exit();
 }
@@ -119,7 +119,7 @@ void ap810_enumeration_algo(void)
  * ports connected to AP0. For now assume
  * that AP0 is connected to all the APs in the system
  */
-int ap810_get_ap_count(void)
+int ap_get_count(void)
 {
 	uint32_t reg;
 	int count;
@@ -152,7 +152,7 @@ int ap810_get_ap_count(void)
  */
 int ap810_get_cp_per_ap_static_cnt(int ap_id)
 {
-	const int ap_count = ap810_get_ap_count();
+	const int ap_count = ap_get_count();
 	int cps_per_ap_id = CP110_DIE_NUM / ap_count;
 	int reminder = CP110_DIE_NUM % ap_count;
 
@@ -230,7 +230,7 @@ void ap810_setup_banked_rgf(int ap_id)
 	 * Open access for all IO & proccess stops, because MC & SG
 	 * stop can't start transcations to another ring
 	 */
-	val = AP810_MAX_AP_MASK >> (AP810_MAX_AP_NUM - ap810_get_ap_count());
+	val = AP810_MAX_AP_MASK >> (AP810_MAX_AP_NUM - ap_get_count());
 	for (stop = 0; stop < AP810_S_END; stop++) {
 		switch (stop) {
 		case AP810_S0_SMC0:
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c
index 9eacfbec..1fa7e4b0 100644
--- a/drivers/marvell/mochi/apn806_setup.c
+++ b/drivers/marvell/mochi/apn806_setup.c
@@ -249,3 +249,8 @@ void ap_ble_init(void)
 {
 }
 
+int ap_get_count(void)
+{
+	return 1;
+}
+
diff --git a/include/drivers/marvell/mochi/ap810_setup.h b/include/drivers/marvell/mochi/ap810_setup.h
index 92b678fa..d703cd89 100644
--- a/include/drivers/marvell/mochi/ap810_setup.h
+++ b/include/drivers/marvell/mochi/ap810_setup.h
@@ -8,8 +8,9 @@
 #ifndef __APN810_SETUP_H__
 #define __APN810_SETUP_H__
 
+#include <ap_setup.h>
+
 void ap810_enumeration_algo(void);
-int ap810_get_ap_count(void);
 int ap810_get_cp_per_ap_cnt(int);
 int ap810_get_cp_per_ap_static_cnt(int);
 int ap810_rev_id_get(int ap_index);
diff --git a/include/drivers/marvell/mochi/ap_setup.h b/include/drivers/marvell/mochi/ap_setup.h
index cf0de93b..1e6af6b7 100644
--- a/include/drivers/marvell/mochi/ap_setup.h
+++ b/include/drivers/marvell/mochi/ap_setup.h
@@ -9,4 +9,6 @@
 
 void ap_init(void);
 void ap_ble_init(void);
+int ap_get_count(void);
+
 #endif /* __AP_SETUP_H__ */
diff --git a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c
index f3af6314..e6702689 100644
--- a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c
+++ b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c
@@ -80,7 +80,7 @@ struct addr_map_win gwin_memory_map4_ap3[] = {
 
 int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *size)
 {
-	int ap_count = ap810_get_ap_count();
+	int ap_count = ap_get_count();
 
 	if (ap_count < 3) {
 		switch (ap) {
@@ -172,7 +172,7 @@ uint32_t marvell_get_ccu_gcr_target(int ap)
 
 int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size)
 {
-	int ap_count = ap810_get_ap_count();
+	int ap_count = ap_get_count();
 
 	if (ap_count < 3) {
 		switch (ap) {
@@ -243,7 +243,7 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index)
 
 int marvell_get_io_win_memory_map(int ap, struct addr_map_win **win, uint32_t *size)
 {
-	int ap_count = ap810_get_ap_count();
+	int ap_count = ap_get_count();
 
 	if (ap_count < 3) {
 		switch (ap) {
@@ -513,7 +513,7 @@ int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintpt
 {
 	int  ap, cp;
 
-	for (ap = 0; ap < ap810_get_ap_count(); ap++) {
+	for (ap = 0; ap < ap_get_count(); ap++) {
 		for (cp = 0; cp < ap810_get_cp_per_ap_cnt(ap); cp++) {
 			if (MVEBU_CP_REGS_BASE(ap, cp) == base) {
 				*win = iob_map[ap][cp];
@@ -558,7 +558,7 @@ int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintpt
 {
 	int  ap, cp;
 
-	for (ap = 0; ap < ap810_get_ap_count(); ap++) {
+	for (ap = 0; ap < ap_get_count(); ap++) {
 		for (cp = 0; cp < ap810_get_cp_per_ap_cnt(ap); cp++) {
 			if (MVEBU_CP_REGS_BASE(ap, cp) == base) {
 				*win = amb_map[ap][cp];
diff --git a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
index 1ce1ac93..e0d74978 100644
--- a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
@@ -42,7 +42,7 @@ static void bl2_store_num_of_cps(void)
 {
 	int i;
 
-	for (i = 0; i < ap810_get_ap_count(); i++)
+	for (i = 0; i < ap_get_count(); i++)
 		mmio_write_32(MVEBU_REGS_BASE_AP(i) + GP_LOG_REG_0,
 			      ap810_get_cp_per_ap_cnt(i));
 }
@@ -57,7 +57,7 @@ static void bl2_plat_mss_remap(void)
 	 * then MSS remap will remap the address to 0x81_0000_0000
 	 */
 	/* MSS remap for CP1 */
-	for (i = 0; i < ap810_get_ap_count(); i++) {
+	for (i = 0; i < ap_get_count(); i++) {
 		mmio_write_32(MSS_REMAP_WIN1_ALR(i), MSS_WIN_ALR_VAL);
 		mmio_write_32(MSS_REMAP_WIN1_AHR(i), MSS_WIN_AHR_VAL);
 		mmio_write_32(MSS_REMAP_WIN1_CR(i), MSS_WIN1_CR_ADDR_MASK |
@@ -114,7 +114,7 @@ uint32_t bl2_plat_get_cp_count(int ap_idx)
 
 uint32_t bl2_plat_get_ap_count(void)
 {
-	return ap810_get_ap_count();
+	return ap_get_count();
 }
 
 void bl2_plat_configure_mss_windows(uintptr_t mss_regs)
diff --git a/plat/marvell/a8k-p/common/plat_bl1_setup.c b/plat/marvell/a8k-p/common/plat_bl1_setup.c
index 191158a8..c406c4f3 100644
--- a/plat/marvell/a8k-p/common/plat_bl1_setup.c
+++ b/plat/marvell/a8k-p/common/plat_bl1_setup.c
@@ -137,7 +137,7 @@ static void a8kp_mci_turn_off_links(uintptr_t mci_base)
 	int ap_id, cp_id, mci_id;
 
 	/* Go over the APs and turn off the link of MCIs */
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		ap810_win_route_open(ap_id, mci_base, MVEBU_MCI_REG_SIZE_REMAP, IO_0_TID);
 
 		/* Go over the MCIs  */
@@ -214,7 +214,7 @@ static int mci_wa_initialize(void)
 	a8kp_mci_mpp_reset(MPP_MCI_RELEASE_FROM_RESET);
 
 	/* 3rd stage - Re-init the MCI phy in AP side & in CP side */
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		ap810_win_route_open(ap_id, mci_base, MVEBU_MCI_REG_SIZE_REMAP, IO_0_TID);
 
 		/* Go over the MCIs in every APx */
@@ -304,7 +304,7 @@ static int a8kp_mci_configure_threshold(void)
 	debug_enter();
 
 	/* Run MCI WA for performance improvements */
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		ap810_win_route_open(ap_id, mci_base, MVEBU_MCI_REG_SIZE_REMAP, IO_0_TID);
 
 		/* Go over the MCIs in every APx */
@@ -376,7 +376,7 @@ static void update_cp110_default_win(void)
 	/* Go over the APs and update every CP with
 	 * the new configuration address
 	 */
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		ap810_win_route_open(ap_id, cp110_temp_base, MVEBU_CP_DEFAULT_BASE_SIZE, IO_0_TID);
 
 		/* Go over the connected CPx in the APx */
@@ -421,7 +421,7 @@ static void ap810_addr_decode_init(void)
 
 	debug_enter();
 
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		INFO("Initialize address decode for AP-%d\n", ap_id);
 		/* configure IO-WIN windows */
 		init_io_win(ap_id);
@@ -449,7 +449,7 @@ static void ap810_soc_misc_configurations(void)
 
 	debug_enter();
 
-	for (ap = 0; ap < ap810_get_ap_count(); ap++) {
+	for (ap = 0; ap < ap_get_count(); ap++) {
 		/* Un-mask Watchdog reset from influencing the SYSRST_OUTn.
 		 * Otherwise, upon WD timeout, the WD reset singal won't trigger reset
 		 */
diff --git a/plat/marvell/a8k-p/common/plat_bl31_setup.c b/plat/marvell/a8k-p/common/plat_bl31_setup.c
index 5c97ca15..de5a20fa 100644
--- a/plat/marvell/a8k-p/common/plat_bl31_setup.c
+++ b/plat/marvell/a8k-p/common/plat_bl31_setup.c
@@ -83,7 +83,7 @@ static void cp110_die_init(void)
 {
 	int ap_id, cp_id;
 
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++)
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++)
 		for (cp_id = 0; cp_id < ap810_get_cp_per_ap_cnt(ap_id); cp_id++)
 			cp110_init(MVEBU_CP_REGS_BASE(ap_id, cp_id),
 				   STREAM_ID_BASE +
@@ -123,7 +123,7 @@ static void ap810_dvm_affinity(int ap_id)
 		mmio_write_32(CCU_HTC_GACR(ap_id, i), AP810_MAX_AP_MASK);
 
 	mmio_write_32(CCU_HTC_GASET(ap_id),
-			AP810_MAX_AP_MASK >> (AP810_MAX_AP_NUM - ap810_get_ap_count()));
+			AP810_MAX_AP_MASK >> (AP810_MAX_AP_NUM - ap_get_count()));
 
 	debug_exit();
 }
@@ -279,7 +279,7 @@ static void ap810_setup_events(int ap_id)
 	 */
 	switch (ap_id) {
 	case 0:
-		if (ap810_get_ap_count() == 2) {
+		if (ap_get_count() == 2) {
 			/* Port 2 - unmask local GEvent */
 			mmio_write_32(GEVENT_CR_PORTx_EVENT_MASK(ap_id, 2), 0x2f);
 			/* Port 4 (Local) - unmask Port 2 */
@@ -296,7 +296,7 @@ static void ap810_setup_events(int ap_id)
 		}
 		break;
 	case 1:
-		if (ap810_get_ap_count() == 2) {
+		if (ap_get_count() == 2) {
 			/* Port 0 - unmask local GEvent */
 			mmio_write_32(GEVENT_CR_PORTx_EVENT_MASK(ap_id, 0), 0x2f);
 			/* Port 4 (Local) - unmask Port 0 */
@@ -347,7 +347,7 @@ static void ap810_generic_timer_init(void)
 	 * In this code, we re-initialize the timer in the all APs.
 	 * TODO: move this code to be timer calibration algorithm
 	 */
-	for (i = 0; i < ap810_get_ap_count(); i++) {
+	for (i = 0; i < ap_get_count(); i++) {
 		/* Disable timer */
 		reg = mmio_read_32(MVEBU_MSS_GTCR_REG(i));
 		reg &= ~MVEBU_MSS_GTCR_ENABLE_BIT;
@@ -358,7 +358,7 @@ static void ap810_generic_timer_init(void)
 		mmio_write_32(MVEBU_MSS_GTCVHR_REG(i), 0x0);
 	}
 
-	if (ap810_get_ap_count() == 2) {
+	if (ap_get_count() == 2) {
 		/* Enable timer */
 		mmio_write_32(MVEBU_MSS_GTCR_REG(0), MVEBU_MSS_GTCR_ENABLE_BIT);
 		mmio_write_32(MVEBU_MSS_GTCR_REG(1), MVEBU_MSS_GTCR_ENABLE_BIT);
@@ -369,7 +369,7 @@ static void ap810_generic_timer_init(void)
 		ap1 = mmio_read_32(MVEBU_MSS_GTCVLR_REG(1));
 		INFO("Read time AP0 = %x - AP1 = %x\n", ap0, ap1);
 #endif
-	} else if (ap810_get_ap_count() == 4) {
+	} else if (ap_get_count() == 4) {
 		mmio_write_32(MVEBU_MSS_GTCR_REG(0), MVEBU_MSS_GTCR_ENABLE_BIT);
 		mmio_write_32(MVEBU_MSS_GTCR_REG(1), MVEBU_MSS_GTCR_ENABLE_BIT);
 		mmio_write_32(MVEBU_MSS_GTCR_REG(2), MVEBU_MSS_GTCR_ENABLE_BIT);
@@ -396,7 +396,7 @@ static void ap810_bl31_init(void)
 
 	debug_enter();
 
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		INFO("Initialize AP-%d\n", ap_id);
 		/* Setup Aurora2. */
 		ap810_init_aurora2(ap_id);
diff --git a/plat/marvell/a8k-p/common/plat_ble_setup.c b/plat/marvell/a8k-p/common/plat_ble_setup.c
index b84b5b66..8e9358ee 100644
--- a/plat/marvell/a8k-p/common/plat_ble_setup.c
+++ b/plat/marvell/a8k-p/common/plat_ble_setup.c
@@ -5,6 +5,7 @@
  * https://spdx.org/licenses
  */
 
+#include <ap_setup.h>
 #include <ap810_setup.h>
 #include <ap810_init_clocks.h>
 #include <a8kp_plat_def.h>
@@ -43,7 +44,7 @@ int ble_plat_setup(int *skip)
 
 #if !PALLADIUM
 	/* SW WA for AP link bring-up over JTAG connection */
-	if ((ap810_get_ap_count() != 1) &&
+	if ((ap_get_count() != 1) &&
 	    (ap810_rev_id_get(MVEBU_AP0) == MVEBU_AP810_REV_ID_A0))
 		jtag_init_ihb_dual_ap();
 #endif
@@ -56,7 +57,7 @@ int ble_plat_setup(int *skip)
 	ap810_enumeration_algo();
 
 	/* init clocks for single AP */
-	ap810_clocks_init(ap810_get_ap_count());
+	ap810_clocks_init(ap_get_count());
 
 	/* TODO: need to check if need early cpu powerdown */
 
diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c
index 0102736c..36052da1 100644
--- a/plat/marvell/a8k-p/common/plat_dram.c
+++ b/plat/marvell/a8k-p/common/plat_dram.c
@@ -131,7 +131,7 @@ void plat_dram_freq_update(enum ddr_freq freq_option)
 	uint32_t ifaces_size, i, ap_id;
 
 	/* Update DDR topology for all APs for all interfaces */
-	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap_get_count(); ap_id++) {
 		plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size);
 		for (i = 0; i < ifaces_size; i++, iface++)
 			iface->tm.interface_params[0].memory_freq = freq_option;
@@ -302,7 +302,7 @@ static void plat_dram_interfaces_update(void)
 {
 	struct mv_ddr_iface *iface = NULL;
 	uint32_t ifaces_size, i, ap_id, iface_cnt;
-	const uint32_t ap_cnt = ap810_get_ap_count();
+	const uint32_t ap_cnt = ap_get_count();
 
 	debug_enter();
 
@@ -395,7 +395,7 @@ int plat_dram_init(void)
 {
 	struct mv_ddr_iface *iface = NULL;
 	uint32_t ifaces_size, i, ap_id, ret, iface_cnt;
-	const uint32_t ap_cnt = ap810_get_ap_count();
+	const uint32_t ap_cnt = ap_get_count();
 	uint64_t ap_dram_size;
 	uint32_t ap_dram_tgt;
 
diff --git a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c
index 5110286d..75d359c9 100644
--- a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c
+++ b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c
@@ -112,7 +112,7 @@ int gic600_multi_chip_init(void)
 
 	INFO("GIC-600 Multi Chip initialization\n");
 	/* Go over APs and configure the routing table */
-	for (nb_id = 0; nb_id < ap810_get_ap_count(); nb_id++) {
+	for (nb_id = 0; nb_id < ap_get_count(); nb_id++) {
 		unsigned int spi_block_min, spi_blocks;
 
 		INFO("Configure AP %d\n", nb_id);