diff options
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2018-07-12 12:53:04 +0200 |
|---|---|---|
| committer | Konstantin Porotchkin <kostap@marvell.com> | 2018-09-03 14:45:20 +0300 |
| commit | 2dfe2c019f03b47eaeca800898e24f5b53d42d69 (patch) | |
| tree | 028ba6319140849155d452ab56206e091d820313 | |
| parent | ac05b4e57ed1affbcf803373059247de59d23129 (diff) | |
mvebu: cp110: do not perform comphy power on/off after rx_training was run
If the rx_training was triggered (e.g. in U-Boot) do not perform comphy
power on/off on the serdes for which the rx training was triggered. Thanks
to this change the rx_training results will not be reset after moving from
U-Boot to Linux.
Change-Id: I6748e570b2f386cb5f65d7dc8cfff69424a9db5e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/58022
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | drivers/marvell/comphy/phy-comphy-cp110.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index 4982e5a7..b94435e0 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -151,6 +151,8 @@ enum pcie_link_width { PCIE_LNK_WIDTH_UNKNOWN = 0xFF, }; +_Bool rx_trainng_done[AP_NUM][CP_NUM][MAX_LANE_NR] = {0}; + static void mvebu_cp110_get_ap_and_cp_nr(uint8_t *ap_nr, uint8_t *cp_nr, uint64_t comphy_base) { #if (AP_NUM == 1) @@ -816,6 +818,12 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base); + if (rx_trainng_done[ap_nr][cp_nr][comphy_index]) { + debug("Skipping %s for comphy[%d][%d][%d], due to rx training\n", + __func__, ap_nr, cp_nr, comphy_index); + return 0; + } + const struct xfi_params *xfi_static_values = &xfi_static_values_tab[ap_nr][cp_nr][comphy_index]; @@ -2205,6 +2213,8 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base, hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG, mmio_read_32(hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG)); + rx_trainng_done[ap_nr][cp_nr][comphy_index] = 1; + return 0; } @@ -2317,9 +2327,18 @@ int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint8_t comphy_index) { uintptr_t sd_ip_addr, comphy_ip_addr; uint32_t mask, data; + uint8_t ap_nr, cp_nr; debug_enter(); + mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base); + + if (rx_trainng_done[ap_nr][cp_nr][comphy_index]) { + debug("Skipping %s for comphy[%d][%d][%d], due to rx training\n", + __func__, ap_nr, cp_nr, comphy_index); + return 0; + } + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); comphy_ip_addr = COMPHY_ADDR(comphy_base, comphy_index); |