diff options
| author | Konstantin Porotchkin <kostap@marvell.com> | 2018-07-23 13:56:54 +0300 |
|---|---|---|
| committer | Konstantin Porotchkin <kostap@marvell.com> | 2018-09-03 14:48:32 +0300 |
| commit | 77d5a2b3e2635002bfc7042abb0388395648bf71 (patch) | |
| tree | dbc422ee19a2e7315a3d40840e9bc69e5a521daa | |
| parent | 71b6429c5769b0c5b7165217dd441ea2a0318bfa (diff) | |
plat: marvell: align the sources with mainline TF-A
Following the acception of Marvell platform support in the mainline
TF-A code, some changes triggered by the TF-A team review should be
ported back.
This patch introduces changes (mostly cosmetic) that sync between
the mainline and LSP code bases.
- Limit line length to 80 characters for passing through Linux checkpatch
- Make all comment blocks comply the Linux kernel coduing style
- Arrange all includes in alphabetical order
- Rename plat_config.h to armada_common.h (a8k_common in the mainline,
but we should take into account next platform support as well)
- Rename plat_private.h to marvell_plat_priv.h
- Rename plat_def.h to mvebu_def.h
Change-Id: Idd542c8a7d4ff8d8fb67c3601410308be5aed8e5
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/58282
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
186 files changed, 3519 insertions, 2567 deletions
diff --git a/acknowledgements.rst b/acknowledgements.rst index 9b81b6c5..5686a580 100644 --- a/acknowledgements.rst +++ b/acknowledgements.rst @@ -14,5 +14,7 @@ Xilinx, Inc. NXP Semiconductors +Marvell International Ltd. + Individuals ----------- diff --git a/ble/ble.ld.S b/ble/ble.ld.S index 8a01ce43..d7a05928 100644 --- a/ble/ble.ld.S +++ b/ble/ble.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -1,4 +1,4 @@ -# Copyright (C) 2016, 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/ble/ble_main.c b/ble/ble_main.c index 7d41e6a0..3c9f8a6f 100644 --- a/ble/ble_main.c +++ b/ble/ble_main.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -8,10 +8,10 @@ #include <arch_helpers.h> #include <debug.h> #include <console.h> +#include <marvell_plat_priv.h> #include <marvell_pm.h> #include <platform_def.h> #include <plat_marvell.h> -#include <plat_private.h> #include <string.h> #define BR_FLAG_SILENT 0x1 @@ -82,7 +82,7 @@ int exec_ble_main(int bootrom_flags) * This should be done until the BootROM have a native support * for the system restore flow. */ - ble_prepare_exit(); + marvell_ble_prepare_exit(); bootrom_exit(); } diff --git a/ble/ble_mem.S b/ble/ble_mem.S index be5108b2..a48d5463 100644 --- a/ble/ble_mem.S +++ b/ble/ble_mem.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -11,9 +11,9 @@ #define PTE_NON_EXEC_OFF 54 /* XN - eXecute Never bit offset - see VMSAv8-64 */ - .globl ble_prepare_exit + .globl marvell_ble_prepare_exit -func ble_prepare_exit +func marvell_ble_prepare_exit /* * Read the page table base and set the first page to be executable. * This is required for jumping to DRAM for further execution. @@ -27,4 +27,4 @@ func ble_prepare_exit dsb sy isb ret -endfunc ble_prepare_exit +endfunc marvell_ble_prepare_exit diff --git a/docs/marvell/build.txt b/docs/marvell/build.txt index 300c09f3..5646bdd0 100644 --- a/docs/marvell/build.txt +++ b/docs/marvell/build.txt @@ -1,17 +1,17 @@ -ATF Build Instructions +TF-A Build Instructions ====================== -This section describes how to compile the ARM Trusted Firmware (ATF) project for Marvell's platforms. +This section describes how to compile the ARM Trusted Firmware (TF-A) project for Marvell's platforms. Build Instructions ------------------ (1) Set the cross compiler:: - > export CROSS_COMPILE=/path/to/toolchain/aarch64-marvell-linux-gnu- + > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu- (2) Set path for FIP images: - Set U-Boot image path (relatively to ATF root or absolute path):: + Set U-Boot image path (relatively to TF-A root or absolute path):: > export BL33=path/to/u-boot.bin @@ -37,7 +37,7 @@ Build Instructions > make distclean -(5) Build ATF: +(5) Build TF-A: There are several build options: @@ -46,14 +46,16 @@ Build Instructions - LOG_LEVEL: defines the level of logging which will be purged to the default output port. LOG_LEVEL_NONE 0 - LOG_LEVEL_NOTICE 10 - LOG_LEVEL_ERROR 20 + LOG_LEVEL_ERROR 10 + LOG_LEVEL_NOTICE 20 LOG_LEVEL_WARNING 30 LOG_LEVEL_INFO 40 LOG_LEVEL_VERBOSE 50 - USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the - BL memory map or not. It should be set to 0. + BL memory map or not. + + - LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1). - MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted. @@ -67,7 +69,7 @@ Build Instructions Usage example: MV_DDR_PATH=path/to/mv_ddr The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter - is neccesary for A37x0. + is necessary for A37x0. - DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0. Supported Options: @@ -114,7 +116,7 @@ Build Instructions suitable for a8xxY SoC, where "Y" is a number of connected CPs and "xx" is a number of CPU cores. Valid values with CP_NUM is in a range of 0 to 8. The CPs defined by this parameter are evenly distributed across interconnected APs that in turn - are dynamically detected. For instance, if the CP_NUM=6 and the ATF detects 2 interconnected + are dynamically detected. For instance, if the CP_NUM=6 and the TF-A detects 2 interconnected APs, each AP assumed to have 3 attached CPs. With the same amount of APs and CP_NUM=3, the AP0 will have 2 CPs connected and AP1 - a just single CP. @@ -143,26 +145,26 @@ Build Instructions Special Build Flags -------------------- - - PALLADIUM: Enables building ATF for palladium target. This mainly involves changing the UART baud rate + - PALLADIUM: Enables building TF-A for palladium target. This mainly involves changing the UART baud rate and the timer frequency to a lower values to match palladium's setup. - PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build atf. In order to build uart recovery image this operation should be disabled for a70x0 and a80x0 - because of hardware limitation(boot from secondary image can interrrupt uart recovery process). + because of hardware limitation(boot from secondary image can interrupt uart recovery process). This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file -(for more information about build options, please refer to section 'Summary of build options' in ATF user-guide: +(for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide: https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/user-guide.md) Build output ------------- -Marvell's ATF compilation generates 7 files: +Marvell's TF-A compilation generates 7 files: - ble.bin - BLe image - bl1.bin - BL1 image - bl2.bin - BL2 image - bl31.bin - BL31 image - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) - - boot-image.bin - ATF image (contains BL1 and FIP images) + - boot-image.bin - TF-A image (contains BL1 and FIP images) - flash-image.bin - Image which contains boot-image.bin and SPL image; should be placed on the boot flash/device. diff --git a/docs/marvell/misc/mvebu-a8k-addr-map.txt b/docs/marvell/misc/mvebu-a8k-addr-map.txt new file mode 100644 index 00000000..586e8b73 --- /dev/null +++ b/docs/marvell/misc/mvebu-a8k-addr-map.txt @@ -0,0 +1,47 @@ +Address decoding flow and address translation units of Marvell Armada 8K SoC family + ++--------------------------------------------------------------------------------------------------+ +| +-------------+ +--------------+ | +| | Memory +----- DRAM CS | | +|+------------+ +-----------+ +-----------+ | Controller | +--------------+ | +|| AP DMA | | | | | +-------------+ | +|| SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ | +|| MCI-0/1 | | | | | | Memory | | +|+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ | +| | | | | +----- Translaton | |AP | | +| | | | | | +-------------+ |Configuration| | +| | | +-----+ +-------------------------Space | | +| | | +-------------+ | CCU | +-------------+ | +| | | | MMU +---------+ Windows | +-----------+ +-------------+ | +| | +-| translation | | Lookup +---- +--------- AP SPI | | +| | +-------------+ | | | | +-------------+ | +| | +-------------+ | | | IO | +-------------+ | +| +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | | +| | translation | +------------+ | Lookup | +-------------+ | +| +---------+---+ | | +-------------+ | +| - | | +--------- AP STM | | +| +----------------- | | +-------------+ | +| AP | | +-+---------+ | ++---------------------------------------------------------------|----------------------------------+ ++-------------|-------------------------------------------------|----------------------------------+ +| CP | +-------------+ +------+-----+ +-------------------+ | +| | | | | +------- SB CFG Space | | +| | | DIOB | | | +-------------------+ | +| | | Windows ----------------- IOB | +-------------------+ | +| | | Control | | Windows +------| SB PCIe-0 - PCIe2 | | +| | | | | Lookup | +-------------------+ | +| | +------+------+ | | +-------------------+ | +| | | | +------+ SB NAND | | +| | | +------+-----+ +-------------------+ | +| | | | | +| | | | | +| +------------------+ +------------+ +------+-----+ +-------------------+ | +| | Network Engine | | | | +------- SB SPI-0/SPI-1 | | +| | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ | +| | SATA, USB | | DMA | | Windows | +-------------------+ | +| | SD/eMMC | | | | Lookup +------- SB Device Bus | | +| | TDM, I2C | | | | | +-------------------+ | +| +------------------+ +------------+ +------------+ | +| | ++--------------------------------------------------------------------------------------------------+ + diff --git a/docs/marvell/misc/mvebu-amb.txt b/docs/marvell/misc/mvebu-amb.txt index 1b22eeea..2a7a41ec 100644 --- a/docs/marvell/misc/mvebu-amb.txt +++ b/docs/marvell/misc/mvebu-amb.txt @@ -1,6 +1,8 @@ AMB - AXI MBUS address decoding ------------------------------- +AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs. + - The Runit offers a second level of address windows lookup. It is used to map transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR). - The Runit contains eight configurable windows. Each window defines a contiguous, diff --git a/docs/marvell/misc/mvebu-ccu.txt b/docs/marvell/misc/mvebu-ccu.txt index 337a5c6c..97640276 100644 --- a/docs/marvell/misc/mvebu-ccu.txt +++ b/docs/marvell/misc/mvebu-ccu.txt @@ -1,6 +1,8 @@ Marvell CCU address decoding bindings ===================================== +CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. + The CCU node includes a description of the address decoding configuration. Mandatory functions: diff --git a/docs/marvell/misc/mvebu-io-win.txt b/docs/marvell/misc/mvebu-io-win.txt index 59e4b657..c83ad1fd 100644 --- a/docs/marvell/misc/mvebu-io-win.txt +++ b/docs/marvell/misc/mvebu-io-win.txt @@ -1,6 +1,8 @@ Marvell IO WIN address decoding bindings ===================================== +IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. + The IO WIN includes a description of the address decoding configuration. Transactions that are decoded by CCU windows as IO peripheral, have an additional diff --git a/docs/marvell/misc/mvebu-iob.txt b/docs/marvell/misc/mvebu-iob.txt index 6dea0a2e..97ec09d0 100644 --- a/docs/marvell/misc/mvebu-iob.txt +++ b/docs/marvell/misc/mvebu-iob.txt @@ -1,6 +1,8 @@ Marvell IOB address decoding bindings ===================================== +IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. + The IOB includes a description of the address decoding configuration. IOB supports up to n (in CP110 n=24) windows for external memory transaction. diff --git a/docs/marvell/porting.txt b/docs/marvell/porting.txt index e264421a..5f0ad3f7 100644 --- a/docs/marvell/porting.txt +++ b/docs/marvell/porting.txt @@ -1,13 +1,13 @@ -ATF Porting Guide +TF-A Porting Guide ================= -This section describes how to port ATF to a customer board, assuming that the SoC being used is already supported -in ATF. +This section describes how to port TF-A to a customer board, assuming that the SoC being used is already supported +in TF-A. Source Code Structure --------------------- -- The cusomer platform specific code shall reside under "plat/marvell/<soc family>/<soc>_cust" +- The customer platform specific code shall reside under "plat/marvell/<soc family>/<soc>_cust" (e.g. 'plat/marvell/a8k/a7040_cust'). - The platform name for build purposes is called "<soc>_cust" (e.g. a7040_cust). - The build system will reuse all files from within the soc directory, and take only the porting @@ -47,7 +47,7 @@ Armada-70x0/Armada-80x0 Porting In A7040-DB specific implementation (plat/marvell/a8k/a70x0/board/marvell_plat_config.c), the image skip is implemented using GPIO: mpp 33 (SW5). - Before reseting the board make sure there is a valid image on the next flash address: + Before resetting the board make sure there is a valid image on the next flash address: -tftp [valid address] flash-image.bin -sf update [valid address] 0x2000000 [size] @@ -56,10 +56,10 @@ Armada-70x0/Armada-80x0 Porting - DDR Porting (dram_port.c): - This file defines the dram topology and parameters of the target board. - - The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (ATF). - - The DDR driver called mv_ddr is released separately apart from ATF sources. + - The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (TF-A). + - The DDR driver called mv_ddr is released separately apart from TF-A sources. - The BLE and consequently, the DDR init code is executed at the early stage of the boot process. - - Each supported platform of the ATF has its own DDR porting file called dram_port.c located at + - Each supported platform of the TF-A has its own DDR porting file called dram_port.c located at ``atf/plat/marvell/a8k/<platform>/board`` directory. - Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed porting description. - The build target directory is "build/<platform>/release/ble". diff --git a/drivers/marvell/amb_adec.c b/drivers/marvell/amb_adec.c index 6051a51d..d1c930ec 100644 --- a/drivers/marvell/amb_adec.c +++ b/drivers/marvell/amb_adec.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */ + +#include <armada_common.h> #include <debug.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -41,10 +43,10 @@ static void amb_check_win(struct addr_map_win *win, uint32_t win_num) /* make sure the base address is in 16-bit range */ if (win->base_addr > AMB_BASE_ADDR_MASK) { - printf("Warning: Window %d: base address is too big 0x%llx\n", + WARN("Window %d: base address is too big 0x%llx\n", win_num, win->base_addr); win->base_addr = AMB_BASE_ADDR_MASK; - printf("Set the base address to 0x%llx\n", win->base_addr); + WARN("Set the base address to 0x%llx\n", win->base_addr); } base_addr = win->base_addr << AMB_BASE_OFFSET; @@ -52,17 +54,17 @@ static void amb_check_win(struct addr_map_win *win, uint32_t win_num) /* check if address is aligned to 1M */ if (IS_NOT_ALIGN(base_addr, AMB_WIN_ALIGNMENT_1M)) { win->base_addr = ALIGN_UP(base_addr, AMB_WIN_ALIGNMENT_1M); - printf("Warning: Window %d: base address unaligned to 0x%x\n", + WARN("Window %d: base address unaligned to 0x%x\n", win_num, AMB_WIN_ALIGNMENT_1M); - printf("Align up the base address to 0x%llx\n", win->base_addr); + WARN("Align up the base address to 0x%llx\n", win->base_addr); } /* size parameter validity check */ if (!IS_POWER_OF_2(win->win_size)) { - printf("Warning: Window %d: window size is not power of 2 (0x%llx)\n", + WARN("Window %d: window size is not power of 2 (0x%llx)\n", win_num, win->win_size); win->win_size = ROUND_UP_TO_POW_OF_2(win->win_size); - printf("Rounding size to 0x%llx\n", win->win_size); + WARN("Rounding size to 0x%llx\n", win->win_size); } } @@ -70,9 +72,12 @@ static void amb_enable_win(struct addr_map_win *win, uint32_t win_num) { uint32_t ctrl, base, size; - size = (win->win_size / AMB_WIN_ALIGNMENT_64K) - 1; /* size is 64KB granularity. - * The number of 1s specifies the size of the - * window in 64 KB granularity. 0 is 64KB */ + /* + * size is 64KB granularity. + * The number of ones specifies the size of the + * window in 64 KB granularity. 0 is 64KB + */ + size = (win->win_size / AMB_WIN_ALIGNMENT_64K) - 1; ctrl = (size << AMB_SIZE_OFFSET) | (win->target_id << AMB_ATTR_OFFSET); base = win->base_addr << AMB_BASE_OFFSET; @@ -91,8 +96,8 @@ static void dump_amb_adec(void) uint32_t size, size_count; /* Dump all AMB windows */ - printf("bank attribute base size\n"); - printf("--------------------------------------------\n"); + tf_printf("bank attribute base size\n"); + tf_printf("--------------------------------------------\n"); for (win_id = 0; win_id < AMB_MAX_WIN_ID; win_id++) { ctrl = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); if (ctrl & WIN_ENABLE_BIT) { @@ -100,11 +105,10 @@ static void dump_amb_adec(void) attr = (ctrl >> AMB_ATTR_OFFSET) & AMB_ATTR_MASK; size_count = (ctrl >> AMB_SIZE_OFFSET) & AMB_SIZE_MASK; size = (size_count + 1) * AMB_WIN_ALIGNMENT_64K; - printf("amb 0x%04x 0x%08x 0x%08x\n", attr, base, size); + tf_printf("amb 0x%04x 0x%08x 0x%08x\n", + attr, base, size); } } - - return; } #endif diff --git a/drivers/marvell/ap810_aro.c b/drivers/marvell/ap810_aro.c index 2150c608..451a128c 100644 --- a/drivers/marvell/ap810_aro.c +++ b/drivers/marvell/ap810_aro.c @@ -8,7 +8,7 @@ #include <ap810_setup.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define ARO_REG_BASE_ADDR(ap) (MVEBU_DFX_SR_BASE(ap) + (0xD00)) #define ARO_CLUSTER_REG0_ADDR(cluster, ap) (ARO_REG_BASE_ADDR(ap) + 0x48 + ((cluster) * 0x8)) diff --git a/drivers/marvell/aro.c b/drivers/marvell/aro.c index 31777afe..9a20568a 100644 --- a/drivers/marvell/aro.c +++ b/drivers/marvell/aro.c @@ -4,13 +4,14 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <aro.h> #include <debug.h> #include <delay_timer.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #define CPU_ARO_CTRL_BASE MVEBU_REGS_BASE + (0x6F8D00) #define SAR_REG_ADDR MVEBU_REGS_BASE + 0x6f4400 diff --git a/drivers/marvell/cache_llc.c b/drivers/marvell/cache_llc.c index b2ce5bfa..e13e6ce2 100644 --- a/drivers/marvell/cache_llc.c +++ b/drivers/marvell/cache_llc.c @@ -1,23 +1,30 @@ /* - * Copyright (C) 2015 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* LLC driver is the Last Level Cache (L3C) driver + * for Marvell SoCs in AP806, AP807, and AP810 + */ + +#include <arch_helpers.h> #include <assert.h> #include <cache_llc.h> #include <ccu.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define CCU_HTC_CR(ap_index) (MVEBU_CCU_BASE(ap_index) + 0x200) #define CCU_SET_POC_OFFSET 5 +extern void ca72_l2_enable_unique_clean(void); + void llc_cache_sync(int ap_index) { - mmio_write_32(LLC_CACHE_SYNC(ap_index), 0); - /* Atumic write no need to wait */ + mmio_write_32(LLC_SYNC(ap_index), 0); + /* Atomic write, no need to wait */ } void llc_flush_all(int ap_index) @@ -42,23 +49,23 @@ void llc_disable(int ap_index) { llc_flush_all(ap_index); mmio_write_32(LLC_CTRL(ap_index), 0); - __asm__ volatile("dsb st"); + dsbishst(); } void llc_enable(int ap_index, int excl_mode) { uint32_t val; - __asm__ volatile("dsb sy"); + dsbsy(); llc_inv_all(ap_index); - __asm__ volatile("dsb sy"); + dsbsy(); val = LLC_CTRL_EN; if (excl_mode) val |= LLC_EXCLUSIVE_EN; mmio_write_32(LLC_CTRL(ap_index), val); - __asm__ volatile("dsb sy"); + dsbsy(); } int llc_is_exclusive(int ap_index) @@ -67,19 +74,11 @@ int llc_is_exclusive(int ap_index) reg = mmio_read_32(LLC_CTRL(ap_index)); - if ((reg & (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) == (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) + if ((reg & (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) == + (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) return 1; - return 0; -} -void llc_save(int ap_index) -{ - /* TBD */ -} - -void llc_resume(int ap_index) -{ - /* TBD */ + return 0; } void llc_runtime_enable(int ap_index) @@ -93,15 +92,12 @@ void llc_runtime_enable(int ap_index) INFO("Enabling LLC\n"); /* - * Enable L2 UniqueClean evictions + * Enable L2 UniqueClean evictions with data * Note: this configuration assumes that LLC is configured * in exclusive mode. * Later on in the code this assumption will be validated */ - __asm__ volatile ("mrs %0, s3_1_c15_c0_0" : "=r" (reg)); - reg |= (1 << 14); - __asm__ volatile ("msr s3_1_c15_c0_0, %0" : : "r" (reg)); - + ca72_l2_enable_unique_clean(); llc_enable(ap_index, 1); /* Set point of coherency to DDR. diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c index e71975a7..13246586 100644 --- a/drivers/marvell/ccu.c +++ b/drivers/marvell/ccu.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ +#include <armada_common.h> #include <ccu.h> #include <debug.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -38,24 +39,26 @@ static void dump_ccu(int ap_index) uint64_t start, end; /* Dump all AP windows */ - printf("\tbank target start end\n"); - printf("\t----------------------------------------------------\n"); + tf_printf("\tbank target start end\n"); + tf_printf("\t----------------------------------------------------\n"); for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); if (win_cr & WIN_ENABLE_BIT) { - target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & CCU_TARGET_ID_MASK; - alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); - ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, win_id)); + target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & + CCU_TARGET_ID_MASK; + alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, + win_id)); + ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, + win_id)); start = ((uint64_t)alr << ADDRESS_SHIFT); end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); - printf("\tccu %02x 0x%016llx 0x%016llx\n", target_id, start, end); + tf_printf("\tccu %02x 0x%016llx 0x%016llx\n", + target_id, start, end); } } win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; - printf("\tccu GCR %d - all other transactions\n", target_id); - - return; + tf_printf("\tccu GCR %d - all other transactions\n", target_id); } #endif @@ -64,13 +67,15 @@ void ccu_win_check(struct addr_map_win *win) /* check if address is aligned to 1M */ if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); - NOTICE("%s: Align up the base address to 0x%llx\n", __func__, win->base_addr); + NOTICE("%s: Align up the base address to 0x%llx\n", + __func__, win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); - NOTICE("%s: Aligning size to 0x%llx\n", __func__, win->win_size); + NOTICE("%s: Aligning size to 0x%llx\n", + __func__, win->win_size); } } @@ -93,7 +98,8 @@ void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); ccu_win_reg = WIN_ENABLE_BIT; - ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; + ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) + << CCU_TARGET_ID_OFFSET; mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); } @@ -142,6 +148,7 @@ void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) for (int i = 0; i < size; i++) { uint64_t base; uint32_t target; + win_id = MVEBU_CCU_MAX_WINS - 1 - i; target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); @@ -152,7 +159,8 @@ void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) base <<= ADDRESS_SHIFT; if ((win->target_id != target) || (win->base_addr != base)) { - ERROR("%s: Trying to remove bad window-%d!\n", __func__, win_id); + ERROR("%s: Trying to remove bad window-%d!\n", + __func__, win_id); continue; } ccu_disable_win(ap_index, win_id); @@ -175,7 +183,8 @@ static uint32_t ccu_dram_target_get(int ap_index) /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. * All the rest of detected APs will use window at index 1. - * The AP0 DRAM window is moved from index 2 to 1 during init_ccu() execution. + * The AP0 DRAM window is moved from index 2 to 1 during + * init_ccu() execution. */ const uint32_t win_id = (ap_index == 0) ? 2 : 1; uint32_t target; @@ -191,7 +200,8 @@ void ccu_dram_target_set(int ap_index, uint32_t target) { /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. * All the rest of detected APs will use window at index 1. - * The AP0 DRAM window is moved from index 2 to 1 during init_ccu() execution. + * The AP0 DRAM window is moved from index 2 to 1 + * during init_ccu() execution. */ const uint32_t win_id = (ap_index == 0) ? 2 : 1; uint32_t dram_cr; @@ -212,24 +222,25 @@ void ccu_dram_win_config(int ap_index, struct addr_map_win *win) */ const uint32_t win_id = (ap_index == 0) ? 2 : 1; #else /* end of BLE */ - /* At the ccu_init() execution stage, DRAM windows of all APs are arranged at index 1. - * The AP0 still has the old window BootROM DRAM at index 2, so the window-1 can be safely - * disabled without breaking the DRAM access. + /* At the ccu_init() execution stage, DRAM windows of all APs + * are arranged at index 1. + * The AP0 still has the old window BootROM DRAM at index 2, so + * the window-1 can be safely disabled without breaking the DRAM access. */ const uint32_t win_id = 1; #endif ccu_disable_win(ap_index, win_id); /* enable write secure (and clear read secure) */ - mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), CCU_WIN_ENA_WRITE_SECURE); + mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), + CCU_WIN_ENA_WRITE_SECURE); ccu_win_check(win); ccu_enable_win(ap_index, win, win_id); - - return; } /* Save content of CCU window + GCR */ -static void ccu_save_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void ccu_save_win_range(int ap_id, int win_first, + int win_last, uint32_t *buffer) { int win_id, idx; /* Save CCU */ @@ -243,7 +254,8 @@ static void ccu_save_win_range(int ap_id, int win_first, int win_last, uint32_t } /* Restore content of CCU window + GCR */ -static void ccu_restore_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void ccu_restore_win_range(int ap_id, int win_first, + int win_last, uint32_t *buffer) { int win_id, idx; /* Restore CCU */ @@ -288,25 +300,27 @@ int init_ccu(int ap_index) if (win_count <= 0) { INFO("No windows configurations found\n"); } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { - ERROR("CCU memory map array greater than max available windows, set win_count to max %d\n", + ERROR("CCU mem map array > than max available windows (%d)\n", MVEBU_CCU_MAX_WINS); win_count = MVEBU_CCU_MAX_WINS; } - /* Need to set GCR to DRAM before all CCU windows are disabled for securing the normal access - * to DRAM location, which the ATF is running from. Once all CCU windows are set, which have to - * include the dedicated DRAM window as well, the GCR can be switched to the target defined - * by the platform configuration. + /* Need to set GCR to DRAM before all CCU windows are disabled for + * securing the normal access to DRAM location, which the ATF is running + * from. Once all CCU windows are set, which have to include the + * dedicated DRAM window as well, the GCR can be switched to the target + * defined by the platform configuration. */ dram_target = ccu_dram_target_get(ap_index); win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); /* If the DRAM window was already configured at the BLE stage, - * only the window target considered valid, the address range should be updated - * according to the platform configuration. + * only the window target considered valid, the address range should be + * updated according to the platform configuration. */ - for (dram_win = win, array_id = 0; array_id < win_count; array_id++, dram_win++) { + for (dram_win = win, array_id = 0; array_id < win_count; + array_id++, dram_win++) { if (IS_DRAM_TARGET(dram_win->target_id)) { dram_win->target_id = dram_target; break; @@ -320,14 +334,16 @@ int init_ccu(int ap_index) for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { ccu_disable_win(ap_index, win_id); /* enable write secure (and clear read secure) */ - mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), CCU_WIN_ENA_WRITE_SECURE); + mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), + CCU_WIN_ENA_WRITE_SECURE); } /* win_id is the index of the current ccu window * array_id is the index of the current memory map window entry */ for (win_id = win_start, array_id = 0; - ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); win_id++) { + ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); + win_id++) { ccu_win_check(win); ccu_enable_win(ap_index, win, win_id); win++; @@ -335,7 +351,8 @@ int init_ccu(int ap_index) } /* Get & set the default target according to board topology */ - win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; + win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) + << CCU_GCR_TARGET_OFFSET; mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); #ifdef DEBUG_ADDR_MAP diff --git a/drivers/marvell/comphy.h b/drivers/marvell/comphy.h index 9ae98513..788b1b60 100644 --- a/drivers/marvell/comphy.h +++ b/drivers/marvell/comphy.h @@ -1,100 +1,132 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +/* Driver for COMPHY unit that is part or Marvell A8K SoCs */ + #ifndef _COMPHY_H_ #define _COMPHY_H_ /* COMPHY registers */ #define COMMON_PHY_CFG1_REG 0x0 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 -#define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) +#define COMMON_PHY_CFG1_PWR_UP_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 -#define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ + (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 -#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 -#define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) +#define COMMON_PHY_CFG1_CORE_RSTN_MASK \ + (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) #define COMMON_PHY_PHY_MODE_OFFSET 15 -#define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET) +#define COMMON_PHY_PHY_MODE_MASK \ + (0x1 << COMMON_PHY_PHY_MODE_OFFSET) -#define COMMON_SELECTOR_PHY_OFFSET 0x140 -#define COMMON_SELECTOR_PIPE_OFFSET 0x144 +#define COMMON_SELECTOR_PHY_OFFSET 0x140 +#define COMMON_SELECTOR_PIPE_OFFSET 0x144 -#define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1 0x148 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) #define DFX_DEV_GEN_CTRL12 0x80 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 -#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) +#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ + (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) /* HPIPE register */ #define HPIPE_PWR_PLL_REG 0x4 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 -#define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) +#define HPIPE_PWR_PLL_REF_FREQ_MASK \ + (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 -#define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) +#define HPIPE_PWR_PLL_PHY_MODE_MASK \ + (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) #define HPIPE_DFE_REG0 0x01C #define HPIPE_DFE_RES_FORCE_OFFSET 15 -#define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) +#define HPIPE_DFE_RES_FORCE_MASK \ + (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) #define HPIPE_G2_SET_1_REG 0x040 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 -#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 -#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) #define HPIPE_G3_SETTINGS_1_REG 0x048 #define HPIPE_G3_RX_SELMUPI_OFFSET 0 -#define HPIPE_G3_RX_SELMUPI_MASK (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) #define HPIPE_G3_RX_SELMUPF_OFFSET 3 -#define HPIPE_G3_RX_SELMUPF_MASK (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) #define HPIPE_G3_SETTING_BIT_OFFSET 13 -#define HPIPE_G3_SETTING_BIT_MASK (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) +#define HPIPE_G3_SETTING_BIT_MASK \ + (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) #define HPIPE_INTERFACE_REG 0x94 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 -#define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_GEN_MAX_MASK \ + (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 -#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_MASK \ + (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 -#define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) +#define HPIPE_INTERFACE_LINK_TRAIN_MASK \ + (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) #define HPIPE_VDD_CAL_CTRL_REG 0x114 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 -#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) +#define HPIPE_EXT_SELLV_RXSAMPL_MASK \ + (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) -#define HPIPE_PCIE_REG0 0x120 +#define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 -#define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) +#define HPIPE_PCIE_IDLE_SYNC_MASK \ + (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) #define HPIPE_PCIE_SEL_BITS_OFFSET 13 -#define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) +#define HPIPE_PCIE_SEL_BITS_MASK \ + (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) #define HPIPE_LANE_ALIGN_REG 0x124 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 -#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) +#define HPIPE_LANE_ALIGN_OFF_MASK \ + (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 -#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_CLK100M_125M_MASK \ + (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) #define HPIPE_MISC_ICP_FORCE_OFFSET 5 -#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) +#define HPIPE_MISC_ICP_FORCE_MASK \ + (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 -#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) +#define HPIPE_MISC_TXDCLK_2X_MASK \ + (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 -#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) +#define HPIPE_MISC_CLK500_EN_MASK \ + (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 -#define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) +#define HPIPE_MISC_REFCLK_SEL_MASK \ + (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_SMAPLER_OFFSET 12 @@ -102,76 +134,101 @@ #define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) #define HPIPE_FRAME_DET_CONTROL_REG 0x220 #define HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET 12 -#define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK (0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET) +#define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK \ + (0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET) #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 -#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ + (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 -#define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 -#define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 -#define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G0_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) +#define HPIPE_TRX_TRAIN_TIMER_MASK \ + (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 -#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 -#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 -#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 -#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) #define HPIPE_TX_TRAIN_REG 0x31C #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 -#define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) +#define HPIPE_TX_TRAIN_CHK_INIT_MASK \ + (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 -#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ + (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 -#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 -#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 -#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ + (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 -#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_MASK \ + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 -#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_MASK \ + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) #define HPIPE_G2_SETTINGS_4_REG 0x44C #define HPIPE_G2_DFE_RES_OFFSET 8 #define HPIPE_G2_DFE_RES_MASK (0x3 << HPIPE_G2_DFE_RES_OFFSET) #define HPIPE_G3_SETTING_3_REG 0x450 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G3_FFE_CAP_SEL_MASK (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) +#define HPIPE_G3_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G3_FFE_RES_SEL_MASK (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) +#define HPIPE_G3_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G3_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) #define HPIPE_G3_SETTING_4_REG 0x454 #define HPIPE_G3_DFE_RES_OFFSET 8 @@ -179,23 +236,28 @@ #define HPIPE_DFE_CONTROL_REG 0x470 #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 -#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ + (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 -#define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) +#define HPIPE_DFE_CTRL_28_PIPE4_MASK \ + (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) #define HPIPE_G3_SETTING_5_REG 0x548 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 -#define HPIPE_G3_SETTING_5_G3_ICP_MASK (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) +#define HPIPE_G3_SETTING_5_G3_ICP_MASK \ + (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) #define HPIPE_LANE_STATUS1_REG 0x60C #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 -#define HPIPE_LANE_STATUS1_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) +#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ + (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) -#define HPIPE_LANE_CFG4_REG 0x620 +#define HPIPE_LANE_CFG4_REG 0x620 #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 -#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C #define HPIPE_CFG_EQ_FS_OFFSET 0 @@ -203,157 +265,209 @@ #define HPIPE_CFG_EQ_LF_OFFSET 6 #define HPIPE_CFG_EQ_LF_MASK (0x3f << HPIPE_CFG_EQ_LF_OFFSET) #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 -#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) +#define HPIPE_CFG_PHY_RC_EP_MASK \ + (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 -#define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) +#define HPIPE_CFG_UPDATE_POLARITY_MASK \ + (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) #define HPIPE_LANE_EQ_CFG2_REG 0x6a4 #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14 -#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) +#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \ + (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) #define HPIPE_LANE_PRESET_CFG0_REG 0x6a8 #define HPIPE_CFG_CURSOR_PRESET0_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET0_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET0_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET) #define HPIPE_CFG_CURSOR_PRESET1_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET1_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET1_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET) #define HPIPE_LANE_PRESET_CFG1_REG 0x6ac #define HPIPE_CFG_CURSOR_PRESET2_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET2_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET2_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET) #define HPIPE_CFG_CURSOR_PRESET3_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET3_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET3_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET) #define HPIPE_LANE_PRESET_CFG2_REG 0x6b0 #define HPIPE_CFG_CURSOR_PRESET4_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET4_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET4_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET) #define HPIPE_CFG_CURSOR_PRESET5_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET5_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET5_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET) #define HPIPE_LANE_PRESET_CFG3_REG 0x6b4 #define HPIPE_CFG_CURSOR_PRESET6_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET6_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET6_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET) #define HPIPE_CFG_CURSOR_PRESET7_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET7_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET7_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET) #define HPIPE_LANE_PRESET_CFG4_REG 0x6b8 #define HPIPE_CFG_CURSOR_PRESET8_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET8_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET8_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET) #define HPIPE_CFG_CURSOR_PRESET9_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET9_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET9_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET) #define HPIPE_LANE_PRESET_CFG5_REG 0x6bc #define HPIPE_CFG_CURSOR_PRESET10_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET10_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET10_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET) #define HPIPE_CFG_CURSOR_PRESET11_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET11_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET11_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET) #define HPIPE_LANE_PRESET_CFG6_REG 0x6c0 #define HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET0_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET0_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET) #define HPIPE_LANE_PRESET_CFG7_REG 0x6c4 #define HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET1_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET1_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET) #define HPIPE_LANE_PRESET_CFG8_REG 0x6c8 #define HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET2_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET2_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET) #define HPIPE_LANE_PRESET_CFG9_REG 0x6cc #define HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET3_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET3_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET) #define HPIPE_LANE_PRESET_CFG10_REG 0x6d0 #define HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET4_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET4_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET) #define HPIPE_LANE_PRESET_CFG11_REG 0x6d4 #define HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET5_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET5_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET) #define HPIPE_LANE_PRESET_CFG12_REG 0x6d8 #define HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET6_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET6_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET) #define HPIPE_LANE_PRESET_CFG13_REG 0x6dc #define HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET7_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET7_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET) #define HPIPE_LANE_PRESET_CFG14_REG 0x6e0 #define HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET8_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET8_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET) #define HPIPE_LANE_PRESET_CFG15_REG 0x6e4 #define HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET9_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET9_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET) #define HPIPE_LANE_PRESET_CFG16_REG 0x6e8 #define HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET10_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET10_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET) #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 -#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 -#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 -#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ + (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) #define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 -#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 -#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 -#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 -#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) -#define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_REG 0x70c #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ + (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ + (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ + (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) #define HPIPE_CLK_SRC_HI_REG 0x710 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 -#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 -#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 -#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 -#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) -#define HPIPE_GLOBAL_PM_CTRL 0x740 +#define HPIPE_GLOBAL_PM_CTRL 0x740 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 -#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ + (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) #endif /* _COMPHY_H_ */ diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h index df9a6e65..6aa088ab 100644 --- a/drivers/marvell/comphy/comphy-cp110.h +++ b/drivers/marvell/comphy/comphy-cp110.h @@ -5,6 +5,8 @@ * https://spdx.org/licenses */ +/* Marvell CP110 SoC COMPHY unit driver */ + #ifndef _PHY_COMPHY_CP110_H #define _PHY_COMPHY_CP110_H @@ -18,23 +20,30 @@ /* Comphy registers */ #define COMMON_PHY_CFG1_REG 0x0 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 -#define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) +#define COMMON_PHY_CFG1_PWR_UP_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 -#define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ + (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 13 -#define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) +#define COMMON_PHY_CFG1_CORE_RSTN_MASK \ + (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 14 -#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) #define COMMON_PHY_PHY_MODE_OFFSET 15 -#define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET) +#define COMMON_PHY_PHY_MODE_MASK \ + (0x1 << COMMON_PHY_PHY_MODE_OFFSET) #define COMMON_PHY_CFG6_REG 0x14 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 -#define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) +#define COMMON_PHY_CFG6_IF_40_SEL_MASK \ + (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) #define COMMON_PHY_CFG6_REG 0x14 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 -#define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) +#define COMMON_PHY_CFG6_IF_40_SEL_MASK \ + (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) #define COMMON_SELECTOR_PHY_REG_OFFSET 0x140 #define COMMON_SELECTOR_PIPE_REG_OFFSET 0x144 @@ -62,65 +71,87 @@ #define COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK 0xFFFF #define COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK 0xFF #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 -#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 -#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) /* DFX register */ #define DFX_BASE (0x400000) #define DFX_DEV_GEN_CTRL12_REG (0x280) #define DFX_DEV_GEN_PCIE_CLK_SRC_MUX (0x3) #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 -#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) +#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ + (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) /* SerDes IP registers */ #define SD_EXTERNAL_CONFIG0_REG 0 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 -#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 -#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 -#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 -#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ + (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 -#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) #define SD_EXTERNAL_CONFIG1_REG 0x4 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 -#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 -#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) +#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 -#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) +#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 -#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) #define SD_EXTERNAL_CONFIG2_REG 0x8 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 -#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 -#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) #define SD_EXTERNAL_STATUS_REG 0xc #define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7 -#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) +#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \ + (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 -#define SD_EXTERNAL_STATUS0_PLL_TX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) +#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 -#define SD_EXTERNAL_STATUS0_PLL_RX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) +#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 -#define SD_EXTERNAL_STATUS0_RX_INIT_MASK (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) +#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) #define SD_EXTERNAL_STATAUS1_REG 0x1c #define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET 0 @@ -133,31 +164,40 @@ /* HPIPE registers */ #define HPIPE_PWR_PLL_REG 0x4 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 -#define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) +#define HPIPE_PWR_PLL_REF_FREQ_MASK \ + (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 -#define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) +#define HPIPE_PWR_PLL_PHY_MODE_MASK \ + (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) #define HPIPE_CAL_REG1_REG 0xc #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 -#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ + (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 -#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ + (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) -#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 #define HPIPE_SQUELCH_THRESH_IN_OFFSET 8 -#define HPIPE_SQUELCH_THRESH_IN_MASK (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) +#define HPIPE_SQUELCH_THRESH_IN_MASK \ + (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) #define HPIPE_SQUELCH_DETECTED_OFFSET 14 -#define HPIPE_SQUELCH_DETECTED_MASK (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET) +#define HPIPE_SQUELCH_DETECTED_MASK \ + (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET) #define HPIPE_DFE_REG0 0x1c #define HPIPE_DFE_RES_FORCE_OFFSET 15 -#define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) +#define HPIPE_DFE_RES_FORCE_MASK \ + (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) #define HPIPE_DFE_F3_F5_REG 0x28 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 -#define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) +#define HPIPE_DFE_F3_F5_DFE_EN_MASK \ + (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 -#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) +#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ + (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) #define HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG 0x30 #define HPIPE_ADAPTED_DFE_RES_OFFSET 13 @@ -165,37 +205,50 @@ #define HPIPE_G1_SET_0_REG 0x34 #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 -#define HPIPE_G1_SET_0_G1_TX_AMP_MASK (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ + (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ + (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) #define HPIPE_G1_SET_1_REG 0x38 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3 #define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 -#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 -#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) #define HPIPE_G2_SET_0_REG 0x3c #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 -#define HPIPE_G2_SET_0_G2_TX_AMP_MASK (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ + (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 -#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ + (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) #define HPIPE_G2_SET_1_REG 0x40 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 @@ -203,55 +256,76 @@ #define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3 #define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 -#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 -#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 -#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) #define HPIPE_G3_SET_0_REG 0x44 #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 -#define HPIPE_G3_SET_0_G3_TX_AMP_MASK (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ + (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 -#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ + (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 -#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ + (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 -#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) #define HPIPE_G3_SET_1_REG 0x48 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 -#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 -#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 -#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 -#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 -#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 -#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) +#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ + (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) #define HPIPE_PHY_TEST_CONTROL_REG 0x54 #define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4 -#define HPIPE_PHY_TEST_PATTERN_SEL_MASK (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) +#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \ + (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) #define HPIPE_PHY_TEST_RESET_OFFSET 14 -#define HPIPE_PHY_TEST_RESET_MASK (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) +#define HPIPE_PHY_TEST_RESET_MASK \ + (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) #define HPIPE_PHY_TEST_EN_OFFSET 15 -#define HPIPE_PHY_TEST_EN_MASK (0x1 << HPIPE_PHY_TEST_EN_OFFSET) +#define HPIPE_PHY_TEST_EN_MASK \ + (0x1 << HPIPE_PHY_TEST_EN_OFFSET) #define HPIPE_PHY_TEST_DATA_REG 0x6c #define HPIPE_PHY_TEST_DATA_OFFSET 0 -#define HPIPE_PHY_TEST_DATA_MASK (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) +#define HPIPE_PHY_TEST_DATA_MASK \ + (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) #define HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG 0x80 @@ -263,25 +337,33 @@ #define HPIPE_LOOPBACK_REG 0x8c #define HPIPE_LOOPBACK_SEL_OFFSET 1 -#define HPIPE_LOOPBACK_SEL_MASK (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) +#define HPIPE_LOOPBACK_SEL_MASK \ + (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) #define HPIPE_CDR_LOCK_OFFSET 7 -#define HPIPE_CDR_LOCK_MASK (0x1 << HPIPE_CDR_LOCK_OFFSET) +#define HPIPE_CDR_LOCK_MASK \ + (0x1 << HPIPE_CDR_LOCK_OFFSET) #define HPIPE_CDR_LOCK_DET_EN_OFFSET 8 -#define HPIPE_CDR_LOCK_DET_EN_MASK (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET) +#define HPIPE_CDR_LOCK_DET_EN_MASK \ + (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET) #define HPIPE_INTERFACE_REG 0x94 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 -#define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_GEN_MAX_MASK \ + (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 -#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_MASK \ + (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 -#define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) +#define HPIPE_INTERFACE_LINK_TRAIN_MASK \ + (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) #define HPIPE_G1_SET_2_REG 0xf4 #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) +#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ + (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET) +#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ + (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET) #define HPIPE_G2_SET_2_REG 0xf8 #define HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET 0 @@ -289,7 +371,8 @@ #define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET 4 #define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK (0x1 << HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET) #define HPIPE_G2_TX_SSC_AMP_OFFSET 9 -#define HPIPE_G2_TX_SSC_AMP_MASK (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET) +#define HPIPE_G2_TX_SSC_AMP_MASK \ + (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET) #define HPIPE_G3_SET_2_REG 0xfc #define HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET 0 @@ -301,57 +384,76 @@ #define HPIPE_VDD_CAL_0_REG 0x108 #define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 -#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) +#define HPIPE_CAL_VDD_CONT_MODE_MASK \ + (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) #define HPIPE_VDD_CAL_CTRL_REG 0x114 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 -#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) +#define HPIPE_EXT_SELLV_RXSAMPL_MASK \ + (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) -#define HPIPE_PCIE_REG0 0x120 +#define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 -#define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) +#define HPIPE_PCIE_IDLE_SYNC_MASK \ + (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) #define HPIPE_PCIE_SEL_BITS_OFFSET 13 -#define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) +#define HPIPE_PCIE_SEL_BITS_MASK \ + (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) #define HPIPE_LANE_ALIGN_REG 0x124 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 -#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) +#define HPIPE_LANE_ALIGN_OFF_MASK \ + (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 -#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_CLK100M_125M_MASK \ + (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) #define HPIPE_MISC_ICP_FORCE_OFFSET 5 -#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) +#define HPIPE_MISC_ICP_FORCE_MASK \ + (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 -#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) +#define HPIPE_MISC_TXDCLK_2X_MASK \ + (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 -#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) +#define HPIPE_MISC_CLK500_EN_MASK \ + (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 -#define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) +#define HPIPE_MISC_REFCLK_SEL_MASK \ + (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) #define HPIPE_RX_CONTROL_1_REG 0x140 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 -#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ + (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 -#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) +#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ + (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) #define HPIPE_PWR_CTR_REG 0x148 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 -#define HPIPE_PWR_CTR_RST_DFE_MASK (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) +#define HPIPE_PWR_CTR_RST_DFE_MASK \ + (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 -#define HPIPE_PWR_CTR_SFT_RST_MASK (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) +#define HPIPE_PWR_CTR_SFT_RST_MASK \ + (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) #define HPIPE_SPD_DIV_FORCE_REG 0x154 #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 -#define HPIPE_TXDIGCK_DIV_FORCE_MASK (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) +#define HPIPE_TXDIGCK_DIV_FORCE_MASK \ + (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ + (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ + (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ + (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ + (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) /* HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIBRATION_CTRL_REG */ #define HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG 0x168 @@ -362,39 +464,53 @@ #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 -#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ + (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) #define HPIPE_SMAPLER_OFFSET 12 -#define HPIPE_SMAPLER_MASK (0x1 << HPIPE_SMAPLER_OFFSET) +#define HPIPE_SMAPLER_MASK \ + (0x1 << HPIPE_SMAPLER_OFFSET) #define HPIPE_TX_REG1_REG 0x174 #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 -#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ + (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 -#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_MASK \ + (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 -#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 -#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 -#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ + (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 -#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 -#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ + (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 -#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ + (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) #define HPIPE_PHASE_CONTROL_REG 0x188 #define HPIPE_OS_PH_OFFSET_OFFSET 0 -#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) +#define HPIPE_OS_PH_OFFSET_MASK \ + (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 -#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_MASK \ + (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) #define HPIPE_OS_PH_VALID_OFFSET 8 -#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALID_OFFSET) +#define HPIPE_OS_PH_VALID_MASK \ + (0x1 << HPIPE_OS_PH_VALID_OFFSET) #define HPIPE_DATA_PHASE_OFF_CTRL_REG 0x1A0 #define HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET 9 @@ -408,23 +524,29 @@ #define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8 #define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0 -#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) +#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) #define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4 -#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) +#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) #define HPIPE_SQ_DEGLITCH_EN_OFFSET 8 -#define HPIPE_SQ_DEGLITCH_EN_MASK (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) +#define HPIPE_SQ_DEGLITCH_EN_MASK \ + (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 -#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) +#define HPIPE_TRAIN_PAT_NUM_MASK \ + (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 -#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ + (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) #define HPIPE_DME_REG 0x228 #define HPIPE_DME_ETHERNET_MODE_OFFSET 7 -#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) +#define HPIPE_DME_ETHERNET_MODE_MASK \ + (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) #define HPIPE_TRX_TRAIN_CTRL_0_REG 0x22c #define HPIPE_TRX_TX_F0T_EO_BASED_OFFSET 14 @@ -442,31 +564,41 @@ #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 -#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ + (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 -#define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 -#define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 -#define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G0_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) +#define HPIPE_TRX_TRAIN_TIMER_MASK \ + (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 #define HPIPE_RX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_RX_TRAIN_TIMER_MASK (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) +#define HPIPE_RX_TRAIN_TIMER_MASK \ + (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 -#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 -#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 -#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 -#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) #define HPIPE_INTERRUPT_1_REGISTER 0x2AC #define HPIPE_TRX_TRAIN_FAILED_OFFSET 6 @@ -482,69 +614,94 @@ #define HPIPE_TX_TRAIN_REG 0x31C #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 -#define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) +#define HPIPE_TX_TRAIN_CHK_INIT_MASK \ + (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 -#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ + (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 -#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 -#define HPIPE_TX_TRAIN_PAT_SEL_MASK (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_MASK \ + (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) -#define HPIPE_SAVED_DFE_VALUES_REG 0x328 -#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 -#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) +#define HPIPE_SAVED_DFE_VALUES_REG 0x328 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \ + (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 -#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 -#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 -#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ + (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 -#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_MASK \ + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 -#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_MASK \ + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) #define HPIPE_G1_SETTINGS_3_REG 0x440 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 -#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ + (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) #define HPIPE_G1_SETTINGS_4_REG 0x444 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 -#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) +#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ + (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) #define HPIPE_G2_SETTINGS_4_REG 0x44c #define HPIPE_G2_DFE_RES_OFFSET 8 -#define HPIPE_G2_DFE_RES_MASK (0x3 << HPIPE_G2_DFE_RES_OFFSET) +#define HPIPE_G2_DFE_RES_MASK \ + (0x3 << HPIPE_G2_DFE_RES_OFFSET) #define HPIPE_G3_SETTING_3_REG 0x450 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G3_FFE_CAP_SEL_MASK (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) +#define HPIPE_G3_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G3_FFE_RES_SEL_MASK (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) +#define HPIPE_G3_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G3_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) #define HPIPE_G3_SETTING_4_REG 0x454 #define HPIPE_G3_DFE_RES_OFFSET 8 @@ -552,98 +709,128 @@ #define HPIPE_TX_PRESET_INDEX_REG 0x468 #define HPIPE_TX_PRESET_INDEX_OFFSET 0 -#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) +#define HPIPE_TX_PRESET_INDEX_MASK \ + (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) #define HPIPE_DFE_CONTROL_REG 0x470 #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 -#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ + (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 -#define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) +#define HPIPE_DFE_CTRL_28_PIPE4_MASK \ + (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) #define HPIPE_G1_SETTING_5_REG 0x538 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 -#define HPIPE_G1_SETTING_5_G1_ICP_MASK (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) +#define HPIPE_G1_SETTING_5_G1_ICP_MASK \ + (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) #define HPIPE_G3_SETTING_5_REG 0x548 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 -#define HPIPE_G3_SETTING_5_G3_ICP_MASK (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) +#define HPIPE_G3_SETTING_5_G3_ICP_MASK \ + (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) #define HPIPE_LANE_CONFIG0_REG 0x600 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 -#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) +#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ + (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) #define HPIPE_LANE_STATUS1_REG 0x60C #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 -#define HPIPE_LANE_STATUS1_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) +#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ + (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) -#define HPIPE_LANE_CFG4_REG 0x620 +#define HPIPE_LANE_CFG4_REG 0x620 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 -#define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ + (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 -#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 -#define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) +#define HPIPE_LANE_CFG4_DFE_OVER_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 -#define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ + (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 -#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 -#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 -#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ + (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 -#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) +#define HPIPE_CFG_PHY_RC_EP_MASK \ + (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 -#define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) +#define HPIPE_CFG_UPDATE_POLARITY_MASK \ + (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) #define HPIPE_LANE_EQ_CFG2_REG 0x6a4 #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14 -#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) +#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \ + (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) #define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 -#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 -#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 -#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 -#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) #define HPIPE_TST_MODE_CTRL_REG 0x708 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 -#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) +#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ + (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) -#define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_REG 0x70c #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ + (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ + (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ + (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) #define HPIPE_CLK_SRC_HI_REG 0x710 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 -#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 -#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 -#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 -#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) -#define HPIPE_GLOBAL_MISC_CTRL 0x718 -#define HPIPE_GLOBAL_PM_CTRL 0x740 +#define HPIPE_GLOBAL_MISC_CTRL 0x718 +#define HPIPE_GLOBAL_PM_CTRL 0x740 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 -#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ + (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) /* General defines */ #define PLL_LOCK_TIMEOUT 15000 diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index 9686d00c..6e7be7f3 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -5,12 +5,14 @@ * https://spdx.org/licenses */ +/* Marvell CP110 SoC COMPHY unit driver */ + #include <ap_setup.h> #include <debug.h> #include <delay_timer.h> #include <errno.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <spinlock.h> #include "mvebu.h" #include "comphy-cp110.h" @@ -41,35 +43,45 @@ #define COMPHY_INVERT_OFFSET 0 #define COMPHY_INVERT_LEN 2 -#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, COMPHY_INVERT_LEN) +#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \ + COMPHY_INVERT_LEN) #define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN) #define COMPHY_SPEED_LEN 6 -#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, COMPHY_SPEED_LEN) +#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \ + COMPHY_SPEED_LEN) #define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN) #define COMPHY_UNIT_ID_LEN 4 -#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, COMPHY_UNIT_ID_LEN) +#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \ + COMPHY_UNIT_ID_LEN) #define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN) #define COMPHY_MODE_LEN 5 #define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN) #define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN) #define COMPHY_CLK_SRC_LEN 1 -#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, COMPHY_CLK_SRC_LEN) +#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \ + COMPHY_CLK_SRC_LEN) #define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN) #define COMPHY_PCI_WIDTH_LEN 3 -#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, COMPHY_PCI_WIDTH_LEN) +#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \ + COMPHY_PCI_WIDTH_LEN) #define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset)) /* Macro which extracts mode from lane description */ -#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> COMPHY_MODE_OFFSET) +#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \ + COMPHY_MODE_OFFSET) /* Macro which extracts unit index from lane description */ -#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> COMPHY_UNIT_ID_OFFSET) +#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \ + COMPHY_UNIT_ID_OFFSET) /* Macro which extracts speed from lane description */ -#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> COMPHY_SPEED_OFFSET) +#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \ + COMPHY_SPEED_OFFSET) /* Macro which extracts clock source indication from lane description */ -#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> COMPHY_CLK_SRC_OFFSET) +#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \ + COMPHY_CLK_SRC_OFFSET) /* Macro which extracts pcie width indication from lane description */ -#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> COMPHY_PCI_WIDTH_OFFSET) +#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \ + COMPHY_PCI_WIDTH_OFFSET) #define COMPHY_SATA_MODE 0x1 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ @@ -101,7 +113,7 @@ #define COMPHY_PIPE_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + 0x120000) -/* System controler registers */ +/* System controller registers */ #define PCIE_MAC_RESET_MASK_PORT0 BIT(13) #define PCIE_MAC_RESET_MASK_PORT1 BIT(11) #define PCIE_MAC_RESET_MASK_PORT2 BIT(12) @@ -110,9 +122,11 @@ /* DFX register spaces */ #define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET (0) -#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK (0x1 << SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET) +#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK (0x1 << \ + SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET) #define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET (1) -#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK (0x1 << SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET) +#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK (0x1 << \ + SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET) #define SAR_STATUS_0_REG 200 #define DFX_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + DFX_BASE) @@ -170,8 +184,11 @@ static void mvebu_cp110_get_ap_and_cp_nr(uint8_t *ap_nr, uint8_t *cp_nr, uint64_ (unsigned long)MVEBU_CP_OFFSET); } -static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, - uint32_t mask, uint32_t usec_timout, enum reg_width_type type) +static inline uint32_t polling_with_timeout(uintptr_t addr, + uint32_t val, + uint32_t mask, + uint32_t usec_timeout, + enum reg_width_type type) { uint32_t data; @@ -181,9 +198,9 @@ static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, data = mmio_read_16(addr) & mask; else data = mmio_read_32(addr) & mask; - } while (data != val && --usec_timout > 0); + } while (data != val && --usec_timeout > 0); - if (usec_timout == 0) + if (usec_timeout == 0) return data; return 0; @@ -191,7 +208,7 @@ static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) { - debug("<atf>: Write to address = %#010lx, data = %#010x (mask = %#010x) - ", + debug("<atf>: WR to addr = %#010lx, data = %#010x (mask = %#010x) - ", addr, data, mask); debug("old value = %#010x ==> ", mmio_read_32(addr)); mmio_clrsetbits_32(addr, mask, data); @@ -200,10 +217,12 @@ static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) } /* Clear PIPE selector - avoid collision with previous configuration */ -static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base, uint8_t comphy_index) +static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base, + uint8_t comphy_index) { uint32_t reg, mask, field; - uint32_t comphy_offset = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; + uint32_t comphy_offset = + COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET); @@ -211,15 +230,18 @@ static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base, uint8_t c if (field) { reg &= ~mask; - mmio_write_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET, reg); + mmio_write_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET, + reg); } } /* Clear PHY selector - avoid collision with previous configuration */ -static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base, uint8_t comphy_index) +static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base, + uint8_t comphy_index) { uint32_t reg, mask, field; - uint32_t comphy_offset = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; + uint32_t comphy_offset = + COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET); @@ -232,7 +254,8 @@ static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base, uint8_t co */ if (field) { reg &= ~mask; - mmio_write_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET, reg); + mmio_write_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET, + reg); } } @@ -241,7 +264,8 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, uint8_t comphy_index, uint32_t comphy_mode) { uint32_t reg, mask; - uint32_t comphy_offset = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; + uint32_t comphy_offset = + COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; int mode; /* If phy selector is used the pipe selector should be marked as @@ -270,7 +294,8 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, /* For comphy 0,1, and 2: * Network selector value is always 1. */ - reg |= COMMON_SELECTOR_COMPHY0_1_2_NETWORK << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY0_1_2_NETWORK << + comphy_offset; break; case(3): /* For comphy 3: @@ -278,28 +303,35 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, * 0x2 = SGMII/HS-SGMII Port1 */ if (mode == COMPHY_RXAUI_MODE) - reg |= COMMON_SELECTOR_COMPHY3_RXAUI << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY3_RXAUI << + comphy_offset; else - reg |= COMMON_SELECTOR_COMPHY3_SGMII << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY3_SGMII << + comphy_offset; break; case(4): /* For comphy 4: * 0x1 = SGMII/HS-SGMII Port1, XFI1/SFI1 * 0x2 = SGMII/HS-SGMII Port0: XFI0/SFI0, RXAUI_Lane0 * - * We want to check if SGMII1/HS_SGMII1 is the requested mode in order to - * determine which value should be set (all other modes use the same value) - * so we need to strip the mode, and check the ID because we might handle - * SGMII0/HS_SGMII0 too. + * We want to check if SGMII1/HS_SGMII1 is the + * requested mode in order to determine which value + * should be set (all other modes use the same value) + * so we need to strip the mode, and check the ID + * because we might handle SGMII0/HS_SGMII0 too. */ - /* TODO: need to diffrenciate between CP110 and CP115 as SFI1/XFI1 - * availalbe only for CP115. + /* TODO: need to distinguish between CP110 and CP115 + * as SFI1/XFI1 available only for CP115. */ - if ((mode == COMPHY_SGMII_MODE || mode == COMPHY_HS_SGMII_MODE || - mode == COMPHY_SFI_MODE) && COMPHY_GET_ID(comphy_mode) == 1) - reg |= COMMON_SELECTOR_COMPHY4_PORT1 << comphy_offset; + if ((mode == COMPHY_SGMII_MODE || + mode == COMPHY_HS_SGMII_MODE || + mode == COMPHY_SFI_MODE) && + COMPHY_GET_ID(comphy_mode) == 1) + reg |= COMMON_SELECTOR_COMPHY4_PORT1 << + comphy_offset; else - reg |= COMMON_SELECTOR_COMPHY4_ALL_OTHERS << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY4_ALL_OTHERS << + comphy_offset; break; case(5): /* For comphy 5: @@ -307,9 +339,11 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, * 0x2 = RXAUI Lane1 */ if (mode == COMPHY_RXAUI_MODE) - reg |= COMMON_SELECTOR_COMPHY5_RXAUI << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY5_RXAUI << + comphy_offset; else - reg |= COMMON_SELECTOR_COMPHY5_SGMII << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY5_SGMII << + comphy_offset; break; } } @@ -378,13 +412,15 @@ int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, uint8_t comphy_index) debug_enter(); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & SD_EXTERNAL_STATUS0_PLL_RX_MASK; mask = data; - data = polling_with_timeout(addr, data, mask, PLL_LOCK_TIMEOUT, REG_32BIT); + data = polling_with_timeout(addr, data, mask, + PLL_LOCK_TIMEOUT, REG_32BIT); if (data != 0) { if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) ERROR("RX PLL is not locked\n"); @@ -422,10 +458,13 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* configure phy selector for SATA */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, + comphy_index, comphy_mode); - hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); debug(" add hpipe 0x%lx, sd 0x%lx, comphy 0x%lx\n", @@ -444,7 +483,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* Set select data width 40Bit - SATA mode only */ reg_set(comphy_addr + COMMON_PHY_CFG6_REG, - 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, COMMON_PHY_CFG6_IF_40_SEL_MASK); + 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, + COMMON_PHY_CFG6_IF_40_SEL_MASK); /* release from hard reset in SD external */ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; @@ -460,7 +500,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* Start comphy Configuration */ /* Set reference clock to comes from group 1 - choose 25Mhz */ reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, HPIPE_MISC_REFCLK_SEL_MASK); + 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, + HPIPE_MISC_REFCLK_SEL_MASK); /* Reference frequency select set 1 (for SATA = 25Mhz) */ mask = HPIPE_PWR_PLL_REF_FREQ_MASK; data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; @@ -470,7 +511,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); /* Set max PHY generation setting - 6Gbps */ reg_set(hpipe_addr + HPIPE_INTERFACE_REG, - 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); + 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, + HPIPE_INTERFACE_GEN_MAX_MASK); /* Set select data width 40Bit (SEL_BITS[2:0]) */ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); @@ -671,14 +713,18 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* DFE reset sequence */ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, + HPIPE_PWR_CTR_RST_DFE_MASK); reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, + HPIPE_PWR_CTR_RST_DFE_MASK); /* SW reset for interrupt logic */ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, + HPIPE_PWR_CTR_SFT_RST_MASK); reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, + HPIPE_PWR_CTR_SFT_RST_MASK); debug_exit(); @@ -694,12 +740,15 @@ static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base, debug_enter(); - hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); /* configure phy selector for SGMII */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, + comphy_mode); /* Confiugre the lane */ debug("stage: RFU configurations - hard reset comphy\n"); @@ -795,7 +844,8 @@ static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base, debug("stage: Analog parameters from ETP(HW)\n"); reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, - 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); + 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, + HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); /* SERDES External Configuration */ @@ -883,12 +933,15 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, return -EINVAL; } - hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); /* configure phy selector for XFI/SFI */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, + comphy_mode); debug("stage: RFU configurations - hard reset comphy\n"); /* RFU configurations - hard reset comphy */ @@ -1181,9 +1234,11 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, /* check PLL rx & tx ready */ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | SD_EXTERNAL_STATUS0_PLL_TX_MASK; + data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | + SD_EXTERNAL_STATUS0_PLL_TX_MASK; mask = data; - data = polling_with_timeout(addr, data, mask, PLL_LOCK_TIMEOUT, REG_32BIT); + data = polling_with_timeout(addr, data, mask, + PLL_LOCK_TIMEOUT, REG_32BIT); if (data != 0) { if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) ERROR("RX PLL is not locked\n"); @@ -1240,7 +1295,7 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, spin_lock(&cp110_mac_reset_lock); reg = mmio_read_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) + - SYS_CTRL_UINIT_SOFT_RESET_REG); + SYS_CTRL_UINIT_SOFT_RESET_REG); switch (comphy_index) { case COMPHY_LANE0: reg |= PCIE_MAC_RESET_MASK_PORT0; @@ -1259,7 +1314,7 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, /* Configure PIPE selector for PCIE */ mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index, - comphy_mode); + comphy_mode); /* * Read SAR (Sample-At-Reset) configuration for the PCIe clock @@ -1388,7 +1443,7 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, mask |= HPIPE_MISC_CLK100M_125M_MASK; data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; } - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */ + /* Set PIN_TXDCLK_2X Clock Freq. Selection for outputs 500MHz clock */ mask |= HPIPE_MISC_TXDCLK_2X_MASK; data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; /* Enable 500MHz Clock */ @@ -1634,9 +1689,10 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, /* Release from PIPE soft reset * For PCIe by4 or by2: * release from soft reset all lanes - can't use - *read modify write + * read modify write */ - reg_set(HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), 0) + + reg_set(HPIPE_ADDR( + COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), 0) + HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); } else { start_lane = comphy_index; @@ -1677,7 +1733,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, debug("stage: Check PLL\n"); /* Read lane status */ for (i = start_lane; i < end_lane; i++) { - addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), i) + + addr = HPIPE_ADDR( + COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), i) + HPIPE_LANE_STATUS1_REG; data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; mask = data; @@ -1706,10 +1763,12 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); /* configure phy selector for RXAUI */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, + comphy_mode); /* RFU configurations - hard reset comphy */ mask = COMMON_PHY_CFG1_PWR_UP_MASK; @@ -1790,8 +1849,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); - /* Set analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); + /* Set analog parameters from ETP(HW) */ + debug("stage: Analog parameters from ETP(HW)\n"); /* SERDES External Configuration 2 */ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, @@ -1843,7 +1902,7 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, if (data != 0) { debug("Read from reg = %lx - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - ERROR("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", + ERROR("SD_EXTERNAL_STATUS0_PLL_RX is %d, -\"-_PLL_TX is %d\n", (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); ret = -ETIMEDOUT; @@ -1890,7 +1949,7 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base, /* Configure PIPE selector for USB3 */ mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index, - comphy_mode); + comphy_mode); hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); @@ -2265,7 +2324,8 @@ static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base, uint8_t comphy_index) { uint32_t mask, data; - uintptr_t comphy_addr = comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); + uintptr_t comphy_addr = comphy_addr = + COMPHY_ADDR(comphy_base, comphy_index); debug_enter(); debug("stage: RFU configurations - hard reset comphy\n"); @@ -2292,7 +2352,8 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uintptr_t sd_ip_addr; uint32_t mask, data; - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); switch (mode) { case (COMPHY_SGMII_MODE): @@ -2306,7 +2367,7 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); break; default: - ERROR("comphy%d: COMPHY_COMMAND_DIGITAL_PWR_ON/OFF is not supported\n", + ERROR("comphy%d: Digital PWR ON/OFF is not supported\n", comphy_index); return -EINVAL; } @@ -2323,25 +2384,37 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index, uint switch (mode) { case(COMPHY_SATA_MODE): - err = mvebu_cp110_comphy_sata_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_sata_power_on(comphy_base, + comphy_index, + comphy_mode); break; case(COMPHY_SGMII_MODE): case(COMPHY_HS_SGMII_MODE): - err = mvebu_cp110_comphy_sgmii_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_sgmii_power_on(comphy_base, + comphy_index, + comphy_mode); break; /* From comphy perspective, XFI and SFI are the same */ case (COMPHY_XFI_MODE): case (COMPHY_SFI_MODE): - err = mvebu_cp110_comphy_xfi_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_xfi_power_on(comphy_base, + comphy_index, + comphy_mode); break; case (COMPHY_PCIE_MODE): - err = mvebu_cp110_comphy_pcie_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_pcie_power_on(comphy_base, + comphy_index, + comphy_mode); break; case (COMPHY_RXAUI_MODE): - err = mvebu_cp110_comphy_rxaui_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_rxaui_power_on(comphy_base, + comphy_index, + comphy_mode); case (COMPHY_USB3H_MODE): case (COMPHY_USB3D_MODE): - err = mvebu_cp110_comphy_usb3_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_usb3_power_on(comphy_base, + comphy_index, + comphy_mode); break; case (COMPHY_AP_MODE): err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index); diff --git a/drivers/marvell/dw-pcie-ep.c b/drivers/marvell/dw-pcie-ep.c index 7aa7a754..373d1dbc 100644 --- a/drivers/marvell/dw-pcie-ep.c +++ b/drivers/marvell/dw-pcie-ep.c @@ -4,8 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_def.h> + #include <mmio.h> +#include <mvebu_def.h> #define PCIE_CFG_VENDOR 0x0 #define PCIE_CFG_DEVICE 0x2 diff --git a/drivers/marvell/eawg.c b/drivers/marvell/eawg.c index 178fa4db..529867c4 100644 --- a/drivers/marvell/eawg.c +++ b/drivers/marvell/eawg.c @@ -8,8 +8,8 @@ #include <debug.h> #include <eawg.h> #include <mmio.h> +#include <mvebu_def.h> #include <stdio.h> -#include <plat_def.h> #define EAWG_BASE_REGS(ap) MVEBU_AR_RFU_BASE(ap) + 0x6000 #define EAWG_WRITE_ADDR_REG(ap) (EAWG_BASE_REGS(ap) + 0x0) diff --git a/drivers/marvell/gwin.c b/drivers/marvell/gwin.c index 07b34481..d09375d3 100644 --- a/drivers/marvell/gwin.c +++ b/drivers/marvell/gwin.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2017, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* GWIN unit device driver for Marvell AP810 SoC */ + +#include <armada_common.h> #include <debug.h> #include <gwin.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -20,7 +22,8 @@ #define WIN_ENABLE_BIT (0x1) #define WIN_TARGET_MASK (0xF) #define WIN_TARGET_SHIFT (0x8) -#define WIN_TARGET(tgt) (((tgt) & WIN_TARGET_MASK) << WIN_TARGET_SHIFT) +#define WIN_TARGET(tgt) (((tgt) & WIN_TARGET_MASK) \ + << WIN_TARGET_SHIFT) /* Bits[43:26] of the physical address are the window base, * which is aligned to 64MB @@ -30,9 +33,12 @@ #define GWIN_ALIGNMENT_64M (0x4000000) /* AP registers */ -#define GWIN_CR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x0 + (0x10 * (win))) -#define GWIN_ALR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x8 + (0x10 * (win))) -#define GWIN_AHR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0xc + (0x10 * (win))) +#define GWIN_CR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x0 + \ + (0x10 * (win))) +#define GWIN_ALR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x8 + \ + (0x10 * (win))) +#define GWIN_AHR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0xc + \ + (0x10 * (win))) #define CCU_GRU_CR_OFFSET(ap) (MVEBU_CCU_GRU_BASE(ap)) #define CCR_GRU_CR_GWIN_MBYPASS (1 << 1) @@ -42,17 +48,20 @@ static void gwin_check(struct addr_map_win *win) /* The base is always 64M aligned */ if (IS_NOT_ALIGN(win->base_addr, GWIN_ALIGNMENT_64M)) { win->base_addr &= ~(GWIN_ALIGNMENT_64M - 1); - NOTICE("%s: Align the base address to 0x%llx\n", __func__, win->base_addr); + NOTICE("%s: Align the base address to 0x%llx\n", + __func__, win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, GWIN_ALIGNMENT_64M)) { win->win_size = ALIGN_UP(win->win_size, GWIN_ALIGNMENT_64M); - NOTICE("%s: Aligning window size to 0x%llx\n", __func__, win->win_size); + NOTICE("%s: Aligning window size to 0x%llx\n", + __func__, win->win_size); } } -static void gwin_enable_window(int ap_index, struct addr_map_win *win, uint32_t win_num) +static void gwin_enable_window(int ap_index, struct addr_map_win *win, + uint32_t win_num) { uint32_t alr, ahr; uint64_t end_addr; @@ -117,6 +126,7 @@ void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size) for (int i = 0; i < size; i++) { uint64_t base; uint32_t target; + win_id = MVEBU_GWIN_MAX_WINS - i - 1; target = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_id)); @@ -128,7 +138,8 @@ void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size) base <<= ADDRESS_RSHIFT; if (win->target_id != target) { - ERROR("%s: Trying to remove bad window-%d!\n", __func__, win_id); + ERROR("%s: Trying to remove bad window-%d!\n", + __func__, win_id); continue; } gwin_disable_window(ap_index, win_id); @@ -142,8 +153,8 @@ static void dump_gwin(int ap_index) uint32_t win_num; /* Dump all GWIN windows */ - printf("\tbank target start end\n"); - printf("\t----------------------------------------------------\n"); + tf_printf("\tbank target start end\n"); + tf_printf("\t----------------------------------------------------\n"); for (win_num = 0; win_num < MVEBU_GWIN_MAX_WINS; win_num++) { uint32_t cr; uint64_t alr, ahr; @@ -155,10 +166,10 @@ static void dump_gwin(int ap_index) alr = (alr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT; ahr = mmio_read_32(GWIN_AHR_OFFSET(ap_index, win_num)); ahr = (ahr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT; - printf("\tgwin %d 0x%016llx 0x%016llx\n", (cr >> 8) & 0xF, alr, ahr); + tf_printf("\tgwin %d 0x%016llx 0x%016llx\n", + (cr >> 8) & 0xF, alr, ahr); } } - return; } #endif @@ -179,7 +190,8 @@ int init_gwin(int ap_index) } if (win_count > MVEBU_GWIN_MAX_WINS) { - ERROR("number of windows is bigger than %d\n", MVEBU_GWIN_MAX_WINS); + ERROR("number of windows is bigger than %d\n", + MVEBU_GWIN_MAX_WINS); return 0; } diff --git a/drivers/marvell/i2c/a8k_i2c.c b/drivers/marvell/i2c/a8k_i2c.c index 2ebdec8b..72a77316 100644 --- a/drivers/marvell/i2c/a8k_i2c.c +++ b/drivers/marvell/i2c/a8k_i2c.c @@ -1,59 +1,55 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - -/* This driver provides I2C support for A8K */ + +/* This driver provides I2C support for Marvell A8K and compatible SoCs */ #include <a8k_i2c.h> #include <debug.h> #include <delay_timer.h> +#include <errno.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_VERBOSE #define DEBUG_I2C #endif -#define CONFIG_SYS_TCLK 250000000 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define I2C_TIMEOUT_VALUE 0x500 -#define I2C_MAX_RETRY_CNT 1000 -#define I2C_CMD_WRITE 0x0 -#define I2C_CMD_READ 0x1 - -#define I2C_DATA_ADDR_7BIT_OFFS 0x1 -#define I2C_DATA_ADDR_7BIT_MASK (0xFF << I2C_DATA_ADDR_7BIT_OFFS) - -#define I2C_CONTROL_ACK 0x00000004 -#define I2C_CONTROL_IFLG 0x00000008 -#define I2C_CONTROL_STOP 0x00000010 -#define I2C_CONTROL_START 0x00000020 -#define I2C_CONTROL_TWSIEN 0x00000040 -#define I2C_CONTROL_INTEN 0x00000080 - -#define I2C_STATUS_START 0x08 -#define I2C_STATUS_REPEATED_START 0x10 -#define I2C_STATUS_ADDR_W_ACK 0x18 -#define I2C_STATUS_DATA_W_ACK 0x28 +#define CONFIG_SYS_TCLK 250000000 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define I2C_TIMEOUT_VALUE 0x500 +#define I2C_MAX_RETRY_CNT 1000 +#define I2C_CMD_WRITE 0x0 +#define I2C_CMD_READ 0x1 + +#define I2C_DATA_ADDR_7BIT_OFFS 0x1 +#define I2C_DATA_ADDR_7BIT_MASK (0xFF << I2C_DATA_ADDR_7BIT_OFFS) + +#define I2C_CONTROL_ACK 0x00000004 +#define I2C_CONTROL_IFLG 0x00000008 +#define I2C_CONTROL_STOP 0x00000010 +#define I2C_CONTROL_START 0x00000020 +#define I2C_CONTROL_TWSIEN 0x00000040 +#define I2C_CONTROL_INTEN 0x00000080 + +#define I2C_STATUS_START 0x08 +#define I2C_STATUS_REPEATED_START 0x10 +#define I2C_STATUS_ADDR_W_ACK 0x18 +#define I2C_STATUS_DATA_W_ACK 0x28 #define I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER 0x38 -#define I2C_STATUS_ADDR_R_ACK 0x40 -#define I2C_STATUS_DATA_R_ACK 0x50 -#define I2C_STATUS_DATA_R_NAK 0x58 +#define I2C_STATUS_ADDR_R_ACK 0x40 +#define I2C_STATUS_DATA_R_ACK 0x50 +#define I2C_STATUS_DATA_R_NAK 0x58 #define I2C_STATUS_LOST_ARB_GENERAL_CALL 0x78 -#define I2C_STATUS_IDLE 0xF8 +#define I2C_STATUS_IDLE 0xF8 #define I2C_UNSTUCK_TRIGGER 0x1 #define I2C_UNSTUCK_ONGOING 0x2 #define I2C_UNSTUCK_ERROR 0x4 - -#define EPERM 1 /* Operation not permitted */ -#define EAGAIN 11 /* Try again */ -#define ETIMEDOUT 110 /* Connection timed out */ - struct marvell_i2c_regs { uint32_t slave_address; uint32_t data; @@ -74,7 +70,8 @@ static struct marvell_i2c_regs *base; static int marvell_i2c_lost_arbitration(uint32_t *status) { *status = mmio_read_32((uintptr_t)&base->u.status); - if ((I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER == *status) || (I2C_STATUS_LOST_ARB_GENERAL_CALL == *status)) + if ((*status == I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER) || + (*status == I2C_STATUS_LOST_ARB_GENERAL_CALL)) return -EAGAIN; return 0; @@ -89,8 +86,6 @@ static void marvell_i2c_interrupt_clear(void) mmio_write_32((uintptr_t)&base->control, reg); /* Wait for 1 us for the clear to take effect */ udelay(1); - - return; } static int marvell_i2c_interrupt_get(void) @@ -106,6 +101,7 @@ static int marvell_i2c_interrupt_get(void) static int marvell_i2c_wait_interrupt(void) { uint32_t timeout = 0; + while (!marvell_i2c_interrupt_get() && (timeout++ < I2C_TIMEOUT_VALUE)) ; if (timeout >= I2C_TIMEOUT_VALUE) @@ -123,7 +119,9 @@ static int marvell_i2c_start_bit_set(void) is_int_flag = 1; /* set start bit */ - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_START); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_START); /* in case that the int flag was set before i.e. repeated start bit */ if (is_int_flag) { @@ -137,17 +135,20 @@ static int marvell_i2c_start_bit_set(void) } /* check that start bit went down */ - if ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_START) != 0) { + if ((mmio_read_32((uintptr_t)&base->control) & + I2C_CONTROL_START) != 0) { ERROR("Start bit didn't went down\n"); return -EPERM; } /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } - if ((status != I2C_STATUS_START) && (status != I2C_STATUS_REPEATED_START)) { + if ((status != I2C_STATUS_START) && + (status != I2C_STATUS_REPEATED_START)) { ERROR("Got status %x after enable start bit.\n", status); return -EPERM; } @@ -161,12 +162,15 @@ static int marvell_i2c_stop_bit_set(void) uint32_t status; /* Generate stop bit */ - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_STOP); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_STOP); marvell_i2c_interrupt_clear(); timeout = 0; /* Read control register, check the control stop bit */ - while ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) && (timeout++ < I2C_TIMEOUT_VALUE)) + while ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) && + (timeout++ < I2C_TIMEOUT_VALUE)) ; if (timeout >= I2C_TIMEOUT_VALUE) { ERROR("Stop bit didn't went down\n"); @@ -181,7 +185,8 @@ static int marvell_i2c_stop_bit_set(void) /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } if (status != I2C_STATUS_IDLE) { @@ -210,15 +215,18 @@ static int marvell_i2c_address_set(uint8_t chain, int command) /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } if (((status != I2C_STATUS_ADDR_R_ACK) && (command == I2C_CMD_READ)) || ((status != I2C_STATUS_ADDR_W_ACK) && (command == I2C_CMD_WRITE))) { - /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't - want error messages in case DIMM doesn't exist. */ - INFO("%s: ERROR - status %x addr in %s mode.\n", __func__, status, (command == I2C_CMD_WRITE) ? - "Write" : "Read"); + /* only in debug, since in boot we try to read the SPD + * of both DRAM, and we don't want error messages in cas + * DIMM doesn't exist. + */ + INFO("%s: ERROR - status %x addr in %s mode.\n", __func__, + status, (command == I2C_CMD_WRITE) ? "Write" : "Read"); return -EPERM; } @@ -245,21 +253,23 @@ static unsigned int marvell_i2c_bus_speed_set(unsigned int requested_speed) unsigned int actual_n = 0, actual_m = 0; int val; - /* Calucalte N and M for the TWSI clock baud rate */ + /* Calculate N and M for the TWSI clock baud rate */ for (n = 0; n < 8; n++) { for (m = 0; m < 16; m++) { freq = CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); val = requested_speed - freq; margin = (val > 0) ? val : -val; - if ((freq <= requested_speed) && (margin < min_margin)) { + if ((freq <= requested_speed) && + (margin < min_margin)) { min_margin = margin; actual_n = n; actual_m = m; } } } - VERBOSE("%s: actual_n = %u, actual_m = %u\n", __func__, actual_n, actual_m); + VERBOSE("%s: actual_n = %u, actual_m = %u\n", + __func__, actual_n, actual_m); /* Set the baud rate */ mmio_write_32((uintptr_t)&base->u.baudrate, (actual_m << 3) | actual_n); @@ -274,14 +284,16 @@ static int marvell_i2c_probe(uint8_t chip) ret = marvell_i2c_start_bit_set(); if (ret != 0) { marvell_i2c_stop_bit_set(); - ERROR("%s - %d: %s", __func__, __LINE__, "marvell_i2c_start_bit_set failed\n"); + ERROR("%s - %d: %s", __func__, __LINE__, + "marvell_i2c_start_bit_set failed\n"); return -EPERM; } ret = marvell_i2c_address_set(chip, I2C_CMD_WRITE); if (ret != 0) { marvell_i2c_stop_bit_set(); - ERROR("%s - %d: %s", __func__, __LINE__, "marvell_i2c_address_set failed\n"); + ERROR("%s - %d: %s", __func__, __LINE__, + "marvell_i2c_address_set failed\n"); return -EPERM; } @@ -317,21 +329,25 @@ static int marvell_i2c_data_receive(uint8_t *p_block, uint32_t block_size) } /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } - if ((status != I2C_STATUS_DATA_R_ACK) && (block_size_read != 1)) { + if ((status != I2C_STATUS_DATA_R_ACK) && + (block_size_read != 1)) { ERROR("Status %x in read transaction\n", status); return -EPERM; } - if ((status != I2C_STATUS_DATA_R_NAK) && (block_size_read == 1)) { + if ((status != I2C_STATUS_DATA_R_NAK) && + (block_size_read == 1)) { ERROR("Status %x in Rd Terminate\n", status); return -EPERM; } /* read the data */ *p_block = (uint8_t) mmio_read_32((uintptr_t)&base->data); - VERBOSE("%s: place %d read %x\n", __func__, block_size - block_size_read, *p_block); + VERBOSE("%s: place %d read %x\n", __func__, + block_size - block_size_read, *p_block); p_block++; block_size_read--; } @@ -351,7 +367,8 @@ static int marvell_i2c_data_transmit(uint8_t *p_block, uint32_t block_size) while (block_size_write) { /* write the data */ mmio_write_32((uintptr_t)&base->data, (uint32_t) *p_block); - VERBOSE("%s: index = %d, data = %x\n", __func__, block_size - block_size_write, *p_block); + VERBOSE("%s: index = %d, data = %x\n", __func__, + block_size - block_size_write, *p_block); p_block++; block_size_write--; @@ -364,7 +381,8 @@ static int marvell_i2c_data_transmit(uint8_t *p_block, uint32_t block_size) /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } if (status != I2C_STATUS_DATA_W_ACK) { @@ -389,7 +407,8 @@ static int marvell_i2c_target_offset_set(uint8_t chip, uint32_t addr, int alen) off_block[0] = addr & 0xff; off_size = 1; } - VERBOSE("%s: off_size = %x addr1 = %x addr2 = %x\n", __func__, off_size, off_block[0], off_block[1]); + VERBOSE("%s: off_size = %x addr1 = %x addr2 = %x\n", __func__, + off_size, off_block[0], off_block[1]); return marvell_i2c_data_transmit(off_block, off_size); } @@ -417,13 +436,13 @@ static int marvell_i2c_unstuck(int ret) return ret; } -/* +/* * API Functions */ void i2c_init(void *i2c_base) { /* For I2C speed and slave address, now we do not set them since - * we just provide the working speed and slave address in plat_def.h + * we just provide the working speed and slave address in mvebu_def.h * for i2c_init */ base = (struct marvell_i2c_regs *)i2c_base; @@ -436,14 +455,17 @@ void i2c_init(void *i2c_base) marvell_i2c_bus_speed_set(CONFIG_SYS_I2C_SPEED); /* Enable the I2C and slave */ - mmio_write_32((uintptr_t)&base->control, I2C_CONTROL_TWSIEN | I2C_CONTROL_ACK); + mmio_write_32((uintptr_t)&base->control, + I2C_CONTROL_TWSIEN | I2C_CONTROL_ACK); /* set the I2C slave address */ mmio_write_32((uintptr_t)&base->xtnd_slave_addr, 0); mmio_write_32((uintptr_t)&base->slave_address, CONFIG_SYS_I2C_SLAVE); /* unmask I2C interrupt */ - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_INTEN); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_INTEN); udelay(10); } @@ -472,7 +494,8 @@ int i2c_read(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len) do { if (ret != -EAGAIN && ret) { - ERROR("i2c transaction failed, after %d retries\n", counter); + ERROR("i2c transaction failed, after %d retries\n", + counter); marvell_i2c_stop_bit_set(); return ret; } @@ -514,10 +537,13 @@ int i2c_read(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len) } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); if (counter == I2C_MAX_RETRY_CNT) { - ERROR("I2C transactions failed, got EAGAIN %d times\n", I2C_MAX_RETRY_CNT); + ERROR("I2C transactions failed, got EAGAIN %d times\n", + I2C_MAX_RETRY_CNT); ret = -EPERM; } - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_ACK); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_ACK); udelay(1); return ret; @@ -577,7 +603,8 @@ int i2c_write(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len) } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); if (counter == I2C_MAX_RETRY_CNT) { - ERROR("I2C transactions failed, got EAGAIN %d times\n", I2C_MAX_RETRY_CNT); + ERROR("I2C transactions failed, got EAGAIN %d times\n", + I2C_MAX_RETRY_CNT); ret = -EPERM; } diff --git a/drivers/marvell/icu.c b/drivers/marvell/icu.c index 144dfc86..20d46a1b 100644 --- a/drivers/marvell/icu.c +++ b/drivers/marvell/icu.c @@ -7,7 +7,7 @@ #include <icu.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define ICU_SET_SPI_AL(x) (0x10 + (0x10 * x)) #define ICU_SET_SPI_AH(x) (0x14 + (0x10 * x)) diff --git a/drivers/marvell/io_win.c b/drivers/marvell/io_win.c index 164cbbb8..b8f09776 100644 --- a/drivers/marvell/io_win.c +++ b/drivers/marvell/io_win.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */ + +#include <armada_common.h> #include <debug.h> #include <io_win.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -25,9 +27,12 @@ #define IO_WIN_ALIGNMENT_64K (0x10000) /* AP registers */ -#define IO_WIN_ALR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x0 + (0x10 * win)) -#define IO_WIN_AHR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x8 + (0x10 * win)) -#define IO_WIN_CR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0xC + (0x10 * win)) +#define IO_WIN_ALR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x0 + \ + (0x10 * win)) +#define IO_WIN_AHR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x8 + \ + (0x10 * win)) +#define IO_WIN_CR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0xC + \ + (0x10 * win)) /* For storage of CR, ALR, AHR abd GCR */ static uint32_t io_win_regs_save[MVEBU_IO_WIN_MAX_WINS * 3 + 1]; @@ -38,17 +43,20 @@ static void io_win_check(struct addr_map_win *win) /* check if address is aligned to 1M */ if (IS_NOT_ALIGN(win->base_addr, IO_WIN_ALIGNMENT_1M)) { win->base_addr = ALIGN_UP(win->base_addr, IO_WIN_ALIGNMENT_1M); - NOTICE("%s: Align up the base address to 0x%llx\n", __func__, win->base_addr); + NOTICE("%s: Align up the base address to 0x%llx\n", + __func__, win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, IO_WIN_ALIGNMENT_1M)) { win->win_size = ALIGN_UP(win->win_size, IO_WIN_ALIGNMENT_1M); - NOTICE("%s: Aligning size to 0x%llx\n", __func__, win->win_size); + NOTICE("%s: Aligning size to 0x%llx\n", + __func__, win->win_size); } } -static void io_win_enable_window(int ap_index, struct addr_map_win *win, uint32_t win_num) +static void io_win_enable_window(int ap_index, struct addr_map_win *win, + uint32_t win_num) { uint32_t alr, ahr; uint64_t end_addr; @@ -124,6 +132,7 @@ void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size) for (int i = 0; i < size; i++) { uint64_t base; uint32_t target; + win_id = MVEBU_IO_WIN_MAX_WINS - i - 1; target = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, win_id)); @@ -132,7 +141,8 @@ void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size) base <<= ADDRESS_SHIFT; if ((win->target_id != target) || (win->base_addr != base)) { - ERROR("%s: Trying to remove bad window-%d!\n", __func__, win_id); + ERROR("%s: Trying to remove bad window-%d!\n", + __func__, win_id); continue; } io_win_disable_window(ap_index, win_id); @@ -148,26 +158,29 @@ static void dump_io_win(int ap_index) uint64_t start, end; /* Dump all IO windows */ - printf("\tbank target start end\n"); - printf("\t----------------------------------------------------\n"); + tf_printf("\tbank target start end\n"); + tf_printf("\t----------------------------------------------------\n"); for (win_id = 0; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) { alr = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_id)); if (alr & WIN_ENABLE_BIT) { alr &= ~WIN_ENABLE_BIT; ahr = mmio_read_32(IO_WIN_AHR_OFFSET(ap_index, win_id)); - trgt_id = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, win_id)); + trgt_id = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, + win_id)); start = ((uint64_t)alr << ADDRESS_SHIFT); end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); - printf("\tio-win %d 0x%016llx 0x%016llx\n", trgt_id, start, end); + tf_printf("\tio-win %d 0x%016llx 0x%016llx\n", + trgt_id, start, end); } } - printf("\tio-win gcr is %x\n", mmio_read_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET)); - - return; + tf_printf("\tio-win gcr is %x\n", + mmio_read_32(MVEBU_IO_WIN_BASE(ap_index) + + MVEBU_IO_WIN_GCR_OFFSET)); } #endif -static void iow_save_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void iow_save_win_range(int ap_id, int win_first, int win_last, + uint32_t *buffer) { int win_id, idx; @@ -181,7 +194,8 @@ static void iow_save_win_range(int ap_id, int win_first, int win_last, uint32_t MVEBU_IO_WIN_GCR_OFFSET); } -static void iow_restore_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void iow_restore_win_range(int ap_id, int win_first, int win_last, + uint32_t *buffer) { int win_id, idx; @@ -197,12 +211,14 @@ static void iow_restore_win_range(int ap_id, int win_first, int win_last, uint32 void iow_save_win_all(int ap_id) { - iow_save_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, io_win_regs_save); + iow_save_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, + io_win_regs_save); } void iow_restore_win_all(int ap_id) { - iow_restore_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, io_win_regs_save); + iow_restore_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, + io_win_regs_save); } int init_io_win(int ap_index) @@ -219,19 +235,23 @@ int init_io_win(int ap_index) INFO("no windows configurations found\n"); if (win_count > MVEBU_IO_WIN_MAX_WINS) { - INFO("number of windows is bigger than %d\n", MVEBU_IO_WIN_MAX_WINS); + INFO("number of windows is bigger than %d\n", + MVEBU_IO_WIN_MAX_WINS); return 0; } /* Get the default target id to set the GCR */ win_reg = marvell_get_io_win_gcr_target(ap_index); - mmio_write_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET, win_reg); + mmio_write_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET, + win_reg); /* disable all IO windows */ for (win_id = 1; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) io_win_disable_window(ap_index, win_id); - /* enable relevant windows, starting from win_id=1 because index 0 dedicated for BootRom */ + /* enable relevant windows, starting from win_id = 1 because + * index 0 dedicated for BootROM + */ for (win_id = 1; win_id <= win_count; win_id++, win++) { io_win_check(win); io_win_enable_window(ap_index, win, win_id); diff --git a/drivers/marvell/iob.c b/drivers/marvell/iob.c index 343a7cb4..0a30287f 100644 --- a/drivers/marvell/iob.c +++ b/drivers/marvell/iob.c @@ -5,13 +5,15 @@ * https://spdx.org/licenses */ +/* IOW unit device driver for Marvell CP110 and CP115 SoCs */ + +#include <armada_common.h> #include <arch_helpers.h> #include <debug.h> #include <iob.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -48,15 +50,18 @@ static void iob_win_check(struct addr_map_win *win, uint32_t win_num) /* check if address is aligned to the size */ if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) { win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT); - ERROR("Window %d: base address unaligned to 0x%x\n", win_num, IOB_WIN_ALIGNMENT); - printf("Align up the base address to 0x%llx\n", win->base_addr); + ERROR("Window %d: base address unaligned to 0x%x\n", + win_num, IOB_WIN_ALIGNMENT); + tf_printf("Align up the base address to 0x%llx\n", + win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) { win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT); - ERROR("Window %d: window size unaligned to 0x%x\n", win_num, IOB_WIN_ALIGNMENT); - printf("Aligning size to 0x%llx\n", win->win_size); + ERROR("Window %d: window size unaligned to 0x%x\n", win_num, + IOB_WIN_ALIGNMENT); + tf_printf("Aligning size to 0x%llx\n", win->win_size); } } @@ -74,7 +79,8 @@ static void iob_enable_win(struct addr_map_win *win, uint32_t win_id) mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr); iob_win_reg = WIN_ENABLE_BIT; - iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK) << IOB_TARGET_ID_OFFSET; + iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK) + << IOB_TARGET_ID_OFFSET; mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg); } @@ -85,16 +91,18 @@ static void dump_iob(void) uint32_t win_id, win_cr, alr, ahr; uint8_t target_id; uint64_t start, end; - char *iob_target_name[IOB_MAX_TID] = {"CFG ", "MCI0 ", "PEX1 ", "PEX2 ", - "PEX0 ", "NAND ", "RUNIT", "MCI1 "}; + char *iob_target_name[IOB_MAX_TID] = { + "CFG ", "MCI0 ", "PEX1 ", "PEX2 ", + "PEX0 ", "NAND ", "RUNIT", "MCI1 " }; /* Dump all IOB windows */ - printf("bank id target start end\n"); - printf("----------------------------------------------------\n"); + tf_printf("bank id target start end\n"); + tf_printf("----------------------------------------------------\n"); for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) { win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); if (win_cr & WIN_ENABLE_BIT) { - target_id = (win_cr >> IOB_TARGET_ID_OFFSET) & IOB_TARGET_ID_MASK; + target_id = (win_cr >> IOB_TARGET_ID_OFFSET) & + IOB_TARGET_ID_MASK; alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id)); start = ((uint64_t)alr << ADDRESS_SHIFT); if (win_id != 0) { @@ -102,31 +110,33 @@ static void dump_iob(void) end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); } else { /* Window #0 size is hardcoded to 16MB, as it's - ** reserved for CP configuration space. */ + * reserved for CP configuration space. + */ end = start + (16 << 20); } - printf("iob %02d %s 0x%016llx 0x%016llx\n" - , win_id, iob_target_name[target_id], start, end); + tf_printf("iob %02d %s 0x%016llx 0x%016llx\n", + win_id, iob_target_name[target_id], + start, end); } } - - return; } #endif -void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base, uintptr_t new_base) +void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base, + uintptr_t new_base) { debug_enter(); iob_base = base + MVEBU_IOB_OFFSET; - NOTICE("Change the base address of AP%d-CP%d to %lx\n", ap_idx, cp_idx, new_base); + NOTICE("Change the base address of AP%d-CP%d to %lx\n", + ap_idx, cp_idx, new_base); mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT); iob_base = new_base + MVEBU_IOB_OFFSET; /* Make sure the address was configured by the CPU before - * any possibe access to the CP. + * any possible access to the CP. */ dsb(); @@ -150,12 +160,14 @@ int init_iob(uintptr_t base) INFO("no windows configurations found\n"); return 0; } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) { - ERROR("IOB memory map array greater than max available windows, set win_count to max %d\n", - MVEBU_IOB_MAX_WINS); + ERROR("IOB mem map array > than max available windows (%d)\n", + MVEBU_IOB_MAX_WINS); win_count = MVEBU_IOB_MAX_WINS; } - /* disable all IOB windows, start from win_id = 1 because can't disable internal register window */ + /* disable all IOB windows, start from win_id = 1 + * because can't disable internal register window + */ for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) { win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); win_reg &= ~WIN_ENABLE_BIT; diff --git a/drivers/marvell/jtag.c b/drivers/marvell/jtag.c index 7800524e..3d8f30c9 100644 --- a/drivers/marvell/jtag.c +++ b/drivers/marvell/jtag.c @@ -5,9 +5,9 @@ * https://spdx.org/licenses */ -#include <plat_def.h> -#include <mmio.h> #include <delay_timer.h> +#include <mmio.h> +#include <mvebu_def.h> #define MPP_CTRL_REG 0xEC6f4000 #define GPIO_DATA_EN 0xEC6f5044 diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.c b/drivers/marvell/mc_trustzone/mc_trustzone.c index 6062379f..bd4295a3 100644 --- a/drivers/marvell/mc_trustzone/mc_trustzone.c +++ b/drivers/marvell/mc_trustzone/mc_trustzone.c @@ -8,7 +8,7 @@ #include <addr_map.h> #include <debug.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include "mc_trustzone.h" #define TZ_SIZE(x) ((x) >> 13) diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c index a35c2b22..721504e0 100644 --- a/drivers/marvell/mci.c +++ b/drivers/marvell/mci.c @@ -1,53 +1,67 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* MCI bus driver for Marvell ARMADA 8K and 8K+ SoCs */ + #include <debug.h> #include <delay_timer.h> #include <mmio.h> #include <mci.h> #include <mvebu.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> -/* /HB /Units /Direct_regs /Direct regs /Configuration Register Write/Read Data Register */ -#define MCI_WRITE_READ_DATA_REG(mci_index) MVEBU_MCI_REG_BASE_REMAP(mci_index) -/* /HB /Units /Direct_regs /Direct regs /Configuration Register Access Command Register */ -#define MCI_ACCESS_CMD_REG(mci_index) (MVEBU_MCI_REG_BASE_REMAP(mci_index) + 0x4) +/* /HB /Units /Direct_regs /Direct regs + * /Configuration Register Write/Read Data Register + */ +#define MCI_WRITE_READ_DATA_REG(mci_index) \ + MVEBU_MCI_REG_BASE_REMAP(mci_index) +/* /HB /Units /Direct_regs /Direct regs + * /Configuration Register Access Command Register + */ +#define MCI_ACCESS_CMD_REG(mci_index) \ + (MVEBU_MCI_REG_BASE_REMAP(mci_index) + 0x4) /* Access Command fields : - * bit[3:0] - Sub command: 1 => Periferal Config Register Read, - * 0 => Periferal Config Refister Write, - * 2 => Periferal Assign ID request, + * bit[3:0] - Sub command: 1 => Peripheral Config Register Read, + * 0 => Peripheral Config Register Write, + * 2 => Peripheral Assign ID request, * 3 => Circular Config Write * bit[5] - 1 => Local (same chip access) 0 => Remote * bit[15:8] - Destination hop ID. Put Global ID (GID) here (see scheme below). * bit[23:22] - 0x3 IHB PHY REG address space, 0x0 IHB Controller space * bit[21:16] - Low 6 bits of offset. Hight 2 bits are taken from bit[28:27] - * of IHB_PHY_CTRL (must be set before any PHY register access occures): - * /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Version Control Register + * of IHB_PHY_CTRL + * (must be set before any PHY register access occurs): + * /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Version Control Register * - * ixi_ihb_top IHB PHY + * ixi_ihb_top IHB PHY * AXI ----------------------------- ------------- * <--| axi_hb_top | ihb_pipe_top |-->| | * -->| GID=1 | GID=0 |<--| | * ----------------------------- ------------- */ -#define MCI_INDIRECT_CTRL_READ_CMD 0x1 -#define MCI_INDIRECT_CTRL_ASSIGN_CMD 0x2 -#define MCI_INDIRECT_CTRL_CIRCULAR_CMD 0x3 -#define MCI_INDIRECT_CTRL_LOCAL_PKT (1 << 5) -#define MCI_INDIRECT_CTRL_CMD_DONE_OFFSET 6 -#define MCI_INDIRECT_CTRL_CMD_DONE (1 << MCI_INDIRECT_CTRL_CMD_DONE_OFFSET) -#define MCI_INDIRECT_CTRL_DATA_READY_OFFSET 7 -#define MCI_INDIRECT_CTRL_DATA_READY (1 << MCI_INDIRECT_CTRL_DATA_READY_OFFSET) -#define MCI_INDIRECT_CTRL_HOPID_OFFSET 8 -#define MCI_INDIRECT_CTRL_HOPID(id) (((id) & 0xFF) << MCI_INDIRECT_CTRL_HOPID_OFFSET) -#define MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET 16 -#define MCI_INDIRECT_REG_CTRL_ADDR(reg_num) (reg_num << MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET) +#define MCI_INDIRECT_CTRL_READ_CMD 0x1 +#define MCI_INDIRECT_CTRL_ASSIGN_CMD 0x2 +#define MCI_INDIRECT_CTRL_CIRCULAR_CMD 0x3 +#define MCI_INDIRECT_CTRL_LOCAL_PKT (1 << 5) +#define MCI_INDIRECT_CTRL_CMD_DONE_OFFSET 6 +#define MCI_INDIRECT_CTRL_CMD_DONE \ + (1 << MCI_INDIRECT_CTRL_CMD_DONE_OFFSET) +#define MCI_INDIRECT_CTRL_DATA_READY_OFFSET 7 +#define MCI_INDIRECT_CTRL_DATA_READY \ + (1 << MCI_INDIRECT_CTRL_DATA_READY_OFFSET) +#define MCI_INDIRECT_CTRL_HOPID_OFFSET 8 +#define MCI_INDIRECT_CTRL_HOPID(id) \ + (((id) & 0xFF) << MCI_INDIRECT_CTRL_HOPID_OFFSET) +#define MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET 16 +#define MCI_INDIRECT_REG_CTRL_ADDR(reg_num) \ + (reg_num << MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET) /* Hop ID values */ #define GID_IHB_PIPE 0 @@ -73,95 +87,121 @@ #define MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(val) (((val) & 0xF) << 4) #define MCI_CTRL_RX_TX_MEM_CFG_RTC(val) (((val) & 0x3) << 2) #define MCI_CTRL_RX_TX_MEM_CFG_WTC(val) (((val) & 0x3) << 0) -#define MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x07) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ - MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ - MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) - -#define MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x03) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ - MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ - MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL \ + (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x07) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) + +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL \ + (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x03) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) /* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers/ - * Tx Memory Configuration Register (TX_MEM_CFG) */ + * Tx Memory Configuration Register (TX_MEM_CFG) + */ #define MCI_CTRL_TX_MEM_CFG_REG_NUM 0x1 -/* field mapping for TX mem config register are the as for RX register - see register above */ -#define MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x20) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x20) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x20) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(2) | \ - MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ - MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) - -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Link CRC Control */ +/* field mapping for TX mem config register + * are the same as for RX register - see register above + */ +#define MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL \ + (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x20) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x20) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x20) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(2) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) + +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Link CRC Control + */ /* MCi Link CRC Control Register (MCi_CRC_CTRL) */ #define MCI_LINK_CRC_CTRL_REG_NUM 0x4 -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Status Register */ +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Status Register + */ /* MCi Status Register (MCi_STS) */ #define MCI_CTRL_STATUS_REG_NUM 0x5 #define MCI_CTRL_STATUS_REG_PHY_READY (1 << 12) #define MCI_CTRL_STATUS_REG_LINK_PRESENT (1 << 15) #define MCI_CTRL_STATUS_REG_PHY_CID_VIO_OFFSET 24 -#define MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK (0xF << MCI_CTRL_STATUS_REG_PHY_CID_VIO_OFFSET) +#define MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK \ + (0xF << MCI_CTRL_STATUS_REG_PHY_CID_VIO_OFFSET) /* Expected successful Link result, including reserved bit */ -#define MCI_CTRL_PHY_READY (MCI_CTRL_STATUS_REG_PHY_READY | \ - MCI_CTRL_STATUS_REG_LINK_PRESENT | \ - MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK) +#define MCI_CTRL_PHY_READY (MCI_CTRL_STATUS_REG_PHY_READY | \ + MCI_CTRL_STATUS_REG_LINK_PRESENT | \ + MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK) /* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers/ - * MCi PHY Speed Settings Register (MCi_PHY_SETTING) */ + * MCi PHY Speed Settings Register (MCi_PHY_SETTING) + */ #define MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM 0x8 #define MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(val) (((val) & 0xF) << 28) #define MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(val) (((val) & 0xF) << 12) #define MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(val) (((val) & 0xF) << 8) #define MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(val) (((val) & 0xF) << 4) #define MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(val) (((val) & 0x1) << 1) -#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x2) | \ - MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) -#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x5) | \ - MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) - -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Mode Config */ +#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL \ + (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x2) | \ + MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) +#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 \ + (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x5) | \ + MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) + +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Mode Config + */ #define MCI_CTRL_IHB_MODE_CFG_REG_NUM 0x25 #define MCI_CTRL_IHB_MODE_HBCLK_DIV(val) ((val) & 0xFF) #define MCI_CTRL_IHB_MODE_CHUNK_MOD_OFFSET 8 -#define MCI_CTRL_IHB_MODE_CHUNK_MOD (1 << MCI_CTRL_IHB_MODE_CHUNK_MOD_OFFSET) +#define MCI_CTRL_IHB_MODE_CHUNK_MOD \ + (1 << MCI_CTRL_IHB_MODE_CHUNK_MOD_OFFSET) #define MCI_CTRL_IHB_MODE_FWD_MOD_OFFSET 9 -#define MCI_CTRL_IHB_MODE_FWD_MOD (1 << MCI_CTRL_IHB_MODE_FWD_MOD_OFFSET) +#define MCI_CTRL_IHB_MODE_FWD_MOD \ + (1 << MCI_CTRL_IHB_MODE_FWD_MOD_OFFSET) #define MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(val) (((val) & 0xF) << 12) #define MCI_CTRL_IHB_MODE_RX_COMB_THRESH(val) (((val) & 0xFF) << 16) #define MCI_CTRL_IHB_MODE_TX_COMB_THRESH(val) (((val) & 0xFF) << 24) -#define MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL (MCI_CTRL_IHB_MODE_HBCLK_DIV(6) | \ - MCI_CTRL_IHB_MODE_FWD_MOD | \ - MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(0xF) | \ - MCI_CTRL_IHB_MODE_RX_COMB_THRESH(0x3f) | \ - MCI_CTRL_IHB_MODE_TX_COMB_THRESH(0x40)) +#define MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL \ + (MCI_CTRL_IHB_MODE_HBCLK_DIV(6) | \ + MCI_CTRL_IHB_MODE_FWD_MOD | \ + MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(0xF) | \ + MCI_CTRL_IHB_MODE_RX_COMB_THRESH(0x3f) | \ + MCI_CTRL_IHB_MODE_TX_COMB_THRESH(0x40)) /* AXI_HB registers */ #define MCI_AXI_ACCESS_DATA_REG_NUM 0x0 #define MCI_AXI_ACCESS_PCIE_MODE 1 #define MCI_AXI_ACCESS_CACHE_CHECK_OFFSET 5 -#define MCI_AXI_ACCESS_CACHE_CHECK (1 << MCI_AXI_ACCESS_CACHE_CHECK_OFFSET) +#define MCI_AXI_ACCESS_CACHE_CHECK \ + (1 << MCI_AXI_ACCESS_CACHE_CHECK_OFFSET) #define MCI_AXI_ACCESS_FORCE_POST_WR_OFFSET 6 -#define MCI_AXI_ACCESS_FORCE_POST_WR (1 << MCI_AXI_ACCESS_FORCE_POST_WR_OFFSET) +#define MCI_AXI_ACCESS_FORCE_POST_WR \ + (1 << MCI_AXI_ACCESS_FORCE_POST_WR_OFFSET) #define MCI_AXI_ACCESS_DISABLE_CLK_GATING_OFFSET 9 -#define MCI_AXI_ACCESS_DISABLE_CLK_GATING (1 << MCI_AXI_ACCESS_DISABLE_CLK_GATING_OFFSET) +#define MCI_AXI_ACCESS_DISABLE_CLK_GATING \ + (1 << MCI_AXI_ACCESS_DISABLE_CLK_GATING_OFFSET) -/* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Window 0 Address Mask Register */ +/* /HB /Units /HB_REG /HB_REGHopping Bus Registers + * /Window 0 Address Mask Register + */ #define MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM 0x2 -/* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Window 0 Destination Register */ +/* /HB /Units /HB_REG /HB_REGHopping Bus Registers + * /Window 0 Destination Register + */ #define MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM 0x3 #define MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(val) (((val) & 0x1) << 16) #define MCI_HB_CTRL_WIN0_DEST_ID(val) (((val) & 0xFF) << 0) @@ -169,28 +209,42 @@ /* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Tx Control Register */ #define MCI_HB_CTRL_TX_CTRL_REG_NUM 0xD #define MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET 24 -#define MCI_HB_CTRL_TX_CTRL_PCIE_MODE (1 << MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET) +#define MCI_HB_CTRL_TX_CTRL_PCIE_MODE \ + (1 << MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET) #define MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(val) (((val) & 0xF) << 12) #define MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(val) (((val) & 0x1F) << 6) #define MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(val) (((val) & 0x1F) << 0) -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Version Control Register */ +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Version Control Register + */ #define MCI_PHY_CTRL_REG_NUM 0x7 #define MCI_PHY_CTRL_MCI_MINOR 0x8 /* BITS [3:0] */ #define MCI_PHY_CTRL_MCI_MAJOR_OFFSET 4 -#define MCI_PHY_CTRL_MCI_MAJOR (1 << MCI_PHY_CTRL_MCI_MAJOR_OFFSET) +#define MCI_PHY_CTRL_MCI_MAJOR \ + (1 << MCI_PHY_CTRL_MCI_MAJOR_OFFSET) #define MCI_PHY_CTRL_MCI_SLEEP_REQ_OFFSET 11 -#define MCI_PHY_CTRL_MCI_SLEEP_REQ (1 << MCI_PHY_CTRL_MCI_SLEEP_REQ_OFFSET) -#define MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET 24 /* Host=1 / Device=0 PHY mode */ -#define MCI_PHY_CTRL_MCI_PHY_MODE_HOST (1 << MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET) -#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET 25 /* Register=1 / PWM=0 interface */ -#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE (1 << MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET) -#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET 26 /* PHY code InReset=1 */ -#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE (1 << MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET) +#define MCI_PHY_CTRL_MCI_SLEEP_REQ \ + (1 << MCI_PHY_CTRL_MCI_SLEEP_REQ_OFFSET) +/* Host=1 / Device=0 PHY mode */ +#define MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET 24 +#define MCI_PHY_CTRL_MCI_PHY_MODE_HOST \ + (1 << MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET) +/* Register=1 / PWM=0 interface */ +#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET 25 +#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE \ + (1 << MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET) + /* PHY code InReset=1 */ +#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET 26 +#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE \ + (1 << MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET) #define MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET 27 -#define MCI_PHY_CTRL_PHY_ADDR_MSB(addr) (((addr) & 0x3) << MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET) +#define MCI_PHY_CTRL_PHY_ADDR_MSB(addr) \ + (((addr) & 0x3) << \ + MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET) #define MCI_PHY_CTRL_PIDI_MODE_OFFSET 31 -#define MCI_PHY_CTRL_PIDI_MODE (1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET) +#define MCI_PHY_CTRL_PIDI_MODE \ + (1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET) /* Number of times to wait for the MCI link ready after MCI configurations * Normally takes 34-35 successive reads @@ -221,6 +275,7 @@ static void mci_mmio_write_32(uintptr_t addr, uint32_t value) static uint32_t mci_mmio_read_32(uintptr_t addr) { uint32_t value; + value = mmio_read_32(addr); VERBOSE("Read:\t0x%x = 0x%x\n", (uint32_t)addr, value); return value; @@ -251,7 +306,8 @@ static int mci_poll_command_completion(int mci_index, int command_type) (retry_count-- > 0)); if (retry_count == 0) { - ERROR("%s: MCI command timeout (command status = 0x%x)\n", __func__, mci_cmd_value); + ERROR("%s: MCI command timeout (command status = 0x%x)\n", + __func__, mci_cmd_value); ret = 1; } @@ -280,16 +336,18 @@ int mci_write(int mci_idx, uint32_t cmd, uint32_t data) return mci_poll_command_completion(mci_idx, MCI_CMD_WRITE); } -/* Perform 3 configurations in one command: PCI mode, queues separation and cache bit */ +/* Perform 3 configurations in one command: PCI mode, + * queues separation and cache bit + */ static int mci_axi_set_pcie_mode(int mci_index) { uint32_t reg_data, ret = 1; debug_enter(); - /* This configuration makes MCI IP behave consistently with AXI protocol. - * It should be configured at one side only (for example localy at AP). - * The IP takes care of performing the same configurations at MCI on another - * side (for example remotely at CP). + /* This configuration makes MCI IP behave consistently with AXI protocol + * It should be configured at one side only (for example locally at AP). + * The IP takes care of performing the same configurations at MCI on + * another side (for example remotely at CP). */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_AXI_ACCESS_PCIE_MODE | @@ -297,7 +355,8 @@ static int mci_axi_set_pcie_mode(int mci_index) MCI_AXI_ACCESS_FORCE_POST_WR | MCI_AXI_ACCESS_DISABLE_CLK_GATING); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_AXI_ACCESS_DATA_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_AXI_ACCESS_DATA_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT | MCI_INDIRECT_CTRL_CIRCULAR_CMD); @@ -306,13 +365,15 @@ static int mci_axi_set_pcie_mode(int mci_index) if (mci_poll_command_completion(mci_index, MCI_CMD_WRITE) == 0) { /* Verify the PCIe mode selected */ mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT | MCI_INDIRECT_CTRL_READ_CMD); /* if read was completed, verify PCIe mode */ if (mci_poll_command_completion(mci_index, MCI_CMD_READ) == 0) { - reg_data = mci_mmio_read_32(MCI_WRITE_READ_DATA_REG(mci_index)); + reg_data = mci_mmio_read_32( + MCI_WRITE_READ_DATA_REG(mci_index)); if (reg_data & MCI_HB_CTRL_TX_CTRL_PCIE_MODE) ret = 0; } @@ -322,25 +383,29 @@ static int mci_axi_set_pcie_mode(int mci_index) return ret; } -/* Reduce sequence FIFO timer expiration threshold, including PIDI workaround */ +/* Reduce sequence FIFO timer expiration threshold */ static int mci_axi_set_fifo_thresh(int mci_index) { uint32_t reg_data, ret = 0; debug_enter(); - /* This configuration reduces sequence FIFO timer expiration threshold (to 0x7 instead of 0xA). - * In MCI 1.6 version this configuration prevents possible functional issues. + /* This configuration reduces sequence FIFO timer expiration threshold + * (to 0x7 instead of 0xA). + * In MCI 1.6 version this configuration prevents possible functional + * issues. * In version 1.82 the configuration prevents performance degradation */ /* Configure local AP side */ - /* PIDI Workaround for entering PIDI mode */ - reg_data = MCI_PHY_CTRL_PIDI_MODE | MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE - | MCI_PHY_CTRL_MCI_PHY_MODE_HOST - | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR; + reg_data = MCI_PHY_CTRL_PIDI_MODE | + MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Reduce the threshold */ @@ -348,40 +413,50 @@ static int mci_axi_set_fifo_thresh(int mci_index) MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_IHB_MODE_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_IHB_MODE_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Exit PIDI mode */ - reg_data = MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | MCI_PHY_CTRL_MCI_PHY_MODE_HOST - | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR; + reg_data = MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Configure remote CP side */ - /* PIDI Workaround for entering PIDI mode */ - reg_data = MCI_PHY_CTRL_PIDI_MODE | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR | + reg_data = MCI_PHY_CTRL_PIDI_MODE | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_CTRL_IHB_MODE_FWD_MOD); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_CTRL_IHB_MODE_FWD_MOD); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Reduce the threshold */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_IHB_MODE_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_IHB_MODE_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Exit PIDI mode */ - reg_data = MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE; + reg_data = MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR | + MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_CTRL_IHB_MODE_FWD_MOD); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_CTRL_IHB_MODE_FWD_MOD); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -405,7 +480,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_TX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_TX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -413,15 +489,18 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_TX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_TX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* AP DLO & DLI FIFO full threshold & Auto-Link enable (IHB_reg 0x8) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), - MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL | MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); + MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL | + MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -429,7 +508,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -437,7 +517,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_RX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_RX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -445,28 +526,31 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_RX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_RX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* AP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ + /* AP AR & AW maximum AXI outstanding request cfg (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(3) | MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(3)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* CP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ + /* CP AR & AW maximum AXI outstanding request cfg (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(0xB) | MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(0x11)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -476,8 +560,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) } /* configure MCI to allow read & write transactions to arrive at the same time. - * Without the below configuration, MCI won't sent response to CPU for transactions - * which arrived simultaneously and will lead to CPU hang. + * Without the below configuration, MCI won't sent response to CPU for + * transactions which arrived simultaneously and will lead to CPU hang. * The below will configure MCI to be able to pass transactions from/to CP/AP. */ static int mci_enable_simultaneous_transactions(int mci_index) @@ -491,46 +575,53 @@ static int mci_enable_simultaneous_transactions(int mci_index) MCI_DID_GLOBAL_ASSIGN_REQ_MCI_COUNT(2) | MCI_DID_GLOBAL_ASSIGN_REQ_HOPS_NUM(2)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_DID_GLOBAL_ASSIGNMENT_REQUEST_REG) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_DID_GLOBAL_ASSIGNMENT_REQUEST_REG) | MCI_INDIRECT_CTRL_ASSIGN_CMD); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* Assigning destination ID=3 to all transactions entering from AXI at AP */ + /* Assigning dest. ID=3 to all transactions entering from AXI at AP */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(1) | MCI_HB_CTRL_WIN0_DEST_ID(3)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* Assigning destination ID=1 to all transactions entering from AXI at CP */ + /* Assigning dest. ID=1 to all transactions entering from AXI at CP */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(1) | MCI_HB_CTRL_WIN0_DEST_ID(1)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* End address to all transactions entering from AXI at AP. This will lead to - * get match for any AXI address, and receive destination ID=3 + /* End address to all transactions entering from AXI at AP. + * This will lead to get match for any AXI address + * and receive destination ID=3 */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), 0xffffffff); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* End address to all transactions entering from AXI at CP. This will lead to - * get match for any AXI address, and receive destination ID=1 + /* End address to all transactions entering from AXI at CP. + * This will lead to get match for any AXI address + * and receive destination ID=1 */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), 0xffffffff); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -562,7 +653,8 @@ static _Bool mci_simulatenous_trans_missing(int mci_index) */ debug_enter(); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT | MCI_INDIRECT_CTRL_READ_CMD); @@ -571,7 +663,7 @@ static _Bool mci_simulatenous_trans_missing(int mci_index) reg = mci_mmio_read_32(MCI_WRITE_READ_DATA_REG(mci_index)); if (ret) - ERROR("Failed to verify if MCI simultaneous read/write was enabled\n"); + ERROR("Failed to verify MCI simultaneous read/write status\n"); debug_exit(); /* default ID assignment is 0, so if register doesn't contain zeros @@ -605,12 +697,14 @@ int mci_configure(int mci_index) */ if (mci_simulatenous_trans_missing(mci_index)) { VERBOSE("Enabling MCI simultaneous transaction\n"); - /* set MCI to support read/write transactions to arrive at the same time */ + /* set MCI to support read/write transactions + * to arrive at the same time + */ rval = mci_enable_simultaneous_transactions(mci_index); if (rval) - ERROR("Failed to set MCI for simultaneous read/write transactions\n"); + ERROR("Failed to set MCI simultaneous read/write\n"); } else - VERBOSE("Skipping MCI ID assignment - already done by bootrom\n"); + VERBOSE("Skip MCI ID assignment - already done by bootrom\n"); /* Configure MCI for more consistent behavior with AXI protocol */ rval = mci_axi_set_pcie_mode(mci_index); @@ -661,24 +755,30 @@ void mci_turn_link_down(void) /* Turn off auto-link */ cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(0)); + data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | + MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(0)); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to turn off auto-link\n"); /* Reset AP PHY */ - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_MAJOR | - MCI_PHY_CTRL_MCI_PHY_MODE_HOST | MCI_PHY_CTRL_MCI_PHY_RESET_CORE); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); + data = (MCI_PHY_CTRL_MCI_MINOR | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST | + MCI_PHY_CTRL_MCI_PHY_RESET_CORE); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to reset AP PHY\n"); /* Clear all status & CRC values */ - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_LINK_CRC_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_LINK_CRC_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); data = 0x0; mci_write(0, cmd, data); - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_STATUS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_STATUS_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); data = 0x0; rval = mci_write(0, cmd, data); if (rval) @@ -688,8 +788,10 @@ void mci_turn_link_down(void) mdelay(5); /* Un-reset AP PHY */ - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_PHY_MODE_HOST); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); + data = (MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to un-reset AP PHY\n"); @@ -706,7 +808,8 @@ void mci_turn_link_on(void) /* Turn on auto-link */ cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); + data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | + MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to turn on auto-link\n"); diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c index b3f5fa3b..075ca31f 100644 --- a/drivers/marvell/mochi/ap807_setup.c +++ b/drivers/marvell/mochi/ap807_setup.c @@ -5,6 +5,8 @@ * https://spdx.org/licenses */ +/* AP807 Marvell SoC driver */ + #include <ap_setup.h> #include <cache_llc.h> #include <ccu.h> @@ -12,15 +14,17 @@ #include <io_win.h> #include <mci.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) #define SMMU_sACR_PG_64K (1 << 16) -#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x3F0) +#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ + + 0x3F0) #define GSPMU_CPU_CONTROL (0x1 << 0) -#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x200) +#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ + + 0x200) #define CCU_SET_POC_OFFSET 5 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) @@ -49,7 +53,8 @@ /* Used for Units of AP-807 (e.g. SDIO and etc) */ #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) -#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + 0x4 * index) +#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ + 0x4 * index) enum axi_attr { AXI_SDIO_ATTR = 0, @@ -67,9 +72,11 @@ static void ap_sec_masters_access_en(uint32_t enable) */ reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); if (enable) - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | + SEC_IN_ACCESS_ENA_ALL_MASTERS); else - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, + reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); } static void setup_smmu(void) @@ -117,7 +124,8 @@ static void mci_remap_indirect_access_base(void) for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), - MVEBU_MCI_REG_BASE_REMAP(mci) >> MCI_REMAP_OFF_SHIFT); + MVEBU_MCI_REG_BASE_REMAP(mci) >> + MCI_REMAP_OFF_SHIFT); } static void ap807_axi_attr_init(void) @@ -134,27 +142,32 @@ static void ap807_axi_attr_init(void) case AXI_DFX_ATTR: continue; default: - /* Set Ax-Cache as cacheable, no allocate, modifiable, bufferable - * The values are different because Read & Write definition - * is different in Ax-Cache + /* Set Ax-Cache as cacheable, no allocate, modifiable, + * bufferable. + * The values are different because Read & Write + * definition is different in Ax-Cache */ data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_ARCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_ARCACHE_OFFSET; data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_AWCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_AWCACHE_OFFSET; /* Set Ax-Domain as Outer domain */ data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); } } - - return; } static void misc_soc_configurations(void) @@ -165,7 +178,7 @@ static void misc_soc_configurations(void) mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. - * Otherwise, upon WD timeout, the WD reset singal won't trigger reset + * Otherwise, upon WD timeout, the WD reset signal won't trigger reset */ reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); reg &= ~(WD_MASK_SYS_RST_OUT); @@ -205,7 +218,8 @@ static void ap807_dram_phy_access_config(void) /* Update DSS port access permission to DSS_PHY */ reg_val = mmio_read_32(DSS_SCR_REG); reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); - reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << DSS_PPROT_OFFS); + reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << + DSS_PPROT_OFFS); mmio_write_32(DSS_SCR_REG, reg_val); } diff --git a/drivers/marvell/mochi/ap810_setup.c b/drivers/marvell/mochi/ap810_setup.c index 6f1aadad..4252a49c 100644 --- a/drivers/marvell/mochi/ap810_setup.c +++ b/drivers/marvell/mochi/ap810_setup.c @@ -8,7 +8,7 @@ #include <ap810_setup.h> #include <debug.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define CCU_B_GIDACR(ap, stop) (MVEBU_A2_BANKED_STOP_BASE(ap, stop) + 0x34) diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 1fa7e4b0..10acbca3 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* AP806 Marvell SoC driver */ + #include <ap_setup.h> #include <ccu.h> #include <cache_llc.h> @@ -12,18 +14,21 @@ #include <io_win.h> #include <mci.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) #define SMMU_sACR_PG_64K (1 << 16) -#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x3F0) +#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x3F0) #define GSPMU_CPU_CONTROL (0x1 << 0) -#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x200) +#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x200) #define CCU_SET_POC_OFFSET 5 -#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + 0x90 + 4 * (win)) +#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x90 + 4 * (win)) #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) #define DVM_48BIT_VA_ENABLE (1 << 21) @@ -53,7 +58,8 @@ /* Used for Units of AP-806 (e.g. SDIO and etc) */ #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) -#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + 0x4 * index) +#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ + 0x4 * index) enum axi_attr { AXI_SDIO_ATTR = 0, @@ -71,9 +77,11 @@ static void apn_sec_masters_access_en(uint32_t enable) */ reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); if (enable) - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | + SEC_IN_ACCESS_ENA_ALL_MASTERS); else - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & + ~SEC_IN_ACCESS_ENA_ALL_MASTERS); } static void setup_smmu(void) @@ -102,7 +110,7 @@ static void ap806_generic_timer_init(void) static void apn806_errata_wa_init(void) { /* - * EERATA ID: RES-3033912 - Internal Address Space Init state causes + * ERRATA ID: RES-3033912 - Internal Address Space Init state causes * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and @@ -150,7 +158,8 @@ static void mci_remap_indirect_access_base(void) for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), - MVEBU_MCI_REG_BASE_REMAP(mci) >> MCI_REMAP_OFF_SHIFT); + MVEBU_MCI_REG_BASE_REMAP(mci) >> + MCI_REMAP_OFF_SHIFT); } static void apn806_axi_attr_init(void) @@ -168,27 +177,32 @@ static void apn806_axi_attr_init(void) case AXI_DFX_ATTR: continue; default: - /* Set Ax-Cache as cacheable, no allocate, modifiable, bufferable - * The values are different because Read & Write definition - * is different in Ax-Cache + /* Set Ax-Cache as cacheable, no allocate, modifiable, + * bufferable + * The values are different because Read & Write + * definition is different in Ax-Cache */ data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_ARCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_ARCACHE_OFFSET; data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_AWCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_AWCACHE_OFFSET; /* Set Ax-Domain as Outer domain */ data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); } } - - return; } static void dss_setup(void) @@ -202,7 +216,7 @@ void misc_soc_configurations(void) uint32_t reg; /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. - * Otherwise, upon WD timeout, the WD reset singal won't trigger reset + * Otherwise, upon WD timeout, the WD reset signal won't trigger reset */ reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); reg &= ~(WD_MASK_SYS_RST_OUT); @@ -239,8 +253,10 @@ void ap_init(void) misc_soc_configurations(); #if PALLADIUM - /* This code required to Palladium run only, BootROM init the generic timer - and BootROM isn't running for Palladium */ + /* This code required to Palladium run only, + * BootROM init the generic timer + * and BootROM isn't running for Palladium + */ ap806_generic_timer_init(); #endif } diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index a655af69..79a9c491 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* CP110 Marvell SoC driver */ + #include <amb_adec.h> #include <cp110_setup.h> #include <debug.h> @@ -65,88 +67,90 @@ static const struct icu_config icu_config = { */ /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */ -#define MVEBU_AXI_ATTR_OFFSET (0x441300) -#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + 0x4 * index) +#define MVEBU_AXI_ATTR_OFFSET (0x441300) +#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \ + 0x4 * index) /* AXI Protection bits */ -#define MVEBU_AXI_PROT_OFFSET (0x441200) +#define MVEBU_AXI_PROT_OFFSET (0x441200) /* AXI Protection regs */ -#define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? (MVEBU_AXI_PROT_OFFSET + 0x4 * index) : \ - (MVEBU_AXI_PROT_OFFSET + 0x18)) -#define MVEBU_AXI_PROT_REGS_NUM (6) - -#define MVEBU_SOC_CFGS_OFFSET (0x441900) -#define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + 0x4 * index) -#define MVEBU_SOC_CFG_REG_NUM (0) -#define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) +#define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \ + (MVEBU_AXI_PROT_OFFSET + \ + 0x4 * index) : \ + (MVEBU_AXI_PROT_OFFSET + 0x18)) +#define MVEBU_AXI_PROT_REGS_NUM (6) + +#define MVEBU_SOC_CFGS_OFFSET (0x441900) +#define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \ + 0x4 * index) +#define MVEBU_SOC_CFG_REG_NUM (0) +#define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) /* SATA3 MBUS to AXI regs */ -#define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) -#define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) +#define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) +#define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) /* SATA3 MBUS to AXI regs */ -#define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) +#define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) /* AXI to MBUS bridge registers */ -#define MVEBU_AMB_IP_OFFSET (0x13ff00) -#define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + (win * 0x8)) -#define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 -#define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) -#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 -#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) - -#define MVEBU_SAMPLE_AT_RESET_REG (0x440600) -#define SAR_PCIE1_CLK_CFG_OFFSET 31 -#define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET) -#define SAR_PCIE0_CLK_CFG_OFFSET 30 -#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) -#define SAR_I2C_INIT_EN_OFFSET 24 -#define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) +#define MVEBU_AMB_IP_OFFSET (0x13ff00) +#define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \ + (win * 0x8)) +#define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 +#define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \ + (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) +#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 +#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \ + (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) + +#define MVEBU_SAMPLE_AT_RESET_REG (0x440600) +#define SAR_PCIE1_CLK_CFG_OFFSET 31 +#define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET) +#define SAR_PCIE0_CLK_CFG_OFFSET 30 +#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) +#define SAR_I2C_INIT_EN_OFFSET 24 +#define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) /******************************************************************************* * PCIE clock buffer control ******************************************************************************/ -#define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) -#define PCIE1_REFCLK_BUFF_SOURCE 0x800 -#define PCIE0_REFCLK_BUFF_SOURCE 0x400 +#define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) +#define PCIE1_REFCLK_BUFF_SOURCE 0x800 +#define PCIE0_REFCLK_BUFF_SOURCE 0x400 /******************************************************************************* * MSS Device Push Set Register ******************************************************************************/ -#define MVEBU_CP_MSS_DPSHSR_REG (0x280040) -#define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 +#define MVEBU_CP_MSS_DPSHSR_REG (0x280040) +#define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 /******************************************************************************* * RTC Configuration ******************************************************************************/ -#define MVEBU_RTC_BASE (0x284000) -#define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) -#define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 -#define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 -#define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) -#define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) -#define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) -#define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) -#define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) -#define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) -#define MVEBU_RTC_NOMINAL_TIMING 0x2000 -#define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF -#define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) -#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) -#define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF -#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF -#define MVEBU_RTC_WRCLK_SETUP_OFFS 16 -#define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 -#define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 -#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) -#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF -#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F - -/* Errata */ -/* This bit disables internal HW fix for CP i2c init on REV A1 and later */ -#define MVEBU_CONF_I2C_INIT_SEL_BIT (4) -#define MVEBU_CONF_I2C_INIT_SEL_MASK (1 << MVEBU_CONF_I2C_INIT_SEL_BIT) +#define MVEBU_RTC_BASE (0x284000) +#define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) +#define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 +#define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 +#define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) +#define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) +#define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) +#define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) +#define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) +#define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) +#define MVEBU_RTC_NOMINAL_TIMING 0x2000 +#define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF +#define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) +#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) +#define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF +#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF +#define MVEBU_RTC_WRCLK_SETUP_OFFS 16 +#define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 +#define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 +#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) +#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF +#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F enum axi_attr { AXI_ADUNIT_ATTR = 0, @@ -195,8 +199,10 @@ static void cp110_errata_wa_init(uintptr_t base) uint32_t data; /* ERRATA GL-4076863: - * Reset value for global_secure_enable inputs must be changed from '1' to '0'. - * When asserted, only "secured" transactions can enter IHB configuration space. + * Reset value for global_secure_enable inputs must be changed + * from '1' to '0'. + * When asserted, only "secured" transactions can enter IHB + * configuration space. * However, blocking AXI transactions is performed by IOB. * Performing it also at IHB/HB complicates programming model. * @@ -257,7 +263,7 @@ static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id) while (stream_id_reg[i]) { if (i > MAX_STREAM_ID_PER_CP) { - NOTICE("Too many Stream IDs per CP, allocate only the first %d Stream IDs\n", + NOTICE("Only first %d (maximum) Stream IDs allocated\n", MAX_STREAM_ID_PER_CP); return; } @@ -295,22 +301,29 @@ static void cp110_axi_attr_init(uintptr_t base) case AXI_MSS_ATTR: continue; default: - /* Set Ax-Cache as cacheable, no allocate, modifiable, bufferable - * The values are different because Read & Write definition - * is different in Ax-Cache + /* Set Ax-Cache as cacheable, no allocate, modifiable, + * bufferable + * The values are different because Read & Write + * definition is different in Ax-Cache */ data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index)); data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_ARCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_ARCACHE_OFFSET; data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_AWCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_AWCACHE_OFFSET; /* Set Ax-Domain as Outer domain */ data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data); } } @@ -321,18 +334,21 @@ static void cp110_axi_attr_init(uintptr_t base) */ data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG); data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data); #endif /* Set all IO's AXI attribute to non-secure access. */ for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++) - mmio_write_32(base + MVEBU_AXI_PROT_REG(index), DOMAIN_SYSTEM_SHAREABLE); - - return; + mmio_write_32(base + MVEBU_AXI_PROT_REG(index), + DOMAIN_SYSTEM_SHAREABLE); } static void amb_bridge_init(uintptr_t base) @@ -341,8 +357,10 @@ static void amb_bridge_init(uintptr_t base) /* Open AMB bridge Window to Access COMPHY/MDIO registers */ reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0)); - reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); - reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET | 0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); + reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | + MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); + reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) | + (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg); } @@ -355,7 +373,8 @@ static void cp110_rtc_init(uintptr_t base) mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, MVEBU_RTC_WRCLK_SETUP_MASK, - MVEBU_RTC_WRCLK_SETUP_DEFAULT << MVEBU_RTC_WRCLK_SETUP_OFFS); + MVEBU_RTC_WRCLK_SETUP_DEFAULT << + MVEBU_RTC_WRCLK_SETUP_OFFS); mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, MVEBU_RTC_READ_OUTPUT_DELAY_MASK, @@ -369,7 +388,7 @@ static void cp110_rtc_init(uintptr_t base) MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) { /* Reset Test register */ mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0); - udelay(500000); + mdelay(500); /* Reset Time register */ mmio_write_32(base + MVEBU_RTC_TIME_REG, 0); @@ -377,7 +396,8 @@ static void cp110_rtc_init(uintptr_t base) /* Reset Status register */ mmio_write_32(base + MVEBU_RTC_STATUS_REG, - (MVEBU_RTC_STATUS_ALARM1_MASK | MVEBU_RTC_STATUS_ALARM2_MASK)); + (MVEBU_RTC_STATUS_ALARM1_MASK | + MVEBU_RTC_STATUS_ALARM2_MASK)); udelay(62); /* Turn off Int1 and Int2 sources & clear the Alarm count */ @@ -387,7 +407,8 @@ static void cp110_rtc_init(uintptr_t base) mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0); /* Setup nominal register access timing */ - mmio_write_32(base + MVEBU_RTC_CCR_REG, MVEBU_RTC_NOMINAL_TIMING); + mmio_write_32(base + MVEBU_RTC_CCR_REG, + MVEBU_RTC_NOMINAL_TIMING); /* Reset Time register */ mmio_write_32(base + MVEBU_RTC_TIME_REG, 0); @@ -395,7 +416,8 @@ static void cp110_rtc_init(uintptr_t base) /* Reset Status register */ mmio_write_32(base + MVEBU_RTC_STATUS_REG, - (MVEBU_RTC_STATUS_ALARM1_MASK | MVEBU_RTC_STATUS_ALARM2_MASK)); + (MVEBU_RTC_STATUS_ALARM1_MASK | + MVEBU_RTC_STATUS_ALARM2_MASK)); udelay(50); } } @@ -403,7 +425,8 @@ static void cp110_rtc_init(uintptr_t base) static void cp110_amb_adec_init(uintptr_t base) { /* enable AXI-MBUS by clearing "Bridge Windows Disable" */ - mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); + mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, + (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); /* configure AXI-MBUS windows for CP */ init_amb_adec(base); diff --git a/drivers/marvell/pcie-comphy-cp110.c b/drivers/marvell/pcie-comphy-cp110.c index 0ca667cb..e537a63d 100644 --- a/drivers/marvell/pcie-comphy-cp110.c +++ b/drivers/marvell/pcie-comphy-cp110.c @@ -4,11 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include "comphy.h" #include <debug.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> -#include "comphy.h" +#include <mvebu_def.h> #include "pci_ep.h" #define SD_ADDR(base, lane) (base + 0x1000 * lane) diff --git a/drivers/marvell/thermal.c b/drivers/marvell/thermal.c index c2703d7a..c7ceb929 100644 --- a/drivers/marvell/thermal.c +++ b/drivers/marvell/thermal.c @@ -1,10 +1,12 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* Driver for thermal unit located in Marvell ARMADA 8K and compatible SoCs */ + #include <debug.h> #include <thermal.h> diff --git a/include/drivers/marvell/a8k_i2c.h b/include/drivers/marvell/a8k_i2c.h index 6605902e..8a9abe8d 100644 --- a/include/drivers/marvell/a8k_i2c.h +++ b/include/drivers/marvell/a8k_i2c.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* This driver provides I2C support for Marvell A8K and compatible SoCs */ + #ifndef _A8K_I2C_H_ #define _A8K_I2C_H_ diff --git a/include/drivers/marvell/addr_map.h b/include/drivers/marvell/addr_map.h index c5407dfe..6b957a16 100644 --- a/include/drivers/marvell/addr_map.h +++ b/include/drivers/marvell/addr_map.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2017, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* Address map types for Marvell address translation unit drivers */ + #ifndef _ADDR_MAP_H_ #define _ADDR_MAP_H_ diff --git a/include/drivers/marvell/amb_adec.h b/include/drivers/marvell/amb_adec.h index 3fe87b19..087864a4 100644 --- a/include/drivers/marvell/amb_adec.h +++ b/include/drivers/marvell/amb_adec.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */ + #ifndef _AMB_ADEC_H_ #define _AMB_ADEC_H_ @@ -29,6 +31,6 @@ enum amb_attribute_ids { #define AMB_MAX_WIN_ID 7 -int init_amb_adec(uintptr_t); +int init_amb_adec(uintptr_t base); #endif /* _AMB_ADEC_H_ */ diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h index ea7298ce..9e417939 100644 --- a/include/drivers/marvell/cache_llc.h +++ b/include/drivers/marvell/cache_llc.h @@ -1,15 +1,19 @@ /* - * Copyright (C) 2015 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* LLC driver is the Last Level Cache (L3C) driver + * for Marvell SoCs in AP806, AP807, and AP810 + */ + #ifndef _CACHE_LLC_H_ #define _CACHE_LLC_H_ #define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100) -#define LLC_CACHE_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700) +#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700) #define L2X0_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C) #define L2X0_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC) #define L2X0_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC) @@ -24,15 +28,13 @@ #define LLC_WAY_MASK 0xFFFFFFFF #ifndef __ASSEMBLY__ -void llc_cache_sync(int); -void llc_flush_all(int); -void llc_clean_all(int); -void llc_inv_all(int); -void llc_disable(int); -void llc_enable(int, int excl_mode); -int llc_is_exclusive(int); -void llc_save(int); -void llc_resume(int); +void llc_cache_sync(int ap_index); +void llc_flush_all(int ap_index); +void llc_clean_all(int ap_index); +void llc_inv_all(int ap_index); +void llc_disable(int ap_index); +void llc_enable(int ap_index, int excl_mode); +int llc_is_exclusive(int ap_index); void llc_runtime_enable(int ap_index); #endif diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h index 36438881..ff30a76a 100644 --- a/include/drivers/marvell/ccu.h +++ b/include/drivers/marvell/ccu.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ + #ifndef _CCU_H_ #define _CCU_H_ @@ -13,16 +15,20 @@ #endif /* CCU registers definitions */ -#define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + (0x10 * win)) +#define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + \ + (0x10 * win)) #define CCU_TARGET_ID_OFFSET (8) #define CCU_TARGET_ID_MASK (0x7F) -#define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + (0x10 * win)) +#define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + \ + (0x10 * win)) #define CCU_WIN_ENA_WRITE_SECURE (0x1) #define CCU_WIN_ENA_READ_SECURE (0x2) -#define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + (0x10 * win)) -#define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + (0x10 * win)) +#define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + \ + (0x10 * win)) +#define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + \ + (0x10 * win)) #define CCU_WIN_GCR_OFFSET(ap) (MVEBU_CCU_BASE(ap) + 0xD0) #define CCU_GCR_TARGET_OFFSET (8) diff --git a/include/drivers/marvell/gwin.h b/include/drivers/marvell/gwin.h index f5c113dc..5dc9f244 100644 --- a/include/drivers/marvell/gwin.h +++ b/include/drivers/marvell/gwin.h @@ -1,16 +1,18 @@ /* - * Copyright (C) 2017, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* GWIN unit device driver for Marvell AP810 SoC */ + #ifndef _GWIN_H_ #define _GWIN_H_ #include <addr_map.h> -int init_gwin(int); +int init_gwin(int ap_index); void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size); void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size); diff --git a/include/drivers/marvell/i2c.h b/include/drivers/marvell/i2c.h index 7118547e..bd143852 100644 --- a/include/drivers/marvell/i2c.h +++ b/include/drivers/marvell/i2c.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef _I2C_H_ #define _I2C_H_ diff --git a/include/drivers/marvell/io_win.h b/include/drivers/marvell/io_win.h index 4ec2cc0e..4102a11a 100644 --- a/include/drivers/marvell/io_win.h +++ b/include/drivers/marvell/io_win.h @@ -1,16 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */ + #ifndef _IO_WIN_H_ #define _IO_WIN_H_ #include <addr_map.h> -int init_io_win(int); +int init_io_win(int ap_index); void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size); void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size); void iow_save_win_all(int ap_id); diff --git a/include/drivers/marvell/iob.h b/include/drivers/marvell/iob.h index adb8d4f3..9848c0ab 100644 --- a/include/drivers/marvell/iob.h +++ b/include/drivers/marvell/iob.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* IOW unit device driver for Marvell CP110 and CP115 SoCs */ + #ifndef _IOB_H_ #define _IOB_H_ @@ -22,7 +24,8 @@ enum target_ids_iob { IOB_MAX_TID }; -int init_iob(uintptr_t); -void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base, uintptr_t new_base); +int init_iob(uintptr_t base); +void iob_cfg_space_update(int ap_idx, int cp_idx, + uintptr_t base, uintptr_t new_base); #endif /* _IOB_H_ */ diff --git a/include/drivers/marvell/mci.h b/include/drivers/marvell/mci.h index 76122357..789b3b96 100644 --- a/include/drivers/marvell/mci.h +++ b/include/drivers/marvell/mci.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* MCI bus driver for Marvell ARMADA 8K and 8K+ SoCs */ + #ifndef _MCI_H_ #define _MCI_H_ diff --git a/include/drivers/marvell/mochi/ap_setup.h b/include/drivers/marvell/mochi/ap_setup.h index 1e6af6b7..41f2bac3 100644 --- a/include/drivers/marvell/mochi/ap_setup.h +++ b/include/drivers/marvell/mochi/ap_setup.h @@ -1,9 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +/* AP8xx Marvell SoC driver */ + #ifndef __AP_SETUP_H__ #define __AP_SETUP_H__ diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 032c829d..1c88980a 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -1,14 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#ifndef __PLAT_CP110_H__ -#define __PLAT_CP110_H__ + +/* CP110 Marvell SoC driver */ + +#ifndef __CP110_SETUP_H__ +#define __CP110_SETUP_H__ #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40) #define MVEBU_DEVICE_ID_OFFSET (0) @@ -47,4 +50,4 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_ble_init(uintptr_t cp110_base); -#endif /* __PLAT_CP110_H__ */ +#endif /* __CP110_SETUP_H__ */ diff --git a/include/drivers/marvell/thermal.h b/include/drivers/marvell/thermal.h index b8eb19d0..191f97ba 100644 --- a/include/drivers/marvell/thermal.h +++ b/include/drivers/marvell/thermal.h @@ -1,10 +1,12 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* Driver for thermal unit located in Marvell ARMADA 8K and compatible SoCs */ + #ifndef _THERMAL_H #define _THERMAL_H @@ -17,8 +19,8 @@ struct tsen_config { int tsen_ready; void *regs_base; /* thermal functionality */ - int (*ptr_tsen_probe)(struct tsen_config *); - int (*ptr_tsen_read)(struct tsen_config *, int *); + int (*ptr_tsen_probe)(struct tsen_config *cfg); + int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp); }; /* Thermal driver APIs */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 9f184706..f5ca2ee7 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -38,6 +38,13 @@ #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) /******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 + +#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) + +/******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 diff --git a/include/plat/marvell/a3700/common/armada_common.h b/include/plat/marvell/a3700/common/armada_common.h new file mode 100644 index 00000000..9fc46348 --- /dev/null +++ b/include/plat/marvell/a3700/common/armada_common.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __ARMADA_COMMON_H__ +#define __ARMADA_COMMON_H__ + +#include <io_addr_dec.h> +#include <stdint.h> + +int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size); + +#endif /* __ARMADA_COMMON_H__ */ diff --git a/include/plat/marvell/a3700/common/marvell_def.h b/include/plat/marvell/a3700/common/marvell_def.h index 326aa62a..5de69cc5 100644 --- a/include/plat/marvell/a3700/common/marvell_def.h +++ b/include/plat/marvell/a3700/common/marvell_def.h @@ -108,7 +108,8 @@ * Required platform porting definitions common to all MARVELL standard platforms **************************************************************************** */ -#define ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) /* * This macro defines the deepest retention state possible. A higher state diff --git a/include/plat/marvell/a3700/common/plat_config.h b/include/plat/marvell/a3700/common/plat_config.h deleted file mode 100644 index 36223855..00000000 --- a/include/plat/marvell/a3700/common/plat_config.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2016 Marvell International Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - * https://spdx.org/licenses - */ -#ifndef __PLAT_CONFIG_H__ -#define __PLAT_CONFIG_H__ - -#include <stdint.h> - -int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size); - -#endif /* __PLAT_CONFIG_H__ */ diff --git a/include/plat/marvell/a3700/common/plat_marvell.h b/include/plat/marvell/a3700/common/plat_marvell.h index 1d146f75..7825b7c5 100644 --- a/include/plat/marvell/a3700/common/plat_marvell.h +++ b/include/plat/marvell/a3700/common/plat_marvell.h @@ -19,7 +19,7 @@ extern const mmap_region_t plat_marvell_mmap[]; #define MARVELL_CASSERT_MMAP \ - CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \ + CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \ <= MAX_MMAP_REGIONS, \ assert_max_mmap_regions); @@ -72,7 +72,7 @@ int marvell_io_is_toc_valid(void); /* * PSCI functionality */ -void psci_arch_init(int); +void marvell_psci_arch_init(int idx); void plat_marvell_system_reset(void); /* diff --git a/include/plat/marvell/a8k-p/common/armada_common.h b/include/plat/marvell/a8k-p/common/armada_common.h new file mode 100644 index 00000000..5413f84a --- /dev/null +++ b/include/plat/marvell/a8k-p/common/armada_common.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __ARMADA_COMMON_H__ +#define __ARMADA_COMMON_H__ + +#include <amb_adec.h> +#include <io_win.h> +#include <iob.h> +#include <ccu.h> +#include <gwin.h> + +int marvell_get_mci_map(int ap_id, int cp_id); + +uint32_t marvell_get_io_win_gcr_target(int ap_idx); +uint32_t marvell_get_ccu_gcr_target(int ap_idx); + +/* + * The functions below are defined as Weak and may be overridden + * in specific Marvell standard platform + */ +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base); +int marvell_get_io_win_memory_map(int ap_idx, struct addr_map_win **win, + uint32_t *size); +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base); +int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win, + uint32_t *size); +int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, + uint32_t *size); + +#endif /* __ARMADA_COMMON_H__ */ diff --git a/include/plat/marvell/a8k-p/common/board_marvell_def.h b/include/plat/marvell/a8k-p/common/board_marvell_def.h index 871c1d8b..1d27cd68 100644 --- a/include/plat/marvell/a8k-p/common/board_marvell_def.h +++ b/include/plat/marvell/a8k-p/common/board_marvell_def.h @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #ifndef __BOARD_MARVELL_DEF_H__ #define __BOARD_MARVELL_DEF_H__ diff --git a/include/plat/marvell/a8k-p/common/marvell_def.h b/include/plat/marvell/a8k-p/common/marvell_def.h index 84196576..35fd55ec 100644 --- a/include/plat/marvell/a8k-p/common/marvell_def.h +++ b/include/plat/marvell/a8k-p/common/marvell_def.h @@ -1,14 +1,10 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #ifndef __MARVELL_DEF_H__ #define __MARVELL_DEF_H__ @@ -112,7 +108,8 @@ * Required platform porting definitions common to all MARVELL std. platforms **************************************************************************** */ -#define ADDR_SPACE_SIZE (1ull << 40) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) /* * This macro defines the deepest retention state possible. A higher state diff --git a/include/plat/marvell/a8k-p/common/plat_config.h b/include/plat/marvell/a8k-p/common/plat_config.h deleted file mode 100644 index a6551ad3..00000000 --- a/include/plat/marvell/a8k-p/common/plat_config.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2017 Marvell International Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - * https://spdx.org/licenses - */ - -#ifndef __BOARD_CONFIG_H__ -#define __BOARD_CONFIG_H__ - -#include <amb_adec.h> -#include <io_win.h> -#include <iob.h> -#include <ccu.h> -#include <gwin.h> - -int marvell_get_mci_map(int, int); - -uint32_t marvell_get_io_win_gcr_target(int); -uint32_t marvell_get_ccu_gcr_target(int); - -/* - * The functions below are defined as Weak and may be overridden - * in specific Marvell standard platform - */ -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base); -int marvell_get_io_win_memory_map(int, struct addr_map_win **win, uint32_t *size); -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base); -int marvell_get_ccu_memory_map(int, struct addr_map_win **win, uint32_t *size); -int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *size); - -#endif /* __BOARD_CONFIG_H__ */ diff --git a/include/plat/marvell/a8k-p/common/plat_marvell.h b/include/plat/marvell/a8k-p/common/plat_marvell.h index a56a1805..a8561d85 100644 --- a/include/plat/marvell/a8k-p/common/plat_marvell.h +++ b/include/plat/marvell/a8k-p/common/plat_marvell.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -86,7 +86,7 @@ int marvell_io_is_toc_valid(void); /* * PSCI functionality */ -void psci_arch_init(int); +void marvell_psci_arch_init(int idx); void plat_marvell_system_reset(void); /* @@ -105,7 +105,7 @@ void marvell_bl1_setup_mpps(void); #endif const mmap_region_t *plat_marvell_get_mmap(void); -void ble_prepare_exit(void); +void marvell_ble_prepare_exit(void); int jtag_init_ihb_dual_ap(void); int gic600_multi_chip_init(void); diff --git a/include/plat/marvell/a8k-p/common/plat_pm_trace.h b/include/plat/marvell/a8k-p/common/plat_pm_trace.h index 35275ba9..69048d56 100644 --- a/include/plat/marvell/a8k-p/common/plat_pm_trace.h +++ b/include/plat/marvell/a8k-p/common/plat_pm_trace.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/include/plat/marvell/a8k/common/plat_config.h b/include/plat/marvell/a8k/common/armada_common.h index 405dafcf..7356a67a 100644 --- a/include/plat/marvell/a8k/common/plat_config.h +++ b/include/plat/marvell/a8k/common/armada_common.h @@ -1,17 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#ifndef __BOARD_CONFIG_H__ -#define __BOARD_CONFIG_H__ + +#ifndef __ARMADA_COMMON_H__ +#define __ARMADA_COMMON_H__ #include <amb_adec.h> #include <io_win.h> #include <iob.h> #include <ccu.h> -#include <pci_ep.h> /* * This struct supports skip image request @@ -64,17 +64,22 @@ struct skip_image { * type: the method used to power off the SoC * cfg: * PMIC_GPIO: - * pin_count: current GPIO pin number used for toggling the GPIO to notify PMIC - * info: hold the GPIOs information, CP GPIO should be used and the GPIOs should be within - * same GPIO register - * step_count: current step number to toggle the GPIO for PMIC - * seq: GPIO toggling values in sequence, each bit represents a GPIO - * for exmaple, bit0 represents first GPIO used for toggling the GPIO - * the last step is used to trigger the power off finnally - * delay_ms: transition interval for the GPIO setting to take effect in unit of ms + * pin_count: current GPIO pin number used for toggling the signal for + * notifying external PMIC + * info: holds the GPIOs information, CP GPIO should be used and + * all GPIOs should be within same GPIO config. register + * step_count: current step number to toggle the GPIO for PMIC + * seq: GPIO toggling values in sequence, each bit represents a GPIO. + * For example, bit0 represents first GPIO used for toggling + * the GPIO the last step is used to trigger the power off + * signal + * delay_ms: transition interval for the GPIO setting to take effect + * in unit of ms */ -#define PMIC_GPIO_MAX_NUMBER 8 /* Max GPIO number used to notify PMIC to power off the SoC */ -#define PMIC_GPIO_MAX_TOGGLE_STEP 8 /* Max GPIO toggling steps in sequence to power off the SoC */ +/* Max GPIO number used to notify PMIC to power off the SoC */ +#define PMIC_GPIO_MAX_NUMBER 8 +/* Max GPIO toggling steps in sequence to power off the SoC */ +#define PMIC_GPIO_MAX_TOGGLE_STEP 8 enum gpio_output_state { GPIO_LOW = 0, @@ -103,17 +108,21 @@ struct power_off_method { }; int marvell_gpio_config(void); -uint32_t marvell_get_io_win_gcr_target(int); -uint32_t marvell_get_ccu_gcr_target(int); +uint32_t marvell_get_io_win_gcr_target(int ap_idx); +uint32_t marvell_get_ccu_gcr_target(int ap_idx); /* * The functions below are defined as Weak and may be overridden * in specific Marvell standard platform */ -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base); -int marvell_get_io_win_memory_map(int, struct addr_map_win **win, uint32_t *size); -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base); -int marvell_get_ccu_memory_map(int, struct addr_map_win **win, uint32_t *size); +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base); +int marvell_get_io_win_memory_map(int ap_idx, struct addr_map_win **win, + uint32_t *size); +int marvell_get_iob_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base); +int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win, + uint32_t *size); -#endif /* __BOARD_CONFIG_H__ */ +#endif /* __ARMADA_COMMON_H__ */ diff --git a/include/plat/marvell/a8k/common/board_marvell_def.h b/include/plat/marvell/a8k/common/board_marvell_def.h index 823d5589..b1054db2 100644 --- a/include/plat/marvell/a8k/common/board_marvell_def.h +++ b/include/plat/marvell/a8k/common/board_marvell_def.h @@ -1,38 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ + #ifndef __BOARD_MARVELL_DEF_H__ #define __BOARD_MARVELL_DEF_H__ diff --git a/include/plat/marvell/a8k/common/marvell_def.h b/include/plat/marvell/a8k/common/marvell_def.h index 5bd2c11a..538209e8 100644 --- a/include/plat/marvell/a8k/common/marvell_def.h +++ b/include/plat/marvell/a8k/common/marvell_def.h @@ -1,38 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ + #ifndef __MARVELL_DEF_H__ #define __MARVELL_DEF_H__ @@ -136,7 +108,8 @@ * Required platform porting definitions common to all MARVELL std. platforms *****************************************************************************/ -#define ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) /* * This macro defines the deepest retention state possible. A higher state @@ -155,7 +128,6 @@ #define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) - /* * Some data must be aligned on the biggest cache line size in the platform. * This is known only to the platform as it might have a combination of diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h index 22d844a4..265f33c4 100644 --- a/include/plat/marvell/a8k/common/plat_marvell.h +++ b/include/plat/marvell/a8k/common/plat_marvell.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __PLAT_MARVELL_H__ #define __PLAT_MARVELL_H__ @@ -49,7 +50,7 @@ int marvell_check_mpidr(u_register_t mpidr); /* BLE utility functions */ int ble_plat_setup(int *skip); -void plat_dram_update_topology(void); +void plat_marvell_dram_update_topology(void); void ble_plat_pcie_ep_setup(void); struct pci_hw_cfg *plat_get_pcie_hw_data(void); @@ -73,13 +74,13 @@ void marvell_bl31_plat_runtime_setup(void); void marvell_bl31_plat_arch_setup(void); /* Power management config to power off the SoC */ -void *plat_get_pm_cfg(void); +void *plat_marvell_get_pm_cfg(void); /* Check if MSS AP CM3 firmware contains PM support */ _Bool is_pm_fw_running(void); /* Bootrom image recovery utility functions */ -void *plat_get_skip_image_data(void); +void *plat_marvell_get_skip_image_data(void); /* FIP TOC validity check */ int marvell_io_is_toc_valid(void); @@ -87,7 +88,7 @@ int marvell_io_is_toc_valid(void); /* * PSCI functionality */ -void psci_arch_init(int); +void marvell_psci_arch_init(int ap_idx); void plat_marvell_system_reset(void); /* @@ -105,8 +106,8 @@ void marvell_bl1_setup_mpps(void); #endif const mmap_region_t *plat_marvell_get_mmap(void); -void ble_prepare_exit(void); -void exit_bootrom(uintptr_t); +void marvell_ble_prepare_exit(void); +void marvell_exit_bootrom(uintptr_t base); int plat_marvell_early_cpu_powerdown(void); #endif /* __PLAT_MARVELL_H__ */ diff --git a/include/plat/marvell/a8k/common/plat_pm_trace.h b/include/plat/marvell/a8k/common/plat_pm_trace.h index f82e2b2c..0878959c 100644 --- a/include/plat/marvell/a8k/common/plat_pm_trace.h +++ b/include/plat/marvell/a8k/common/plat_pm_trace.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __PLAT_PM_TRACE_H #define __PLAT_PM_TRACE_H @@ -80,7 +81,7 @@ typedef void (*core_trace_func)(unsigned int); extern core_trace_func funcTbl[PLATFORM_CORE_COUNT]; -#define PM_TRACE(trace) funcTbl[plat_my_core_pos()](trace); +#define PM_TRACE(trace) funcTbl[plat_my_core_pos()](trace) #else diff --git a/include/plat/marvell/common/aarch64/cci_macros.S b/include/plat/marvell/common/aarch64/cci_macros.S index 754da98b..d6080cfd 100644 --- a/include/plat/marvell/common/aarch64/cci_macros.S +++ b/include/plat/marvell/common/aarch64/cci_macros.S @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __CCI_MACROS_S__ #define __CCI_MACROS_S__ diff --git a/include/plat/marvell/common/aarch64/marvell_macros.S b/include/plat/marvell/common/aarch64/marvell_macros.S index 0a3e3798..0102af04 100644 --- a/include/plat/marvell/common/aarch64/marvell_macros.S +++ b/include/plat/marvell/common/aarch64/marvell_macros.S @@ -1,40 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ARM_MACROS_S__ -#define __ARM_MACROS_S__ + +#ifndef __MARVELL_MACROS_S__ +#define __MARVELL_MACROS_S__ #include <cci.h> #include <gic_common.h> @@ -159,4 +131,4 @@ cci_iface_regs: .endm -#endif /* __ARM_MACROS_S__ */ +#endif /* __MARVELL_MACROS_S__ */ diff --git a/include/plat/marvell/common/plat_private.h b/include/plat/marvell/common/marvell_plat_priv.h index 7b7e2917..c1dad0ef 100644 --- a/include/plat/marvell/common/plat_private.h +++ b/include/plat/marvell/common/marvell_plat_priv.h @@ -1,16 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - -#ifndef __PLAT_PRIVATE_H__ -#define __PLAT_PRIVATE_H__ -/******************************************************************************* +#ifndef __MARVELL_PLAT_PRIV_H__ +#define __MARVELL_PLAT_PRIV_H__ + +#include <utils.h> + +/***************************************************************************** * Function and variable prototypes - ******************************************************************************/ + ***************************************************************************** + */ void plat_delay_timer_init(void); uint64_t mvebu_get_dram_size(uint64_t ap_base_addr); @@ -28,4 +31,4 @@ void plat_marvell_gic_irq_restore(void); void plat_marvell_gic_irq_pcpu_save(void); void plat_marvell_gic_irq_pcpu_restore(void); -#endif /* __PLAT_PRIVATE_H__ */ +#endif /* __MARVELL_PLAT_PRIV_H__ */ diff --git a/include/plat/marvell/common/marvell_pm.h b/include/plat/marvell/common/marvell_pm.h index b2632f74..2817a462 100644 --- a/include/plat/marvell/common/marvell_pm.h +++ b/include/plat/marvell/common/marvell_pm.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef _MARVELL_PM_H_ #define _MARVELL_PM_H_ @@ -12,10 +12,15 @@ #define MVEBU_MAILBOX_SUSPEND_STATE 0xb007de7c /* Mailbox entry indexes */ -#define MBOX_IDX_MAGIC 0 /* Magic number for validity check */ -#define MBOX_IDX_SEC_ADDR 1 /* Recovery from suspend entry point */ -#define MBOX_IDX_SUSPEND_MAGIC 2 /* Suspend state magic number */ -#define MBOX_IDX_ROM_EXIT_ADDR 3 /* Recovery jump address for ROM bypass */ -#define MBOX_IDX_START_CNT 4 /* BLE execution start counter value */ +/* Magic number for validity check */ +#define MBOX_IDX_MAGIC 0 +/* Recovery from suspend entry point */ +#define MBOX_IDX_SEC_ADDR 1 +/* Suspend state magic number */ +#define MBOX_IDX_SUSPEND_MAGIC 2 +/* Recovery jump address for ROM bypass */ +#define MBOX_IDX_ROM_EXIT_ADDR 3 +/* BLE execution start counter value */ +#define MBOX_IDX_START_CNT 4 #endif /* _MARVELL_PM_H_ */ diff --git a/include/plat/marvell/common/mvebu.h b/include/plat/marvell/common/mvebu.h index fe55867e..a20e538e 100644 --- a/include/plat/marvell/common/mvebu.h +++ b/include/plat/marvell/common/mvebu.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef _MVEBU_H_ #define _MVEBU_H_ @@ -20,7 +20,8 @@ (((number) + (align)) & ~((align)-1)) : (number)) /* Macro for testing whether a number is a power of 2. Positive if so */ -#define IS_POWER_OF_2(number) (number != 0 && ((number & (number - 1)) == 0)) +#define IS_POWER_OF_2(number) ((number) != 0 && \ + (((number) & ((number) - 1)) == 0)) /* * Macro for ronding up to next power of 2 @@ -28,7 +29,8 @@ * then you can shift it left and get number which power of 2 * Note: this Macro is for 32 bit number */ -#define ROUND_UP_TO_POW_OF_2(number) (1 << (32 - __builtin_clz(number - 1))) +#define ROUND_UP_TO_POW_OF_2(number) (1 << \ + (32 - __builtin_clz((number) - 1))) #define _1MB_ (1024ULL*1024ULL) #define _1GB_ (_1MB_*1024ULL) diff --git a/plat/marvell/a3700/a3700/board/pm_src.c b/plat/marvell/a3700/a3700/board/pm_src.c index 1c4958c6..bc48ce8c 100644 --- a/plat/marvell/a3700/a3700/board/pm_src.c +++ b/plat/marvell/a3700/a3700/board/pm_src.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/a3700/plat_def.h b/plat/marvell/a3700/a3700/mvebu_def.h index 6a1ff0fa..c58f06bb 100644 --- a/plat/marvell/a3700/a3700/plat_def.h +++ b/plat/marvell/a3700/a3700/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * - * SPDX-License-Identifier: BSD-3-Clause + * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a3700/a3700/plat_bl31_setup.c b/plat/marvell/a3700/a3700/plat_bl31_setup.c index 1e813f32..a37af930 100644 --- a/plat/marvell/a3700/a3700/plat_bl31_setup.c +++ b/plat/marvell/a3700/a3700/plat_bl31_setup.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <a3700_dram_cs.h> +#include <armada_common.h> #include <dram_win.h> #include <io_addr_dec.h> #include <mmio.h> -#include <plat_config.h> +#include <marvell_plat_priv.h> #include <plat_marvell.h> -#include <plat_private.h> #include <sys_info.h> /* This function passes DRAM cpu decode window information in ATF to sys info */ @@ -47,7 +48,8 @@ static void marvell_bl31_mpp_init(void) * And anyway, this bit value should be 1 in all modes, * so here we does not judge boot mode and set this bit to 1 always. */ - mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); + mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, + 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); } /* This function overruns the same function in marvell_bl31_setup.c */ diff --git a/plat/marvell/a3700/a3700/platform.mk b/plat/marvell/a3700/a3700/platform.mk index d2316f67..4f7ac08c 100644 --- a/plat/marvell/a3700/a3700/platform.mk +++ b/plat/marvell/a3700/a3700/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk index d963284a..54f8bdaa 100644 --- a/plat/marvell/a3700/common/a3700_common.mk +++ b/plat/marvell/a3700/common/a3700_common.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses @@ -36,16 +36,19 @@ endif #MARVELL_SECURE_BOOT TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl -# WTMI_IMG is used to specify the customized RTOS image runing over CM3 processor. By default, it -# points to a baremetal binary of fuse programming in A3700_utils. +# WTMI_IMG is used to specify the customized RTOS image runing over +# Service CPU (CM3 processor). By the default, it points to a +# baremetal binary of fuse programming in A3700_utils. WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin -# WTMI_SYSINIT_IMG is used for the system early initialization, such as AVS settings, clock-tree -# setup and dynamic DDR PHY training. After the initialization is done, this image will be wiped out +# WTMI_SYSINIT_IMG is used for the system early initialization, +# such as AVS settings, clock-tree setup and dynamic DDR PHY training. +# After the initialization is done, this image will be wiped out # from the memory and CM3 will continue with RTOS image or other application. WTMI_SYSINIT_IMG := $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin -# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG) and sys-init image (WTMI_SYSINIT_IMG). +# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG) +# and sys-init image (WTMI_SYSINIT_IMG). WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin WTMI_ENC_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi-enc.bin @@ -84,31 +87,31 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ ATF_INCLUDES := -Iinclude/common/tbbr \ -Iinclude/drivers -PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \ - -I$(PLAT_COMMON_BASE)/include \ - -I$(PLAT_INCLUDE_BASE)/common \ - -I$(MARVELL_DRV_BASE)/uart \ - -I$/drivers/arm/gic/common/ \ +PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \ + -I$(PLAT_COMMON_BASE)/include \ + -I$(PLAT_INCLUDE_BASE)/common \ + -I$(MARVELL_DRV_BASE)/uart \ + -I$/drivers/arm/gic/common/ \ $(ATF_INCLUDES) -PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \ - drivers/console/aarch64/console.S \ - plat/marvell/common/marvell_cci.c \ +PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \ + drivers/console/aarch64/console.S \ + plat/marvell/common/marvell_cci.c \ $(MARVELL_DRV_BASE)/uart/a3700_console.S -BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ +BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ lib/cpus/aarch64/cortex_a53.S BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ + $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ $(PLAT_COMMON_BASE)/plat_pm.c \ $(PLAT_COMMON_BASE)/a3700_dram_cs.c \ $(PLAT_COMMON_BASE)/dram_win.c \ $(PLAT_COMMON_BASE)/io_addr_dec.c \ - $(PLAT_COMMON_BASE)/marvell_plat_config.c \ - $(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \ + $(PLAT_COMMON_BASE)/marvell_plat_config.c \ + $(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \ plat/marvell/common/sys_info.c \ plat/marvell/common/marvell_gicv3.c \ $(MARVELL_GIC_SOURCES) \ @@ -154,11 +157,13 @@ ifeq ($(MARVELL_SECURE_BOOT),1) @echo -e "\t Secure boot. Encrypting wtmi and boot-image \n"; @echo -e "\t=======================================================\n"; @truncate -s %16 $(WTMI_MULTI_IMG) - @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) -out $(WTMI_ENC_IMG) \ + @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) \ + -out $(WTMI_ENC_IMG) \ -K `cat $(IMAGESPATH)/aes-256.txt` -k 0 -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p @truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE); - @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ + @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \ + -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ -K `cat $(IMAGESPATH)/aes-256.txt` -k 0 -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p endif diff --git a/plat/marvell/a3700/common/a3700_dram_cs.c b/plat/marvell/a3700/common/a3700_dram_cs.c index 400eea06..d894f1d5 100644 --- a/plat/marvell/a3700/common/a3700_dram_cs.c +++ b/plat/marvell/a3700/common/a3700_dram_cs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -76,13 +76,18 @@ static struct dram_cs_addr_len_to_size dram_cs_addr_len_to_size_map[] = { {0x1A, TB_2_MB(4) } }; -static int marvell_dram_cs_get_size_by_addr_len(uint32_t addr_len_value, uint32_t *size_mbytes) +static int marvell_dram_cs_get_size_by_addr_len(uint32_t addr_len_value, + uint32_t *size_mbytes) { int i; - for (i = 0; i < sizeof(dram_cs_addr_len_to_size_map)/sizeof(struct dram_cs_addr_len_to_size); i++) { - if (dram_cs_addr_len_to_size_map[i].addr_len_value == addr_len_value) { - *size_mbytes = dram_cs_addr_len_to_size_map[i].size_mbytes; + for (i = 0; i < sizeof(dram_cs_addr_len_to_size_map)/ + sizeof(struct dram_cs_addr_len_to_size); i++) { + + if (dram_cs_addr_len_to_size_map[i].addr_len_value == + addr_len_value) { + *size_mbytes = + dram_cs_addr_len_to_size_map[i].size_mbytes; return 0; } } @@ -121,9 +126,11 @@ int marvell_get_dram_cs_base_size(uint32_t cs_num, if (!(cs_mmap_reg & MVEBU_CS_MMAP_ENABLE)) return -ENODEV; - *base_low = (cs_mmap_reg & MVEBU_CS_MMAP_START_ADDR_LOW_MASK) >> MVEBU_CS_MMAP_START_ADDR_LOW_OFFS; + *base_low = (cs_mmap_reg & MVEBU_CS_MMAP_START_ADDR_LOW_MASK) >> + MVEBU_CS_MMAP_START_ADDR_LOW_OFFS; *base_high = mmio_read_32(MVEBU_CS_MMAP_HIGH(cs_num)); - area_len = (cs_mmap_reg & MVEBU_CS_MMAP_AREA_LEN_MASK) >> MVEBU_CS_MMAP_AREA_LEN_OFFS; + area_len = (cs_mmap_reg & MVEBU_CS_MMAP_AREA_LEN_MASK) >> + MVEBU_CS_MMAP_AREA_LEN_OFFS; if (marvell_dram_cs_get_size_by_addr_len(area_len, size_mbytes)) return -EFAULT; diff --git a/plat/marvell/a3700/common/aarch64/a3700_common.c b/plat/marvell/a3700/common/aarch64/a3700_common.c index 07a3a2f6..e7840094 100644 --- a/plat/marvell/a3700/common/aarch64/a3700_common.c +++ b/plat/marvell/a3700/common/aarch64/a3700_common.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/aarch64/plat_helpers.S b/plat/marvell/a3700/common/aarch64/plat_helpers.S index 9da72ad3..c132dcdd 100644 --- a/plat/marvell/a3700/common/aarch64/plat_helpers.S +++ b/plat/marvell/a3700/common/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -27,7 +27,7 @@ endfunc plat_secondary_cold_boot_setup /* --------------------------------------------------------------------- * unsigned long plat_get_my_entrypoint (void); * - * Main job of this routine is to distinguish between a cold and warm boot + * Main job of this routine is to distinguish between cold and warm boot * For a cold boot, return 0. * For a warm boot, read the mailbox and return the address it contains. * A magic number is placed before entrypoint to avoid mistake caused by @@ -35,16 +35,19 @@ endfunc plat_secondary_cold_boot_setup * --------------------------------------------------------------------- */ func plat_get_my_entrypoint - mov_imm x0, PLAT_MARVELL_MAILBOX_BASE /* Read first word and compare it with magic num */ - ldr x1, [x0] + /* Read first word and compare it with magic num */ + mov_imm x0, PLAT_MARVELL_MAILBOX_BASE + ldr x1, [x0] mov_imm x2, PLAT_MARVELL_MAILBOX_MAGIC_NUM - cmp x1, x2 - beq entrypoint /* If compare failed, return 0, i.e. cold boot */ - mov x0, #0 + cmp x1, x2 + /* If compare failed, return 0, i.e. cold boot */ + beq entrypoint + mov x0, #0 ret entrypoint: - add x0, x0, #8 /* Second word contains the jump address */ - ldr x0, [x0] + /* Second word contains the jump address */ + add x0, x0, #8 + ldr x0, [x0] ret endfunc plat_get_my_entrypoint diff --git a/plat/marvell/a3700/common/dram_win.c b/plat/marvell/a3700/common/dram_win.c index e623362e..3ffc98cd 100644 --- a/plat/marvell/a3700/common/dram_win.c +++ b/plat/marvell/a3700/common/dram_win.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -134,7 +134,8 @@ void dram_win_map_build(struct dram_win_map *win_map) memset(win_map, 0, sizeof(struct dram_win_map)); for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) { ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); - target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> CPU_DEC_CR_WIN_TARGET_OFFS; + target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> + CPU_DEC_CR_WIN_TARGET_OFFS; enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE; /* Ignore invalid and non-dram windows*/ if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM)) @@ -144,15 +145,19 @@ void dram_win_map_build(struct dram_win_map *win_map) base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); size_reg = mmio_read_32(CPU_DEC_WIN_SIZE_REG(win_id)); /* Base reg [15:0] corresponds to transaction address [39:16] */ - win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> CPU_DEC_BR_BASE_OFFS; + win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> + CPU_DEC_BR_BASE_OFFS; win->base_addr *= CPU_DEC_CR_WIN_SIZE_ALIGNMENT; /* - * Size reg [15:0] is programmed from LSB to MSB as a sequence of 1s followed by a sequence of 0s, - * and the number of 1s specifies the size of the window in 64 KB granularity, + * Size reg [15:0] is programmed from LSB to MSB as a sequence + * of 1s followed by a sequence of 0s and the number of 1s + * specifies the size of the window in 64 KB granularity, * for example, a value of 00FFh specifies 256 x 64 KB = 16 MB */ - win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> CPU_DEC_CR_WIN_SIZE_OFFS; - win->win_size = (win->win_size + 1) * CPU_DEC_CR_WIN_SIZE_ALIGNMENT; + win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> + CPU_DEC_CR_WIN_SIZE_OFFS; + win->win_size = (win->win_size + 1) * + CPU_DEC_CR_WIN_SIZE_ALIGNMENT; win_map->dram_win_num++; } @@ -174,13 +179,17 @@ static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) return; /* Set Base Register */ - base_reg = (uint32_t)(win_cfg->base_addr / CPU_DEC_CR_WIN_SIZE_ALIGNMENT); + base_reg = (uint32_t)(win_cfg->base_addr / + CPU_DEC_CR_WIN_SIZE_ALIGNMENT); base_reg <<= CPU_DEC_BR_BASE_OFFS; base_reg &= CPU_DEC_BR_BASE_MASK; mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); - /* Set Remap Register with the same value as the <Base> field in Base Register */ - remap_reg = (uint32_t)(win_cfg->remap_addr / CPU_DEC_CR_WIN_SIZE_ALIGNMENT); + /* Set Remap Register with the same value + * as the <Base> field in Base Register + */ + remap_reg = (uint32_t)(win_cfg->remap_addr / + CPU_DEC_CR_WIN_SIZE_ALIGNMENT); remap_reg <<= CPU_DEC_RLR_REMAP_LOW_OFFS; remap_reg &= CPU_DEC_RLR_REMAP_LOW_MASK; mmio_write_32(CPU_DEC_REMAP_LOW_REG(win_id), remap_reg); @@ -200,10 +209,12 @@ static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) void cpu_wins_init(void) { - uint32_t cfg_idx, win_id, cs_id, base_low, base_high, size_mbytes, total_mbytes = 0; + uint32_t cfg_idx, win_id, cs_id; + uint32_t base_low, base_high, size_mbytes, total_mbytes = 0; for (cs_id = 0; cs_id < MVEBU_MAX_CS_MMAP_NUM; cs_id++) - if (!marvell_get_dram_cs_base_size(cs_id, &base_low, &base_high, &size_mbytes)) + if (!marvell_get_dram_cs_base_size(cs_id, &base_low, + &base_high, &size_mbytes)) total_mbytes += size_mbytes; if (total_mbytes <= 2048) @@ -211,7 +222,9 @@ void cpu_wins_init(void) else cfg_idx = CPU_WIN_CONFIG_DRAM_4GB; - /* Window 0 is configured always for DRAM in tim header already, no need to configure it again here */ + /* Window 0 is configured always for DRAM in tim header + * already, no need to configure it again here + */ for (win_id = 1; win_id < MV_CPU_WIN_NUM; win_id++) cpu_win_set(win_id, &mv_cpu_wins[cfg_idx][win_id]); } diff --git a/plat/marvell/a3700/common/include/a3700_dram_cs.h b/plat/marvell/a3700/common/include/a3700_dram_cs.h index 6a9edaf4..4ce64dec 100644 --- a/plat/marvell/a3700/common/include/a3700_dram_cs.h +++ b/plat/marvell/a3700/common/include/a3700_dram_cs.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_A3700_DRAM_CS_H__ #define __MVEBU_A3700_DRAM_CS_H__ diff --git a/plat/marvell/a3700/common/include/a3700_plat_def.h b/plat/marvell/a3700/common/include/a3700_plat_def.h index 05c71351..e145c532 100644 --- a/plat/marvell/a3700/common/include/a3700_plat_def.h +++ b/plat/marvell/a3700/common/include/a3700_plat_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/include/a3700_pm.h b/plat/marvell/a3700/common/include/a3700_pm.h index 3ab7c736..a3dac274 100644 --- a/plat/marvell/a3700/common/include/a3700_pm.h +++ b/plat/marvell/a3700/common/include/a3700_pm.h @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_A3700_PM_H__ #define __MVEBU_A3700_PM_H__ diff --git a/plat/marvell/a3700/common/include/dram_win.h b/plat/marvell/a3700/common/include/dram_win.h index 8191b298..4537f916 100644 --- a/plat/marvell/a3700/common/include/dram_win.h +++ b/plat/marvell/a3700/common/include/dram_win.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef _DRAM_WIN_H_ #define _DRAM_WIN_H_ diff --git a/plat/marvell/a3700/common/include/io_addr_dec.h b/plat/marvell/a3700/common/include/io_addr_dec.h index d77e9c18..2e4183cd 100644 --- a/plat/marvell/a3700/common/include/io_addr_dec.h +++ b/plat/marvell/a3700/common/include/io_addr_dec.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef _IO_ADDR_DEC_H_ #define _IO_ADDR_DEC_H_ @@ -23,10 +24,15 @@ */ struct dec_win_config { uint32_t dec_reg_base; /* IO address decoder register base address */ - uint32_t win_attr; /* IO address decoder windows attributes */ - uint32_t max_dram_win; /* How many configurable dram decoder windows that this unit has; */ - uint32_t max_remap; /* The decoder windows number including remapping that this unit has */ - uint32_t win_offset; /* The offset between continuous decode windows within the same unit, typically 0x10 */ + uint32_t win_attr; /* IO address decoder windows attributes */ + /* How many configurable dram decoder windows that this unit has; */ + uint32_t max_dram_win; + /* The decoder windows number including remapping that this unit has */ + uint32_t max_remap; + /* The offset between continuous decode windows + * within the same unit, typically 0x10 + */ + uint32_t win_offset; }; struct dram_win { @@ -53,7 +59,9 @@ struct dram_win_map { * * @return: 0 on success and others on failure */ -int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *io_dec_config, uint32_t io_unit_num); +int init_io_addr_dec(struct dram_win_map *dram_wins_map, + struct dec_win_config *io_dec_config, + uint32_t io_unit_num); #endif /* _IO_ADDR_DEC_H_ */ diff --git a/plat/marvell/a3700/common/include/plat_macros.S b/plat/marvell/a3700/common/include/plat_macros.S index af084882..12f0d6f9 100644 --- a/plat/marvell/a3700/common/include/plat_macros.S +++ b/plat/marvell/a3700/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h index 9e90e0dc..7da1fa14 100644 --- a/plat/marvell/a3700/common/include/platform_def.h +++ b/plat/marvell/a3700/common/include/platform_def.h @@ -8,7 +8,7 @@ #define __PLATFORM_DEF_H__ #include <board_marvell_def.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ @@ -94,9 +94,9 @@ Trusted SRAM section 0x4000000..0x4200000: #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE /* GIC related definitions */ -#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) -#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) -#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) +#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) +#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) +#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ diff --git a/plat/marvell/a3700/common/io_addr_dec.c b/plat/marvell/a3700/common/io_addr_dec.c index e40fac97..c1c404aa 100644 --- a/plat/marvell/a3700/common/io_addr_dec.c +++ b/plat/marvell/a3700/common/io_addr_dec.c @@ -9,9 +9,12 @@ #include <mmio.h> #include <io_addr_dec.h> -#define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off)) -#define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off) + 0x4) -#define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off) + 0x8) +#define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off)) +#define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off) + 0x4) +#define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off) + 0x8) #define MVEBU_DEC_WIN_CTRL_SIZE_OFF (16) #define MVEBU_DEC_WIN_ENABLE (0x1) @@ -22,65 +25,81 @@ #define MVEBU_WIN_BASE_SIZE_ALIGNMENT (0x10000) -/* There are up to 14 IO unit which need address deocode in Armada-3700 */ +/* There are up to 14 IO unit which need address decode in Armada-3700 */ #define IO_UNIT_NUM_MAX (14) #define MVEBU_MAX_ADDRSS_4GB (0x100000000ULL) -static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, uintptr_t win_size, struct dec_win_config *dec_win) +static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, + uintptr_t win_size, + struct dec_win_config *dec_win) { uint32_t ctrl = 0; uint32_t base = 0; /* set size */ - ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << MVEBU_DEC_WIN_CTRL_SIZE_OFF; + ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << + MVEBU_DEC_WIN_CTRL_SIZE_OFF; /* set attr according to IO decode window */ ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF; /* set target */ ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF; /* set base */ - base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << MVEBU_DEC_WIN_BASE_OFF; + base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << + MVEBU_DEC_WIN_BASE_OFF; /* set base address*/ - mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base); + mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), + base); /* set remap window, some unit does not have remap window */ if (win_id < dec_win->max_remap) - mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base); + mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), base); /* set control register */ - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), ctrl); /* enable the address decode window at last to make it effective */ ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF; - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), ctrl); INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)", - win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset)), - mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset))); + win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset)), + mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset))); if (win_id < dec_win->max_remap) INFO(" remap(%x)\n", - mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset))); + mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset))); else INFO("\n"); } /* Set io decode window */ -static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config *dec_win) +static int set_io_addr_dec(struct dram_win_map *win_map, + struct dec_win_config *dec_win) { struct dram_win *win; int id; /* disable all windows first */ for (id = 0; id < dec_win->max_dram_win; id++) - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset), 0); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, + dec_win->win_offset), 0); - /* configure IO decode windows for DRAM, inheritate DRAM size, base and target from CPU-DRAM - * decode window, and others from hard coded IO decode window settings array. + /* configure IO decode windows for DRAM, inheritate DRAM size, + * base and target from CPU-DRAM decode window and others + * from hard coded IO decode window settings array. */ if (win_map->dram_win_num > dec_win->max_dram_win) { /* - * If cpu dram windows number exceeds the io decode windows max number, - * then fill the first io decode window with base(0) and size(4GB). - */ + * If cpu dram windows number exceeds the io decode windows + * max number, then fill the first io decode window + * with base(0) and size(4GB). + */ set_io_addr_dec_win(0, 0, MVEBU_MAX_ADDRSS_4GB, dec_win); return 0; @@ -108,7 +127,8 @@ static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config * * * @return: 0 on success and others on failure */ -int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *io_dec_config, uint32_t io_unit_num) +int init_io_addr_dec(struct dram_win_map *dram_wins_map, + struct dec_win_config *io_dec_config, uint32_t io_unit_num) { int32_t index; struct dec_win_config *io_dec_win; @@ -122,7 +142,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * } if (io_unit_num > IO_UNIT_NUM_MAX) { - ERROR("IO address decoder windows number %d is over max number %d\n", io_unit_num, IO_UNIT_NUM_MAX); + ERROR("IO address decoder windows number %d is over max %d\n", + io_unit_num, IO_UNIT_NUM_MAX); return -1; } @@ -133,7 +154,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * for (index = 0; index < dram_wins_map->dram_win_num; index++) INFO("DRAM mapping %d base(0x%lx) size(0x%lx)\n", - index, dram_wins_map->dram_windows[index].base_addr, dram_wins_map->dram_windows[index].win_size); + index, dram_wins_map->dram_windows[index].base_addr, + dram_wins_map->dram_windows[index].win_size); /* Set address decode window for each IO */ for (index = 0; index < io_unit_num; index++) { @@ -143,9 +165,11 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * ERROR("Failed to set IO address decode\n"); return -1; } - INFO("Set IO decode window successfully, base(0x%x)", io_dec_win->dec_reg_base); + INFO("Set IO decode window successfully, base(0x%x)", + io_dec_win->dec_reg_base); INFO(" win_attr(%x) max_dram_win(%d) max_remap(%d) win_offset(%d)\n", - io_dec_win->win_attr, io_dec_win->max_dram_win, io_dec_win->max_remap, io_dec_win->win_offset); + io_dec_win->win_attr, io_dec_win->max_dram_win, + io_dec_win->max_remap, io_dec_win->win_offset); } return 0; diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/a3700/common/marvell_plat_config.c index 8501ad5b..8207658c 100644 --- a/plat/marvell/a3700/common/marvell_plat_config.c +++ b/plat/marvell/a3700/common/marvell_plat_config.c @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <types.h> -#include <plat_def.h> #include <io_addr_dec.h> +#include <mvebu_def.h> +#include <types.h> struct dec_win_config io_dec_win_conf[] = { /* dec_reg_base win_attr max_dram_win max_remap win_offset */ diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/a3700/common/plat_pm.c index 06da17e4..13df14a1 100644 --- a/plat/marvell/a3700/common/plat_pm.c +++ b/plat/marvell/a3700/common/plat_pm.c @@ -1,22 +1,23 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <a3700_pm.h> #include <arch_helpers.h> -#include <plat_marvell.h> -#include <plat_private.h> -#include <plat_def.h> -#include <psci.h> +#include <armada_common.h> #include <debug.h> +#include <dram_win.h> +#include <io_addr_dec.h> #include <mmio.h> #include <mvebu.h> +#include <mvebu_def.h> +#include <marvell_plat_priv.h> #include <platform.h> -#include <a3700_pm.h> -#include <io_addr_dec.h> -#include <plat_config.h> -#include <dram_win.h> +#include <plat_marvell.h> +#include <psci.h> #ifdef USE_CCI #include <cci.h> #endif @@ -39,22 +40,36 @@ /* IRQ register */ #define MVEBU_NB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE) -#define MVEBU_NB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x10) -#define MVEBU_NB_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x18) -#define MVEBU_SB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x40) -#define MVEBU_SB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x50) -#define MVEBU_NB_GPIO_IRQ_MASK_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xC8) -#define MVEBU_NB_GPIO_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xD8) -#define MVEBU_SB_GPIO_IRQ_MASK_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xE8) +#define MVEBU_NB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_NB_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x18) +#define MVEBU_SB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x40) +#define MVEBU_SB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x50) +#define MVEBU_NB_GPIO_IRQ_MASK_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xC8) +#define MVEBU_NB_GPIO_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xD8) +#define MVEBU_SB_GPIO_IRQ_MASK_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xE8) #define MVEBU_NB_GPIO_IRQ_EN_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE) -#define MVEBU_NB_GPIO_IRQ_EN_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x04) -#define MVEBU_NB_GPIO_IRQ_STATUS_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x10) -#define MVEBU_NB_GPIO_IRQ_STATUS_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x14) -#define MVEBU_NB_GPIO_IRQ_WK_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x18) -#define MVEBU_NB_GPIO_IRQ_WK_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x1C) +#define MVEBU_NB_GPIO_IRQ_EN_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x04) +#define MVEBU_NB_GPIO_IRQ_STATUS_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_NB_GPIO_IRQ_STATUS_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x14) +#define MVEBU_NB_GPIO_IRQ_WK_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x18) +#define MVEBU_NB_GPIO_IRQ_WK_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x1C) #define MVEBU_SB_GPIO_IRQ_EN_REG (MVEBU_SB_GPIO_IRQ_REG_BASE) -#define MVEBU_SB_GPIO_IRQ_STATUS_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + 0x10) -#define MVEBU_SB_GPIO_IRQ_WK_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + 0x18) +#define MVEBU_SB_GPIO_IRQ_STATUS_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_SB_GPIO_IRQ_WK_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + \ + 0x18) /* PMU registers */ #define MVEBU_PM_NB_PWR_CTRL_REG (MVEBU_PMSU_REG_BASE) @@ -177,9 +192,8 @@ struct wake_up_src_func_map { wake_up_src_func func; }; -void psci_arch_init(int die_index) +void marvell_psci_arch_init(int die_index) { - return; } static void a3700_pm_ack_irq(void) @@ -221,7 +235,7 @@ static void a3700_pm_ack_irq(void) ***************************************************************************** */ int a3700_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) + psci_power_state_t *req_state) { ERROR("a3700_validate_power_state needs to be implemented\n"); panic(); @@ -248,7 +262,8 @@ int a3700_pwr_domain_on(u_register_t mpidr) __asm__ volatile("dsb sy"); /* Set the cpu start address to BL1 entry point */ - mmio_write_32(MVEBU_CPU_1_RESET_VECTOR, PLAT_MARVELL_CPU_ENTRY_ADDR >> 2); + mmio_write_32(MVEBU_CPU_1_RESET_VECTOR, + PLAT_MARVELL_CPU_ENTRY_ADDR >> 2); /* Get the cpu out of reset */ mmio_clrbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); @@ -282,9 +297,12 @@ void a3700_pwr_domain_off(const psci_power_state_t *target_state) * Enable Core VDD OFF, core is supposed to be powered * off by PMU when WFI command is issued. */ - mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx, MVEBU_PM_CORE_PD); + mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx, + MVEBU_PM_CORE_PD); - /* Core can not be powered down with pending IRQ, acknowledge all the pending IRQ */ + /* Core can not be powered down with pending IRQ, + * acknowledge all the pending IRQ + */ a3700_pm_ack_irq(); } @@ -294,22 +312,22 @@ static void a3700_set_gen_pwr_off_option(void) mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); /* - * North bridge cannot be VDD off (always ON). The NB state machine support low power - * mode by its state machine. - * This bit MUST be set for north bridge power down, e.g., OSC input cutoff(NOT TEST), - * SRAM power down, PMIC, etc. + * North bridge cannot be VDD off (always ON). + * The NB state machine support low power mode by its state machine. + * This bit MUST be set for north bridge power down, e.g., + * OSC input cutoff(NOT TEST), SRAM power down, PMIC, etc. * It is not related to CPU VDD OFF!! */ mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_CPU_VDDV_OFF_EN); /* * MUST: Switch CPU/AXI clock to OSC - * NB state machine clock is always connected to OSC (slow clock). But Core0/1/processor - * state machine's clock are connected to AXI clock. Now, AXI clock takes the - * TBG as clock source. - * If using AXI clock, Core0/1/processor state machine may much faster than - * NB state machine. It will cause problem in this case if cores are released - * before north bridge gets ready. + * NB state machine clock is always connected to OSC (slow clock). + * But Core0/1/processor state machine's clock are connected to AXI + * clock. Now, AXI clock takes the TBG as clock source. + * If using AXI clock, Core0/1/processor state machine may much faster + * than NB state machine. It will cause problem in this case if cores + * are released before north bridge gets ready. */ mmio_clrbits_32(MVEBU_NB_CLOCK_SEL_REG, MVEBU_A53_CPU_CLK_SEL); @@ -328,9 +346,10 @@ static void a3700_set_gen_pwr_off_option(void) /* * Idle AXI interface in order to get L2_WFI - * L2 WFI is only asserted after CORE-0 and CORE-1 WFI asserted. (only both core-0/1 - * in WFI, L2 WFI will be issued by CORE.) - * Once L2 WFI asserted, this bit is used for signalling assertion to AXI IO masters. + * L2 WFI is only asserted after CORE-0 and CORE-1 WFI asserted. + * (only both core-0/1in WFI, L2 WFI will be issued by CORE.) + * Once L2 WFI asserted, this bit is used for signalling assertion + * to AXI IO masters. */ mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); @@ -352,37 +371,47 @@ static void a3700_set_gen_pwr_off_option(void) static void a3700_en_ddr_self_refresh(void) { /* - * Both count is 16 bits and configurable. By default, osc stb cnt is 0xFFF for lower 12 bits. + * Both count is 16 bits and configurable. By default, osc stb cnt + * is 0xFFF for lower 12 bits. * Thus, powerdown count is smaller than osc count. * This count is used for exiting DDR SR mode on wakeup event. * The powerdown count also has impact on the following * state changes: idle -> count-down -> ... (power-down, vdd off, etc) * Here, make stable counter shorter - * Use power down count value instead of osc_stb_cnt to speed up DDR self refresh exit + * Use power down count value instead of osc_stb_cnt to speed up + * DDR self refresh exit */ mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_PWR_DN_CNT_SEL); /* * Enable DDR SR mode => controlled by north bridge state machine - * Therefore, we must powerdown north bridge to trigger the DDR SR mode switching. + * Therefore, we must powerdown north bridge to trigger the DDR SR + * mode switching. */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_SR_EN); /* Disable DDR clock, otherwise DDR will not enter into SR mode. */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_CLK_DIS_EN); /* Power down DDR PHY (PAD) */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PWRDWN_EN); - mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PAD_PWRDWN_EN); + mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, + MVEBU_PM_DDRPHY_PAD_PWRDWN_EN); /* Set wait time for DDR ready in ROM code */ - mmio_write_32(MVEBU_PM_CPU_VDD_OFF_INFO_1_REG, MVEBU_PM_WAIT_DDR_RDY_VALUE); + mmio_write_32(MVEBU_PM_CPU_VDD_OFF_INFO_1_REG, + MVEBU_PM_WAIT_DDR_RDY_VALUE); /* DDR flush write buffer - mandatory */ - mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | MVEBU_DRAM_CS_CMD0 | MVEBU_DRAM_WCB_DRAIN_REQ); - while ((mmio_read_32(MVEBU_DRAM_STATS_CH0_REG) & MVEBU_DRAM_WCP_EMPTY) != MVEBU_DRAM_WCP_EMPTY) + mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | + MVEBU_DRAM_CS_CMD0 | MVEBU_DRAM_WCB_DRAIN_REQ); + while ((mmio_read_32(MVEBU_DRAM_STATS_CH0_REG) & + MVEBU_DRAM_WCP_EMPTY) != MVEBU_DRAM_WCP_EMPTY) ; - /* Trigger PHY reset after ddr out of self refresh => supply reset pulse for DDR phy after wake up. */ - mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | MVEBU_DRAM_PHY_AUTO_AC_OFF_EN); + /* Trigger PHY reset after ddr out of self refresh => + * supply reset pulse for DDR phy after wake up + */ + mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | + MVEBU_DRAM_PHY_AUTO_AC_OFF_EN); } static void a3700_pwr_dn_avs(void) @@ -443,7 +472,9 @@ static void a3700_set_pwr_off_option(void) /* Power down TBG */ a3700_pwr_dn_tbg(); - /* Power down south bridge, pay attention south bridge setting should be done before */ + /* Power down south bridge, pay attention south bridge setting + * should be done before + */ a3700_pwr_dn_sb(); } @@ -456,7 +487,8 @@ static void a3700_set_wake_up_option(void) mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_NB_WKP_EN); /* Enable both core0 and core1 wakeup on demand */ - mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, MVEBU_PM_CORE1_WAKEUP | MVEBU_PM_CORE0_WAKEUP); + mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, + MVEBU_PM_CORE1_WAKEUP | MVEBU_PM_CORE0_WAKEUP); /* Enable warm reset in low power mode */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_WARM_RESET_EN); @@ -479,21 +511,27 @@ static void a3700_pm_en_nb_gpio(uint32_t gpio) mmio_setbits_32(MVEBU_NB_GPIO_IRQ_EN_LOW_REG, BIT(gpio)); } - mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK); + mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, + MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK); - /* Enable using GPIO as wakeup event (actually not only for north bridge) */ + /* Enable using GPIO as wakeup event + * (actually not only for north bridge) + */ mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_NB_GPIO_WKP_EN | - MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); + MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | + MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); } static void a3700_pm_en_sb_gpio(uint32_t gpio) { /* Enable using GPIO as wakeup event */ mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_SB_WKP_NB_EN | - MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); + MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | + MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); /* SB GPIO Wake UP | South Bridge Wake Up Enable */ - mmio_setbits_32(MVEBU_PM_SB_WK_EN_REG, MVEBU_PM_SB_GPIO_WKP_EN | MVEBU_PM_SB_GPIO_WKP_EN); + mmio_setbits_32(MVEBU_PM_SB_WK_EN_REG, MVEBU_PM_SB_GPIO_WKP_EN | + MVEBU_PM_SB_GPIO_WKP_EN); /* GPIO int mask */ mmio_clrbits_32(MVEBU_SB_GPIO_IRQ_MASK_REG, BIT(gpio)); @@ -548,7 +586,8 @@ struct wake_up_src_func_map src_func_table[WAKE_UP_SRC_MAX] = { {WAKE_UP_SRC_TIMER, NULL} }; -static wake_up_src_func a3700_get_wake_up_src_func(enum pm_wake_up_src_type type) +static wake_up_src_func a3700_get_wake_up_src_func( + enum pm_wake_up_src_type type) { uint32_t loop; for (loop = 0; loop < WAKE_UP_SRC_MAX; loop++) { @@ -566,7 +605,8 @@ static void a3700_set_wake_up_source(void) wake_up_src = mv_wake_up_src_config_get(); for (loop = 0; loop < wake_up_src->wake_up_src_num; loop++) { - src_func = a3700_get_wake_up_src_func(wake_up_src->wake_up_src[loop].wake_up_src_type); + src_func = a3700_get_wake_up_src_func( + wake_up_src->wake_up_src[loop].wake_up_src_type); if (src_func) src_func(&(wake_up_src->wake_up_src[loop].wake_up_data)); } @@ -577,19 +617,22 @@ static void a3700_set_wake_up_source(void) static void a3700_pm_save_lp_flag(void) { /* Save the flag for enter the low power mode */ - mmio_setbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE); + mmio_setbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, + MVEBU_PM_LOW_POWER_STATE); } static void a3700_pm_clear_lp_flag(void) { /* Clear the flag for enter the low power mode */ - mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE); + mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, + MVEBU_PM_LOW_POWER_STATE); } static uint32_t a3700_pm_get_lp_flag(void) { /* Get the flag for enter the low power mode */ - return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & MVEBU_PM_LOW_POWER_STATE; + return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & + MVEBU_PM_LOW_POWER_STATE; } /***************************************************************************** @@ -634,7 +677,7 @@ void a3700_pwr_domain_suspend(const psci_power_state_t *target_state) void a3700_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Per-CPU interrupt initialization */ plat_marvell_gic_pcpu_init(); @@ -660,7 +703,7 @@ void a3700_pwr_domain_suspend_finish(const psci_power_state_t *target_state) struct dram_win_map dram_wins_map; /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ plat_marvell_gic_init(); @@ -726,9 +769,6 @@ static void __dead2 a3700_system_off(void) { ERROR("a3700_system_off needs to be implemented\n"); panic(); - wfi(); - ERROR("A3700 System Off: operation not handled.\n"); - panic(); } /***************************************************************************** @@ -744,7 +784,8 @@ static void __dead2 a3700_system_reset(void) /* Flush data cache if the mail box shared RAM is cached */ #if PLAT_MARVELL_SHARED_RAM_CACHED - flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, 2 * sizeof(uint64_t)); + flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, + 2 * sizeof(uint64_t)); #endif /* Trigger the warm reset */ diff --git a/plat/marvell/a8k-p/a8xxy/board/dram_port.c b/plat/marvell/a8k-p/a8xxy/board/dram_port.c index fa7ff2e3..b18e2c3e 100644 --- a/plat/marvell/a8k-p/a8xxy/board/dram_port.c +++ b/plat/marvell/a8k-p/a8xxy/board/dram_port.c @@ -4,8 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* DB-88F8160-MODULAR has 4 DIMMs on board that are connected to @@ -16,7 +17,8 @@ * AP1 DIMM1 - 0x56 */ #define I2C_SPD_BASE_ADDR 0x53 -#define I2C_SPD_DATA_ADDR(ap_id, iface) (I2C_SPD_BASE_ADDR + (ap_id * DDR_MAX_UNIT_PER_AP) + (iface)) +#define I2C_SPD_DATA_ADDR(ap_id, iface) (I2C_SPD_BASE_ADDR + \ + (ap_id * DDR_MAX_UNIT_PER_AP) + (iface)) #define I2C_SPD_P0_SEL_ADDR 0x36 /* Select SPD data page 0 */ #define MC_RAR_INTERLEAVE_SZ (128) /* Also possible to set to 4Kb */ diff --git a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c index e6702689..e0a99a05 100644 --- a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c +++ b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c @@ -4,9 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <ap810_setup.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> /* This array describe how CPx connect to APx, via which MCI interface * For AP0: CP0 connected via MCI3 @@ -85,11 +86,11 @@ int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *siz if (ap_count < 3) { switch (ap) { case 0: - *size = sizeof(gwin_memory_map2_ap0)/sizeof(gwin_memory_map2_ap0[0]); + *size = ARRAY_SIZE(gwin_memory_map2_ap0); *win = gwin_memory_map2_ap0; return 0; case 1: - *size = sizeof(gwin_memory_map2_ap1)/sizeof(gwin_memory_map2_ap1[0]); + *size = ARRAY_SIZE(gwin_memory_map2_ap1); *win = gwin_memory_map2_ap1; return 0; default: @@ -98,19 +99,19 @@ int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *siz } else { switch (ap) { case 0: - *size = sizeof(gwin_memory_map4_ap0)/sizeof(gwin_memory_map4_ap0[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap0); *win = gwin_memory_map4_ap0; return 0; case 1: - *size = sizeof(gwin_memory_map4_ap1)/sizeof(gwin_memory_map4_ap1[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap1); *win = gwin_memory_map4_ap1; return 0; case 2: - *size = sizeof(gwin_memory_map4_ap2)/sizeof(gwin_memory_map4_ap2[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap2); *win = gwin_memory_map4_ap2; return 0; case 3: - *size = sizeof(gwin_memory_map4_ap3)/sizeof(gwin_memory_map4_ap3[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap3); *win = gwin_memory_map4_ap3; return 0; default: @@ -177,11 +178,11 @@ int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size if (ap_count < 3) { switch (ap) { case 0: - *size = sizeof(ccu_memory_map2_ap0)/sizeof(ccu_memory_map2_ap0[0]); + *size = ARRAY_SIZE(ccu_memory_map2_ap0); *win = ccu_memory_map2_ap0; return 0; case 1: - *size = sizeof(ccu_memory_map2_ap1)/sizeof(ccu_memory_map2_ap1[0]); + *size = ARRAY_SIZE(ccu_memory_map2_ap1); *win = ccu_memory_map2_ap1; return 0; default: @@ -190,19 +191,19 @@ int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size } else { switch (ap) { case 0: - *size = sizeof(ccu_memory_map_ap0)/sizeof(ccu_memory_map_ap0[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap0); *win = ccu_memory_map_ap0; return 0; case 1: - *size = sizeof(ccu_memory_map_ap1)/sizeof(ccu_memory_map_ap1[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap1); *win = ccu_memory_map_ap1; return 0; case 2: - *size = sizeof(ccu_memory_map_ap2)/sizeof(ccu_memory_map_ap2[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap2); *win = ccu_memory_map_ap2; return 0; case 3: - *size = sizeof(ccu_memory_map_ap3)/sizeof(ccu_memory_map_ap3[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap3); *win = ccu_memory_map_ap3; return 0; default: @@ -241,18 +242,19 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return STM_TID; } -int marvell_get_io_win_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { int ap_count = ap_get_count(); if (ap_count < 3) { switch (ap) { case 0: - *size = sizeof(io_win_memory_map2_ap0)/sizeof(io_win_memory_map2_ap0[0]); + *size = ARRAY_SIZE(io_win_memory_map2_ap0); *win = io_win_memory_map2_ap0; return 0; case 1: - *size = sizeof(io_win_memory_map2_ap1)/sizeof(io_win_memory_map2_ap1[0]); + *size = ARRAY_SIZE(io_win_memory_map2_ap1); *win = io_win_memory_map2_ap1; return 0; default: @@ -488,28 +490,29 @@ struct addr_map_win *iob_map[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUN uint32_t iob_map_size[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUNT] = { /* AP0 */ - { sizeof(iob_memory_map_ap0_cp0)/sizeof(iob_memory_map_ap0_cp0[0]), - sizeof(iob_memory_map_ap0_cp1)/sizeof(iob_memory_map_ap0_cp1[0]), - sizeof(iob_memory_map_ap0_cp2)/sizeof(iob_memory_map_ap0_cp2[0]), - sizeof(iob_memory_map_ap0_cp3)/sizeof(iob_memory_map_ap0_cp3[0]) }, + { ARRAY_SIZE(iob_memory_map_ap0_cp0), + ARRAY_SIZE(iob_memory_map_ap0_cp1), + ARRAY_SIZE(iob_memory_map_ap0_cp2), + ARRAY_SIZE(iob_memory_map_ap0_cp3) }, /* AP1 */ - { sizeof(iob_memory_map_ap1_cp0)/sizeof(iob_memory_map_ap1_cp0[0]), - sizeof(iob_memory_map_ap1_cp1)/sizeof(iob_memory_map_ap1_cp1[0]), - sizeof(iob_memory_map_ap1_cp2)/sizeof(iob_memory_map_ap1_cp2[0]), - sizeof(iob_memory_map_ap1_cp3)/sizeof(iob_memory_map_ap1_cp3[0]) }, + { ARRAY_SIZE(iob_memory_map_ap1_cp0), + ARRAY_SIZE(iob_memory_map_ap1_cp1), + ARRAY_SIZE(iob_memory_map_ap1_cp2), + ARRAY_SIZE(iob_memory_map_ap1_cp3) }, /* AP2 */ - { sizeof(iob_memory_map_ap2_cp0)/sizeof(iob_memory_map_ap2_cp0[0]), - sizeof(iob_memory_map_ap2_cp1)/sizeof(iob_memory_map_ap2_cp1[0]), - sizeof(iob_memory_map_ap2_cp2)/sizeof(iob_memory_map_ap2_cp2[0]), - sizeof(iob_memory_map_ap2_cp3)/sizeof(iob_memory_map_ap2_cp3[0]) }, + { ARRAY_SIZE(iob_memory_map_ap2_cp0), + ARRAY_SIZE(iob_memory_map_ap2_cp1), + ARRAY_SIZE(iob_memory_map_ap2_cp2), + ARRAY_SIZE(iob_memory_map_ap2_cp3) }, /* AP3 */ - { sizeof(iob_memory_map_ap3_cp0)/sizeof(iob_memory_map_ap3_cp0[0]), - sizeof(iob_memory_map_ap3_cp1)/sizeof(iob_memory_map_ap3_cp1[0]), - sizeof(iob_memory_map_ap3_cp2)/sizeof(iob_memory_map_ap3_cp2[0]), - sizeof(iob_memory_map_ap3_cp3)/sizeof(iob_memory_map_ap3_cp3[0]) } + { ARRAY_SIZE(iob_memory_map_ap3_cp0), + ARRAY_SIZE(iob_memory_map_ap3_cp1), + ARRAY_SIZE(iob_memory_map_ap3_cp2), + ARRAY_SIZE(iob_memory_map_ap3_cp3) } }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { int ap, cp; @@ -532,7 +535,8 @@ int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintpt * AMB Configuration ***************************************************************************** */ -struct addr_map_win *amb_map[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUNT] = { +struct addr_map_win *amb_map[PLAT_MARVELL_NORTHB_COUNT] + [PLAT_MARVELL_SOUTHB_COUNT] = { /* AP0 */ { NULL, NULL, NULL, NULL }, /* AP1 */ @@ -554,7 +558,8 @@ uint32_t amb_map_size[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUNT] = { { 0, 0, 0, 0 }, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { int ap, cp; diff --git a/plat/marvell/a8k-p/a8xxy/plat_def.h b/plat/marvell/a8k-p/a8xxy/mvebu_def.h index 77b5eaee..77b5eaee 100644 --- a/plat/marvell/a8k-p/a8xxy/plat_def.h +++ b/plat/marvell/a8k-p/a8xxy/mvebu_def.h diff --git a/plat/marvell/a8k-p/common/a8kp_common.mk b/plat/marvell/a8k-p/common/a8kp_common.mk index d03f7fe7..d1175a3d 100644 --- a/plat/marvell/a8k-p/common/a8kp_common.mk +++ b/plat/marvell/a8k-p/common/a8kp_common.mk @@ -13,6 +13,8 @@ PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common MARVELL_DRV_BASE := drivers/marvell MARVELL_COMMON_BASE := plat/marvell/common +$(eval $(call add_define,PLAT_FAMILY)) + ERRATA_A72_859971 := 1 # Enable MSS support for a8kp family diff --git a/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c b/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c index 1df6a0cd..d0f3f23d 100644 --- a/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c +++ b/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c @@ -26,7 +26,7 @@ static void plat_enable_affinity(void) __asm__ volatile("isb"); } -void psci_arch_init(int ap_index) +void marvell_psci_arch_init(int ap_index) { #if LLC_ENABLE /* check if LLC is in exclusive mode diff --git a/plat/marvell/a8k-p/common/ap810_init_clocks.c b/plat/marvell/a8k-p/common/ap810_init_clocks.c index 580a2e3e..742caae9 100644 --- a/plat/marvell/a8k-p/common/ap810_init_clocks.c +++ b/plat/marvell/a8k-p/common/ap810_init_clocks.c @@ -12,7 +12,7 @@ #include <errno.h> #include <debug.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <stdio.h> /* PLL's registers with local base address since each AP has its own EAWG*/ diff --git a/plat/marvell/a8k-p/common/include/platform_def.h b/plat/marvell/a8k-p/common/include/platform_def.h index e784058e..a4ee0ae4 100644 --- a/plat/marvell/a8k-p/common/include/platform_def.h +++ b/plat/marvell/a8k-p/common/include/platform_def.h @@ -11,7 +11,7 @@ #include <board_marvell_def.h> #include <gic_common.h> #include <interrupt_props.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ diff --git a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c index e0d74978..a58032d4 100644 --- a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c @@ -10,8 +10,8 @@ #include <debug.h> #include <mmio.h> #include "mss_scp_bootloader.h" +#include <marvell_plat_priv.h> #include <platform_def.h> -#include <plat_private.h> /* timer functionality */ #define MSS_AP_REG_BASE 0x580000 #define MSS_CP_REG_BASE 0x280000 diff --git a/plat/marvell/a8k-p/common/plat_bl1_setup.c b/plat/marvell/a8k-p/common/plat_bl1_setup.c index c406c4f3..e573aeeb 100644 --- a/plat/marvell/a8k-p/common/plat_bl1_setup.c +++ b/plat/marvell/a8k-p/common/plat_bl1_setup.c @@ -1,19 +1,18 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> -#include <plat_marvell.h> -#include <plat_private.h> - +#include <armada_common.h> #include <ap810_setup.h> #include <debug.h> #include <delay_timer.h> #include <mci.h> #include <mmio.h> +#include <marvell_plat_priv.h> +#include <plat_marvell.h> /* MCI related defines */ #define MVEBU_AP_SYSTEM_SOFT_RESET_REG(ap) (MVEBU_AP_MISC_SOC_BASE(ap) + 0x54) diff --git a/plat/marvell/a8k-p/common/plat_bl31_setup.c b/plat/marvell/a8k-p/common/plat_bl31_setup.c index de5a20fa..c6ad538a 100644 --- a/plat/marvell/a8k-p/common/plat_bl31_setup.c +++ b/plat/marvell/a8k-p/common/plat_bl31_setup.c @@ -5,14 +5,13 @@ * https://spdx.org/licenses */ -#include <plat_marvell.h> -#include <plat_private.h> - #include <ap810_setup.h> #include <cache_llc.h> #include <cp110_setup.h> #include <debug.h> #include <marvell_pm.h> +#include <marvell_plat_priv.h> +#include <plat_marvell.h> #define CCU_ROUT_OPT_DIS(ap, stop) (MVEBU_A2_BANKED_STOP_BASE(ap, stop) + 0x8) #define CCU_SFWD_UL_AC_EN_OFFSET 9 diff --git a/plat/marvell/a8k-p/common/plat_ble_setup.c b/plat/marvell/a8k-p/common/plat_ble_setup.c index 8e9358ee..cdd5dbc4 100644 --- a/plat/marvell/a8k-p/common/plat_ble_setup.c +++ b/plat/marvell/a8k-p/common/plat_ble_setup.c @@ -11,8 +11,8 @@ #include <a8kp_plat_def.h> #include <debug.h> #include <mmio.h> +#include <mvebu_def.h> #include <plat_marvell.h> -#include <plat_def.h> #include <plat_dram.h> /* Read Frequency Value from MPPS 15-17 and save diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c index 36052da1..713dc7a1 100644 --- a/plat/marvell/a8k-p/common/plat_dram.c +++ b/plat/marvell/a8k-p/common/plat_dram.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <addr_map.h> #include <a8k_i2c.h> #include <ap810_setup.h> @@ -13,7 +14,7 @@ #include <gwin.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_dram.h> #define CCU_RGF_WIN0_REG(ap) (MVEBU_CCU_BASE(ap) + 0x90) @@ -45,7 +46,8 @@ #define REMAP_ENABLE_MASK 0x1 /* iface is 0 or 1 */ -#define DSS_SCR_REG(ap, iface) (MVEBU_AR_RFU_BASE(ap) + 0x208 + ((iface) * 0x4)) +#define DSS_SCR_REG(ap, iface) (MVEBU_AR_RFU_BASE(ap) + 0x208 + \ + ((iface) * 0x4)) #define DSS_PPROT_OFFS 4 #define DSS_PPROT_MASK 0x7 #define DSS_PPROT_PRIV_SECURE_DATA 0x1 @@ -58,7 +60,8 @@ extern struct mv_ddr_iface *ptr_iface; /* Use global varibale to check if i2c initialization done */ int i2c_init_done = 0; -static int plat_dram_ap_ifaces_get(int ap_id, struct mv_ddr_iface **ifaces, uint32_t *size) +static int plat_dram_ap_ifaces_get(int ap_id, struct mv_ddr_iface **ifaces, + uint32_t *size) { /* For now support DRAM on AP0/AP1 - TODO: add support for all APs */ if (ap_id == 0) { @@ -110,8 +113,8 @@ static void mpp_config(void) uint32_t val; /* - * The Ax0x0 A0 DB boards are using the AP0 i2c channel (MPP18 and MPP19) - * for accessing all DIMM SPDs available on board. + * The Ax0x0 A0 DB boards are using the AP0 i2c channel + * (MPP18 and MPP19) for accessing all DIMM SPDs available on board. */ reg = MVEBU_AP_MPP_CTRL16_23_REG; val = mmio_read_32(reg); @@ -143,7 +146,8 @@ void plat_dram_freq_update(enum ddr_freq freq_option) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -static void plat_dram_update_topology(uint32_t ap_id, struct mv_ddr_iface *iface) +static void plat_dram_update_topology(uint32_t ap_id, + struct mv_ddr_iface *iface) { struct mv_ddr_topology_map *tm = &iface->tm; int ret; @@ -195,13 +199,15 @@ static void plat_dram_phy_access_config(uint32_t ap_id, uint32_t iface_id) /* Update PHY destination in RGF window */ reg_val = mmio_read_32(CCU_RGF_WIN0_REG(ap_id)); reg_val &= ~(CCU_RGF_WIN_UNIT_ID_MASK << CCU_RGF_WIN_UNIT_ID_OFFS); - reg_val |= ((dram_target & CCU_RGF_WIN_UNIT_ID_MASK) << CCU_RGF_WIN_UNIT_ID_OFFS); + reg_val |= ((dram_target & CCU_RGF_WIN_UNIT_ID_MASK) << + CCU_RGF_WIN_UNIT_ID_OFFS); mmio_write_32(CCU_RGF_WIN0_REG(ap_id), reg_val); /* Update DSS port access permission to DSS_PHY */ reg_val = mmio_read_32(DSS_SCR_REG(ap_id, iface_id)); reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); - reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << DSS_PPROT_OFFS); + reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << + DSS_PPROT_OFFS); mmio_write_32(DSS_SCR_REG(ap_id, iface_id), reg_val); debug_exit(); @@ -223,8 +229,9 @@ static void plat_dram_rar_mode_set(uint32_t ap_id) mmio_write_32(CCU_MC_ITR_OFFSET(ap_id, DRAM_1_TID), interleave); /* Configure RAR registers: - * For RAR 0: mask = interleave, value = 0x0, target = 0x3, enable =0x1. - * For RAR 1: mask = interleave, value = interleave, target = 0x8, enable =0x1 + * For RAR 0: mask = interleave, value = 0x0, target = 0x3, enable = 0x1 + * For RAR 1: mask = interleave, value = interleave, target = 0x8, + * enable =0x1 */ val = interleave << MC_RAR_ADDR_MASK_OFFSET; val |= (DRAM_0_TID << MC_RAR_TID_OFFSET) | MC_RAR_ENABLE; @@ -238,8 +245,9 @@ static void plat_dram_rar_mode_set(uint32_t ap_id) debug_exit(); } -/* Remap Physical address range to Memory Controller addrress range (PA->MCA) */ -void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, uint64_t to, uint64_t size) +/* Remap Physical address range to Memory Controller address range (PA->MCA) */ +void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, + uint64_t to, uint64_t size) { int dram_if[] = { -1, -1 }; int if_idx; @@ -276,14 +284,18 @@ void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, uint64_t to, /* set mc remap source base to the top of dram */ val = (from & REMAP_ADDR_MASK) << REMAP_ADDR_OFFSET; VERBOSE("AP-%d DRAM%d RSBR(0x%x) <== 0x%x\n", - ap_index, if_idx, CCU_MC_RSBR_OFFSET(ap_index, dram_if[if_idx]), val); - mmio_write_32(CCU_MC_RSBR_OFFSET(ap_index, dram_if[if_idx]), val); + ap_index, if_idx, CCU_MC_RSBR_OFFSET(ap_index, + dram_if[if_idx]), val); + mmio_write_32(CCU_MC_RSBR_OFFSET(ap_index, dram_if[if_idx]), + val); /* set mc remap target base to the overlapped dram region */ val = (to & REMAP_ADDR_MASK) << REMAP_ADDR_OFFSET; VERBOSE("AP-%d DRAM%d RTBR(0x%x) <== 0x%x\n", - ap_index, if_idx, CCU_MC_RTBR_OFFSET(ap_index, dram_if[if_idx]), val); - mmio_write_32(CCU_MC_RTBR_OFFSET(ap_index, dram_if[if_idx]), val); + ap_index, if_idx, CCU_MC_RTBR_OFFSET(ap_index, + dram_if[if_idx]), val); + mmio_write_32(CCU_MC_RTBR_OFFSET(ap_index, + dram_if[if_idx]), val); /* set mc remap size to the size of the overlapped dram region */ /* up to 4GB region for remapping */ @@ -291,8 +303,10 @@ void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, uint64_t to, /* enable remapping */ val |= REMAP_ENABLE_MASK; VERBOSE("AP-%d DRAM%d RCR(0x%x) <== 0x%x\n", - ap_index, if_idx, CCU_MC_RCR_OFFSET(ap_index, dram_if[if_idx]), val); - mmio_write_32(CCU_MC_RCR_OFFSET(ap_index, dram_if[if_idx]), val); + ap_index, if_idx, CCU_MC_RCR_OFFSET(ap_index, + dram_if[if_idx]), val); + mmio_write_32(CCU_MC_RCR_OFFSET(ap_index, dram_if[if_idx]), + val); } debug_exit(); @@ -324,14 +338,18 @@ static void plat_dram_interfaces_update(void) /* Initialize iface mode with single interface */ iface->iface_mode = MV_DDR_RAR_DIS; /* Update base address of interface */ - iface->iface_base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt); + iface->iface_base_addr = AP_DRAM_BASE_ADDR(ap_id, + ap_cnt); /* Count number of interfaces are ready */ - VERBOSE("Found DRAM on interface %d AP-%d\n", iface->id, ap_id); + VERBOSE("Found DRAM on interface %d AP-%d\n", + iface->id, ap_id); iface_cnt++; } - if (iface_cnt < ifaces_size) - NOTICE("\n\tFound %d out of %d DRAM interface in AP %d. Performance may be degraded!!\n", + if (iface_cnt < ifaces_size) { + NOTICE("\n\tFound %d out of %d DRAM interface in AP %d", iface_cnt, ifaces_size, ap_id); + NOTICE(" Performance may be degraded!!\n"); + } } } @@ -345,8 +363,8 @@ static void plat_dram_temp_addr_decode_cfg(uint32_t ap_id, /* Add a single GWIN entry from AP1 to AP0 enabling remote AP access * Also add a CCU widow which will pass all transactions to SRAM * through the GWIN window. - * These widows are needed for DRAM scrubbing and DRAM validation purpose - * both using XOR which saves descriptors on SRAM located in AP0 + * These widows are needed for DRAM scrubbing and DRAM validation + * purpose both using XOR which saves descriptors on SRAM located in AP0 */ if (ap_id != 0) { ccu_temp_win->base_addr = AP_DRAM_BASE_ADDR(0, ap_cnt); @@ -424,24 +442,33 @@ int plat_dram_init(void) * 1. open relevant CCU widow for each interface * according to dram size and ap base address * for validation\scrubbing purpose - * 2. remap dram widow to end of dram size for ap 0 interfaces. - * the remapping here is per interface according to the - * DRAM size of the current interface for DRAM training purpose. + * 2. remap dram widow to end of dram size for ap 0 + * interfaces. The remapping here is per interface + * according to the DRAM size of the current + * interface for DRAM training purpose. */ - plat_dram_temp_addr_decode_cfg(ap_id, ap_cnt, iface, &gwin_temp_win, - &ccu_dram_win, &ccu_temp_win); - if ((ap_id == 0) && (dram_iface_mem_sz_get() > (3 * _1GB_))) + plat_dram_temp_addr_decode_cfg(ap_id, ap_cnt, + iface, &gwin_temp_win, + &ccu_dram_win, + &ccu_temp_win); + if ((ap_id == 0) && + (dram_iface_mem_sz_get() > (3 * _1GB_))) plat_dram_mca_remap(0, ccu_dram_win.target_id, - dram_iface_mem_sz_get(), 3 * _1GB_, _1GB_); + dram_iface_mem_sz_get(), + 3 * _1GB_, _1GB_); /* Call DRAM init per interface */ ret = dram_init(); if (ret) { - ERROR("DRAM interface %d on AP-%d failed\n", i, ap_id); + ERROR("DRAM interface %d on AP-%d failed\n", + i, ap_id); return ret; } - /* Remove the temporary GWIN and CCU windows configured before DRAM training */ - plat_dram_temp_addr_decode_remove(ap_id, &gwin_temp_win, &ccu_temp_win); + /* Remove the temporary GWIN and CCU windows configured + * before DRAM training + */ + plat_dram_temp_addr_decode_remove(ap_id, &gwin_temp_win, + &ccu_temp_win); iface_cnt++; /* Update status of interface */ @@ -452,19 +479,22 @@ int plat_dram_init(void) plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size); for (i = 0; i < iface_cnt; i++, iface++) { plat_dram_iface_set(iface); - /* If the number of interfaces equal to MAX (enable RAR) */ + /* If the number of interfaces == MAX (enable RAR) */ if (iface_cnt == DDR_MAX_UNIT_PER_AP) { - VERBOSE("AP-%d set DRAM%d into RAR mode\n", ap_id, i); + VERBOSE("AP-%d set DRAM%d into RAR mode\n", + ap_id, i); ap_dram_tgt = RAR_TID; /* If the base address not 0x0, need to divide - ** the base address, the dram region will be - ** splitted into dual DRAMs - ** */ + * the base address, the dram region will be + * splitted into dual DRAMs + */ iface->iface_base_addr >>= 1; - if (ap810_rev_id_get(ap_id) == MVEBU_AP810_REV_ID_A0) + if (ap810_rev_id_get(ap_id) == + MVEBU_AP810_REV_ID_A0) /* TODO: add ERRATA */ if (iface->id == 1) - iface->iface_base_addr |= 1UL << 43; + iface->iface_base_addr |= + 1UL << 43; } else { if (iface->id == 1) ap_dram_tgt = DRAM_1_TID; @@ -477,22 +507,29 @@ int plat_dram_init(void) INFO("AP-%d DRAM size is 0x%lx (%lldGB)\n", ap_id, ap_dram_size, ap_dram_size/_1GB_); - /* Remap the physical memory shadowed by the internal registers configuration - * address space to the top of the detected memory area. - * Only the AP0 overlaps this configuration area with the DRAM, so only its memory - * controller has to remap the overlapped region to the upper memory. - * With less than 3GB of DRAM the internal registers space remapping is not needed - * since there is no overlap between DRAM and the configuration address spaces - * The remapping here is for AP0 total DRAM size for operational mode purpose + /* Remap the physical memory shadowed by the internal registers + * configuration address space to the top of the detected memory + * area. + * Only the AP0 overlaps this configuration area with the DRAM, + * so only its memory controller has to remap the overlapped + * region to the upper memory. + * With less than 3GB of DRAM the internal registers space + * remapping is not needed since there is no overlap between + * DRAM and the configuration address spaces + * The remapping here is for AP0 total DRAM size for + * operational mode purpose */ if ((ap_id == 0) && (ap_dram_size > (3 * _1GB_))) - plat_dram_mca_remap(0, ap_dram_tgt, ap_dram_size, 3 * _1GB_, _1GB_); + plat_dram_mca_remap(0, ap_dram_tgt, ap_dram_size, + 3 * _1GB_, _1GB_); if (ap_dram_tgt == RAR_TID) plat_dram_rar_mode_set(ap_id); - /* Restore the original DRAM size before returning to the BootROM. - * The correct DRAM size will be set back by init_ccu() at later stage. + /* Restore the original DRAM size before returning to the + * BootROM. + * The correct DRAM size will be set back by init_ccu() at + * later stage. */ ccu_dram_win.base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt); ccu_dram_win.win_size = AP0_BOOTROM_DRAM_SIZE; diff --git a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c index 75d359c9..f27a31fe 100644 --- a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c +++ b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c @@ -15,13 +15,15 @@ * GICv3 Multi chip initialization **************************************************************************** */ -#define GICD_BASE(chip) (MVEBU_REGS_BASE_AP(chip) + MVEBU_GICD_BASE) +#define GICD_BASE(chip) (MVEBU_REGS_BASE_AP(chip) + \ + MVEBU_GICD_BASE) #define GICD_CHIPSR(chip) (GICD_BASE(chip) + 0xC000) #define GICD_CHIPSR_RTS_OFFSET 4 #define GICD_CHIPSR_RTS_MASK 0x3 #define GICD_DCHIPR(chip) (GICD_BASE(chip) + 0xC004) #define GICD_DCHIPR_PUP_OFFSET 0 -#define GICD_CHIPR(chip) (MVEBU_REGS_BASE_AP(0) + MVEBU_GICD_BASE + 0xC008 + (chip) * 0x8) +#define GICD_CHIPR(chip) (MVEBU_REGS_BASE_AP(0) + \ + MVEBU_GICD_BASE + 0xC008 + (chip) * 0x8) #define GICD_CHIPR_PUP_OFFSET 1 #define GICD_CHIPR_SPI_BLOCKS_OFFSET 5 #define GICD_CHIPR_SPI_BLOCKS_MASK 0x1F @@ -34,8 +36,10 @@ #define GICD_CHIPR_CONFIG_VAL(enable, spi_block_min, spi_blocks, addr) \ ((enable) | \ - (((spi_blocks) & GICD_CHIPR_SPI_BLOCKS_MASK) << GICD_CHIPR_SPI_BLOCKS_OFFSET) | \ - (((spi_block_min) & GICD_CHIPR_SPI_BLOCK_MIN_MASK) << GICD_CHIPR_SPI_BLOCK_MIN_OFFSET) | \ + (((spi_blocks) & GICD_CHIPR_SPI_BLOCKS_MASK) << \ + GICD_CHIPR_SPI_BLOCKS_OFFSET) | \ + (((spi_block_min) & GICD_CHIPR_SPI_BLOCK_MIN_MASK) << \ + GICD_CHIPR_SPI_BLOCK_MIN_OFFSET) | \ (((addr) & GICD_CHIPR_ADDR_MASK) << GICD_CHIPR_ADDR_OFFSET)) @@ -67,8 +71,10 @@ int gic_multi_chip_connection_ready(int ap_id) debug_enter(); do { - pup_in_progress = mmio_read_32(GICD_DCHIPR(ap_id)) & (1 << GICD_DCHIPR_PUP_OFFSET); - write_in_progress = mmio_read_64(GICD_CHIPR(ap_id)) & (1 << GICD_CHIPR_PUP_OFFSET); + pup_in_progress = mmio_read_32(GICD_DCHIPR(ap_id)) & + (1 << GICD_DCHIPR_PUP_OFFSET); + write_in_progress = mmio_read_64(GICD_CHIPR(ap_id)) & + (1 << GICD_CHIPR_PUP_OFFSET); } while ((pup_in_progress || write_in_progress) && (timeout-- > 0)); if (pup_in_progress) { @@ -84,11 +90,13 @@ int gic_multi_chip_connection_ready(int ap_id) #if 0 /* TODO: enable this once CHIPSR reflects the right value */ if (ap_id == 0) { /* Check that the Routing Table status is 'Consistent' */ - int rts_status = (mmio_read_32(GICD_CHIPSR(0)) >> GICD_CHIPSR_RTS_OFFSET) & - GICD_CHIPSR_RTS_MASK; + int rts_status = (mmio_read_32(GICD_CHIPSR(0)) >> + GICD_CHIPSR_RTS_OFFSET) & + GICD_CHIPSR_RTS_MASK; INFO("GICD_CHIPSR: 0x%x\n", mmio_read_32(GICD_CHIPSR(0))); if (rts_status != RTS_CONSISTENT) { - INFO("Routing table status (%d) is not consistent\n", rts_status); + INFO("Routing table status (%d) is not consistent\n", + rts_status); return 1; } } @@ -117,25 +125,33 @@ int gic600_multi_chip_init(void) INFO("Configure AP %d\n", nb_id); spi_block_min = (ap_spi_own[nb_id].spi_start - 32) / 32; - spi_blocks = (ap_spi_own[nb_id].spi_end - ap_spi_own[nb_id].spi_start + 1) / 32; - INFO("spi_block_min = %d - spi_blocks = %d\n", spi_block_min, spi_blocks); + spi_blocks = (ap_spi_own[nb_id].spi_end - + ap_spi_own[nb_id].spi_start + 1) / 32; + INFO("spi_block_min = %d - spi_blocks = %d\n", + spi_block_min, spi_blocks); - reg = GICD_CHIPR_CONFIG_VAL(0x1, spi_block_min, spi_blocks, nb_id); + reg = GICD_CHIPR_CONFIG_VAL(0x1, spi_block_min, + spi_blocks, nb_id); mmio_write_64(GICD_CHIPR(nb_id), reg); val = mmio_read_64(GICD_CHIPR(nb_id)); while (((val >> 1) & 0x1) == 1) val = mmio_read_64(GICD_CHIPR(nb_id)); - INFO("AP %d: GICD_CHIPR(nb_id) = %x - GICD_CHIPR: 0x%lx -- val = %x\n", - nb_id, GICD_CHIPR(nb_id), mmio_read_64(GICD_CHIPR(nb_id)), reg); + INFO("AP%d: GICD_CHIPR(nb_id)=%x GICD_CHIPR: 0x%lx val=%x\n", + nb_id, GICD_CHIPR(nb_id), mmio_read_64(GICD_CHIPR(nb_id)), + reg); if (nb_id == 0) { - INFO("GICD_CHIPSR = %x\n", mmio_read_32(GICD_CHIPSR(nb_id))); - INFO("GICD_CHIPR = %x\n", mmio_read_32(GICD_CHIPR(nb_id))); + INFO("GICD_CHIPSR = %x\n", + mmio_read_32(GICD_CHIPSR(nb_id))); + INFO("GICD_CHIPR = %x\n", + mmio_read_32(GICD_CHIPR(nb_id))); } else { - /* check that write was accepted and connection is ready */ + /* check that write was accepted + * and connection is ready + */ if (gic_multi_chip_connection_ready(nb_id)) return 1; } diff --git a/plat/marvell/a8k-p/common/plat_pm.c b/plat/marvell/a8k-p/common/plat_pm.c index 3dbc1eac..ba68f8bb 100644 --- a/plat/marvell/a8k-p/common/plat_pm.c +++ b/plat/marvell/a8k-p/common/plat_pm.c @@ -7,16 +7,16 @@ #include <debug.h> #include <gicv3.h> #include <mmio.h> +#include <marvell_plat_priv.h> #include <platform.h> #include <plat_marvell.h> -#include <plat_private.h> -#define MVEBU_CCU_RVBAR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ - (0x400 * clus) + 0x240 + (cpu * 0x4)) -#define MVEBU_CCU_PRCR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ - (0x400 * clus) + 0x250 + (cpu * 0x4)) +#define MVEBU_CCU_RVBAR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ + (0x400 * clus) + 0x240 + (cpu * 0x4)) +#define MVEBU_CCU_PRCR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ + (0x400 * clus) + 0x250 + (cpu * 0x4)) -#define MVEBU_RFU_GLOBL_SW_RST 0x184 +#define MVEBU_RFU_GLOBL_SW_RST 0x184 int ap_init_status[PLAT_MARVELL_NORTHB_COUNT]; @@ -37,7 +37,8 @@ static int plat_marvell_cpu_on(u_register_t mpidr) cpu_id = MPIDR_CPU_ID_GET(mpidr); /* Set the cpu start address to BL1 entry point (align to 0x10000) */ - mmio_write_32(MVEBU_CCU_RVBAR(ap_id, clust_id, cpu_id), PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); + mmio_write_32(MVEBU_CCU_RVBAR(ap_id, clust_id, cpu_id), + PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); /* Get the cpu out of reset */ mmio_write_32(MVEBU_CCU_PRCR(ap_id, clust_id, cpu_id), 0x10001); @@ -165,7 +166,7 @@ static void a8kp_pwr_domain_on_finish(const psci_power_state_t *target_state) } /* arch specific configuration */ - psci_arch_init(ap_id); + marvell_psci_arch_init(ap_id); /* Per-CPU interrupt initialization */ plat_marvell_gic_pcpu_init(); @@ -180,7 +181,8 @@ static void a8kp_pwr_domain_on_finish(const psci_power_state_t *target_state) * context. Need to implement a separate suspend finisher. ***************************************************************************** */ -static void a8kp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +static void a8kp_pwr_domain_suspend_finish(const psci_power_state_t + *target_state) { ERROR("%s: needs to be implemented\n", __func__); panic(); @@ -208,9 +210,6 @@ static void __dead2 a8kp_system_off(void) { ERROR("%s: needs to be implemented\n", __func__); panic(); - wfi(); - ERROR("%s: operation not handled.\n", __func__); - panic(); } void plat_marvell_system_reset(void) diff --git a/plat/marvell/a8k-p/common/plat_pm_trace.c b/plat/marvell/a8k-p/common/plat_pm_trace.c index 0a2d343b..03cb4e19 100644 --- a/plat/marvell/a8k-p/common/plat_pm_trace.c +++ b/plat/marvell/a8k-p/common/plat_pm_trace.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a3900/board/dram_port.c b/plat/marvell/a8k/a3900/board/dram_port.c index ba25e55b..9622fce6 100644 --- a/plat/marvell/a8k/a3900/board/dram_port.c +++ b/plat/marvell/a8k/a3900/board/dram_port.c @@ -15,7 +15,7 @@ * based on information recieved from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { NOTICE("Gathering DRAM information\n"); } @@ -53,9 +53,9 @@ struct mv_ddr_iface dram_iface_ap0 = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ - MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ + { /* electrical configuration */ + { /* memory electrical configuration */ + MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ @@ -66,7 +66,7 @@ struct mv_ddr_iface dram_iface_ap0 = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -80,7 +80,7 @@ struct mv_ddr_iface dram_iface_ap0 = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ + { /* mac electrical configuration */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ MV_DDR_ODT_CFG_NORMAL /* odtcfg_read */ diff --git a/plat/marvell/a8k/a3900/board/marvell_plat_config.c b/plat/marvell/a8k/a3900/board/marvell_plat_config.c index 9d1681f0..7b91e50c 100644 --- a/plat/marvell/a8k/a3900/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a3900/board/marvell_plat_config.c @@ -5,12 +5,13 @@ * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -19,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -53,13 +55,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -77,10 +80,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000c0000000, 0x30000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -104,10 +108,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a3900/plat_def.h b/plat/marvell/a8k/a3900/mvebu_def.h index 075ea9da..075ea9da 100644 --- a/plat/marvell/a8k/a3900/plat_def.h +++ b/plat/marvell/a8k/a3900/mvebu_def.h diff --git a/plat/marvell/a8k/a3900_z1/board/dram_port.c b/plat/marvell/a8k/a3900_z1/board/dram_port.c index 4acff01d..cd8669eb 100644 --- a/plat/marvell/a8k/a3900_z1/board/dram_port.c +++ b/plat/marvell/a8k/a3900_z1/board/dram_port.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -14,9 +14,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - NOTICE("Gathering DRAM information\n"); } /* @@ -47,12 +46,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +59,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +73,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c b/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c index 708bca16..f1968c4e 100644 --- a/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -52,13 +55,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -76,10 +80,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000c0000000, 0x30000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -103,10 +108,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a3900_z1/plat_def.h b/plat/marvell/a8k/a3900_z1/mvebu_def.h index ea74303d..713ce55f 100644 --- a/plat/marvell/a8k/a3900_z1/plat_def.h +++ b/plat/marvell/a8k/a3900_z1/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a3900_z1/platform.mk b/plat/marvell/a8k/a3900_z1/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a3900_z1/platform.mk +++ b/plat/marvell/a8k/a3900_z1/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0/board/dram_port.c b/plat/marvell/a8k/a70x0/board/dram_port.c index b871a29e..c6702589 100644 --- a/plat/marvell/a8k/a70x0/board/dram_port.c +++ b/plat/marvell/a8k/a70x0/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -11,12 +12,11 @@ /* * This function may modify the default DRAM parameters - * based on information recieved from SPD or bootloader + * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +74,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c index 6d904fec..d126f556 100644 --- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -21,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -51,13 +54,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -80,10 +84,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f9000000, 0x1000000, RUNIT_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -108,10 +113,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -130,7 +136,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a70x0/plat_def.h b/plat/marvell/a8k/a70x0/mvebu_def.h index 129d9332..a7c5abbb 100644 --- a/plat/marvell/a8k/a70x0/plat_def.h +++ b/plat/marvell/a8k/a70x0/mvebu_def.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a70x0/platform.mk b/plat/marvell/a8k/a70x0/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0/platform.mk +++ b/plat/marvell/a8k/a70x0/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_amc/board/dram_port.c b/plat/marvell/a8k/a70x0_amc/board/dram_port.c index 8481fa7e..ab1df465 100644 --- a/plat/marvell/a8k/a70x0_amc/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_amc/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -14,9 +15,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +74,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c index d3bcee60..f8a1c40b 100644 --- a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -48,13 +51,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -71,10 +75,11 @@ struct addr_map_win iob_memory_map[] = { {0x0000000800000000, 0x200000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -99,10 +104,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -127,7 +133,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a70x0_amc/plat_def.h b/plat/marvell/a8k/a70x0_amc/mvebu_def.h index e8bbc154..5c665528 100644 --- a/plat/marvell/a8k/a70x0_amc/plat_def.h +++ b/plat/marvell/a8k/a70x0_amc/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ @@ -13,7 +14,7 @@ /*********************************************************************** * Required platform porting definitions common to all - * Mangement Compute SubSystems (MSS) + * Management Compute SubSystems (MSS) *********************************************************************** */ /* @@ -23,7 +24,7 @@ * it is discarded and BL31 is loaded over the top. */ #ifdef SCP_IMAGE -#define SCP_BL2_BASE BL31_BASE +#define SCP_BL2_BASE BL31_BASE #endif diff --git a/plat/marvell/a8k/a70x0_amc/platform.mk b/plat/marvell/a8k/a70x0_amc/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0_amc/platform.mk +++ b/plat/marvell/a8k/a70x0_amc/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_cust/board/dram_port.c b/plat/marvell/a8k/a70x0_cust/board/dram_port.c index fdcb0bfc..1acf742e 100644 --- a/plat/marvell/a8k/a70x0_cust/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_cust/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* @@ -40,12 +41,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -53,7 +54,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -67,10 +68,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -95,7 +96,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c index 9c7d6c20..ea133b6f 100644 --- a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -20,13 +22,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_DEV_CS0_ID}, /* Device Bus window */ }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -50,13 +53,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -75,10 +79,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f6000000, 0x1000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -101,10 +106,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a70x0_cust/plat_def.h b/plat/marvell/a8k/a70x0_cust/mvebu_def.h index 419ae84e..026bc61b 100644 --- a/plat/marvell/a8k/a70x0_cust/plat_def.h +++ b/plat/marvell/a8k/a70x0_cust/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a70x0_cust/platform.mk b/plat/marvell/a8k/a70x0_cust/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0_cust/platform.mk +++ b/plat/marvell/a8k/a70x0_cust/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c index 44488372..fccc532f 100644 --- a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -14,9 +15,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,7 +74,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ + { /* mac electrical configuration */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ diff --git a/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c index 0b7996a9..aa13c38f 100644 --- a/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> +#include <pci_ep.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -19,7 +21,8 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) @@ -49,7 +52,8 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) @@ -74,7 +78,8 @@ struct addr_map_win iob_memory_map[] = { {0x0000008000000000, 0x80000000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); @@ -101,7 +106,8 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); diff --git a/plat/marvell/a8k/a70x0_pcac/plat_def.h b/plat/marvell/a8k/a70x0_pcac/mvebu_def.h index 5f227133..cd0cdc15 100644 --- a/plat/marvell/a8k/a70x0_pcac/plat_def.h +++ b/plat/marvell/a8k/a70x0_pcac/mvebu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_pcac/platform.mk b/plat/marvell/a8k/a70x0_pcac/platform.mk index bc8c878f..c7d44f19 100644 --- a/plat/marvell/a8k/a70x0_pcac/platform.mk +++ b/plat/marvell/a8k/a70x0_pcac/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c index a1eff474..54c4883c 100644 --- a/plat/marvell/a8k/a80x0/board/dram_port.c +++ b/plat/marvell/a8k/a80x0/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) @@ -54,12 +55,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_SPD, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -67,7 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -81,10 +82,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -117,7 +118,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c index 65684434..836c9b40 100644 --- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -60,13 +62,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -100,16 +103,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -138,10 +142,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -161,7 +166,7 @@ struct power_off_method pm_cfg = { .cfg.gpio.delay_ms = 10, }; -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { /* Return the PM configurations */ return &pm_cfg; @@ -182,7 +187,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/plat_def.h b/plat/marvell/a8k/a80x0/mvebu_def.h index 7686aa20..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/plat_def.h +++ b/plat/marvell/a8k/a80x0/mvebu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/a8k/a80x0/platform.mk index 4b96ae3f..00d24b27 100644 --- a/plat/marvell/a8k/a80x0/platform.mk +++ b/plat/marvell/a8k/a80x0/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c b/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c index 7b9e4ab5..8eb8810e 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) @@ -54,12 +55,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -67,7 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -81,10 +82,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -117,7 +118,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c index a154fb0f..c0742b0e 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,7 +23,8 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) @@ -60,7 +62,8 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) @@ -98,7 +101,8 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): @@ -134,7 +138,8 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; *size = ARRAY_SIZE(ccu_memory_map); diff --git a/plat/marvell/a8k/a80x0_mcbin/plat_def.h b/plat/marvell/a8k/a80x0_32bit_ddr/mvebu_def.h index 3fb268cf..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0_mcbin/plat_def.h +++ b/plat/marvell/a8k/a80x0_32bit_ddr/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk index 142d987b..34818c13 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk +++ b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk @@ -1,9 +1,16 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses +PCI_EP_SUPPORT := 0 + +DOIMAGE_SEC := tools/doimage/secure/sec_img_8K.cfg + +MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c + + CP_NUM := 2 $(eval $(call add_define,CP_NUM)) diff --git a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c index b0150086..4be98f7b 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_CP_MPP_CTRL37_OFFS 20 @@ -48,12 +49,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_SPD, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -61,7 +62,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -75,10 +76,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -108,7 +109,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c index fbe7ce9e..384d0f54 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c @@ -1,18 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +#include <armada_common.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_config.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -55,13 +56,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -93,13 +95,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -133,16 +136,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -171,10 +175,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -185,7 +190,7 @@ int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t * SKIP IMAGE Configuration ***************************************************************************** */ -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* No recovery button on A8k-MCBIN board */ return NULL; diff --git a/plat/marvell/a8k/a80x0/plat_def.h b/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h index 8b98cc70..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0/plat_def.h +++ b/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a80x0_mcbin/platform.mk b/plat/marvell/a8k/a80x0_mcbin/platform.mk index 667f1d27..3749c378 100644 --- a/plat/marvell/a8k/a80x0_mcbin/platform.mk +++ b/plat/marvell/a8k/a80x0_mcbin/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c index 4c836707..e4acc98c 100644 --- a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -7,10 +7,10 @@ #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> +#include <mvebu_def.h> #include <mmio.h> #include <mv_ddr_if.h> #include <plat_marvell.h> -#include <plat_def.h> /* * This struct provides the DRAM training code with @@ -40,12 +40,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -53,7 +53,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -67,10 +67,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -86,6 +86,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { } diff --git a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c index 833ba7c7..2c10ca88 100644 --- a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c @@ -1,15 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> +#include <pci_ep.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +21,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -50,13 +54,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -72,12 +77,13 @@ struct addr_map_win iob_memory_map_cp0[] = { {0x0000008000000000, 0x800000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *size = 0; @@ -109,10 +115,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a80x0_ocp/plat_def.h b/plat/marvell/a8k/a80x0_ocp/mvebu_def.h index 51b0ee8f..51b0ee8f 100644 --- a/plat/marvell/a8k/a80x0_ocp/plat_def.h +++ b/plat/marvell/a8k/a80x0_ocp/mvebu_def.h diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk index 64886ea4..b032b19d 100644 --- a/plat/marvell/a8k/common/a8k_common.mk +++ b/plat/marvell/a8k/common/a8k_common.mk @@ -13,6 +13,8 @@ PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common MARVELL_DRV_BASE := drivers/marvell MARVELL_COMMON_BASE := plat/marvell/common +$(eval $(call add_define,PLAT_FAMILY)) + ERRATA_A72_859971 := 1 # Enable MSS support for a8k family @@ -61,15 +63,15 @@ BLE_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \ MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c -BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \ - $(MARVELL_MOCHI_DRV) \ - $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ - $(PLAT_COMMON_BASE)/plat_pm.c \ - $(MARVELL_DRV_BASE)/aro.c \ - $(MARVELL_DRV_BASE)/thermal.c \ - $(PLAT_COMMON_BASE)/plat_thermal.c \ - $(BLE_PORTING_SOURCES) \ - $(MARVELL_DRV_BASE)/ccu.c \ +BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \ + $(MARVELL_MOCHI_DRV) \ + $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ + $(PLAT_COMMON_BASE)/plat_pm.c \ + $(MARVELL_DRV_BASE)/aro.c \ + $(MARVELL_DRV_BASE)/thermal.c \ + $(PLAT_COMMON_BASE)/plat_thermal.c \ + $(BLE_PORTING_SOURCES) \ + $(MARVELL_DRV_BASE)/ccu.c \ $(MARVELL_DRV_BASE)/io_win.c ifeq (${PCI_EP_SUPPORT}, 1) diff --git a/plat/marvell/a8k/common/aarch64/a8k_common.c b/plat/marvell/a8k/common/aarch64/a8k_common.c index 86814320..b9e02cb9 100644 --- a/plat/marvell/a8k/common/aarch64/a8k_common.c +++ b/plat/marvell/a8k/common/aarch64/a8k_common.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/a8k/common/aarch64/plat_arch_config.c index 131421be..86673314 100644 --- a/plat/marvell/a8k/common/aarch64/plat_arch_config.c +++ b/plat/marvell/a8k/common/aarch64/plat_arch_config.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <platform.h> #include <arch_helpers.h> #include <mmio.h> @@ -16,7 +16,7 @@ #define MVEBU_IO_AFFINITY (0xF00) -void plat_enable_affinity(void) +static void plat_enable_affinity(void) { int cluster_id; int affinity; @@ -27,10 +27,10 @@ void plat_enable_affinity(void) mmio_write_32(CCU_HTC_ASET, affinity); /* set barier */ - __asm__ volatile("isb"); + isb(); } -void psci_arch_init(int die_index) +void marvell_psci_arch_init(int die_index) { #if LLC_ENABLE /* check if LLC is in exclusive mode diff --git a/plat/marvell/a8k/common/aarch64/plat_helpers.S b/plat/marvell/a8k/common/aarch64/plat_helpers.S index e6a8eed8..fadc4c26 100644 --- a/plat/marvell/a8k/common/aarch64/plat_helpers.S +++ b/plat/marvell/a8k/common/aarch64/plat_helpers.S @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <asm_macros.S> #include <platform_def.h> #include <marvell_pm.h> @@ -38,11 +38,12 @@ endfunc plat_secondary_cold_boot_setup * --------------------------------------------------------------------- */ func plat_get_my_entrypoint - mov_imm x0, PLAT_MARVELL_MAILBOX_BASE /* Read first word and compare it with magic num */ + /* Read first word and compare it with magic num */ + mov_imm x0, PLAT_MARVELL_MAILBOX_BASE ldr x1, [x0] mov_imm x2, MVEBU_MAILBOX_MAGIC_NUM cmp x1, x2 - beq warm_boot /* If compare failed, return 0, i.e. cold boot */ + beq warm_boot /* If compare failed, return 0, i.e. cold boot */ mov x0, #0 ret warm_boot: diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h index 80607d93..95f8c417 100644 --- a/plat/marvell/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/a8k/common/include/a8k_plat_def.h @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#ifndef __MVEBU_A8K_DEF_H__ -#define __MVEBU_A8K_DEF_H__ +#ifndef __A8K_PLAT_DEF_H__ +#define __A8K_PLAT_DEF_H__ #include <marvell_def.h> @@ -55,9 +55,11 @@ #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 0x440000 + ((n / 8) << 2)) #define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \ - (MVEBU_CP_REGS_BASE(cp_index) + 0x440100 + ((n > 32) ? 0x40 : 0x00)) + (MVEBU_CP_REGS_BASE(cp_index) + \ + 0x440100 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \ - (MVEBU_CP_REGS_BASE(cp_index) + 0x440104 + ((n > 32) ? 0x40 : 0x00)) + (MVEBU_CP_REGS_BASE(cp_index) + \ + 0x440104 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 0x440110 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2)) @@ -67,40 +69,47 @@ #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) #define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084) -#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + 0x20080 + ((win) * 0x8)) -#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + 0x20084 + ((win) * 0x8)) +#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ + 0x20080 + ((win) * 0x8)) +#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ + 0x20084 + ((win) * 0x8)) /* MCI indirect access definitions */ #define MCI_MAX_UNIT_ID 2 /* SoC RFU / IHBx4 Control */ -#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + 0x4218 + (unit_id * 0x20)) +#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \ + 0x4218 + (unit_id * 0x20)) #define MCI_REMAP_OFF_SHIFT 8 -#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + ((index) * 0x1000000)) +#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \ + ((index) * 0x1000000)) #define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000) #define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000) #define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000) #define MVEBU_CP_DFX_OFFSET (0x400200) -/******************************************************************************* +/***************************************************************************** * MVEBU memory map related constants - ******************************************************************************/ + ***************************************************************************** + */ /* Aggregate of all devices in the first GB */ #define DEVICE0_BASE MVEBU_REGS_BASE #define DEVICE0_SIZE 0x10000000 /******************************************************************************* * GIC-400 & interrupt handling related constants - ******************************************************************************/ + ***************************************************************************** + */ /* Base MVEBU compatible GIC memory map */ #define MVEBU_GICD_BASE 0x210000 #define MVEBU_GICC_BASE 0x220000 -/******************************************************************************* +/***************************************************************************** * AXI Configuration - ******************************************************************************/ + ***************************************************************************** + */ #define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4 #define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \ MVEBU_AXI_ATTR_ARCACHE_OFFSET) @@ -133,9 +142,9 @@ #define DOMAIN_OUTER_SHAREABLE 0x2 #define DOMAIN_SYSTEM_SHAREABLE 0x3 -/************************************************************************* +/************************************************************************ * Required platform porting definitions common to all - * Mangement Compute SubSystems (MSS) + * Management Compute SubSystems (MSS) ************************************************************************ */ /* diff --git a/plat/marvell/a8k/common/include/ddr_info.h b/plat/marvell/a8k/common/include/ddr_info.h index ae90dbd0..e19036a2 100644 --- a/plat/marvell/a8k/common/include/ddr_info.h +++ b/plat/marvell/a8k/common/include/ddr_info.h @@ -1,4 +1,3 @@ - /* * Copyright (C) 2018 Marvell International Ltd. * diff --git a/plat/marvell/a8k/common/include/plat_macros.S b/plat/marvell/a8k/common/include/plat_macros.S index b082208d..2a6ccf27 100644 --- a/plat/marvell/a8k/common/include/plat_macros.S +++ b/plat/marvell/a8k/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index ac65c662..45650ef6 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -11,7 +11,7 @@ #include <board_marvell_def.h> #include <gic_common.h> #include <interrupt_props.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ @@ -137,8 +137,8 @@ GIC_INTR_CFG_LEVEL) #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -191,8 +191,11 @@ /* System timer related constants */ #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 -/* Mailbox base address (note the lower memory space are reserved for BLE data) */ -#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE + 0x400) +/* Mailbox base address (note the lower memory space + * is reserved for BLE data) + */ +#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \ + + 0x400) #define PLAT_MARVELL_MAILBOX_SIZE 0x100 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/a8k/common/mss/mss_a8k.mk index 7ca9132f..58f23d8d 100644 --- a/plat/marvell/a8k/common/mss/mss_a8k.mk +++ b/plat/marvell/a8k/common/mss/mss_a8k.mk @@ -1,18 +1,18 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses # -PLAT_MARVELL := plat/marvell -A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss +PLAT_MARVELL := plat/marvell +A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c -PLAT_INCLUDES += -I$(A8K_MSS_SOURCE) +PLAT_INCLUDES += -I$(A8K_MSS_SOURCE) ifneq (${SCP_BL2},) # This define is used to inidcate the SCP image is present diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index df73a886..58a9472b 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -1,17 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <bl_common.h> #include <ccu.h> #include <cp110_setup.h> #include <debug.h> +#include <marvell_plat_priv.h> /* timer functionality */ #include <mmio.h> -#include <plat_config.h> #include <platform_def.h> -#include <plat_private.h> /* timer functionality */ #include "mss_scp_bootloader.h" @@ -53,7 +54,7 @@ static int bl2_plat_mmap_init(void) { int cfg_num, win_id, cfg_idx; - cfg_num = sizeof(ccu_mem_map) / sizeof(ccu_mem_map[0]); + cfg_num = ARRAY_SIZE(ccu_mem_map); /* CCU window-0 should not be counted - it's already used */ if (cfg_num > (MVEBU_CCU_MAX_WINS - 1)) { @@ -77,10 +78,11 @@ static int bl2_plat_mmap_init(void) return 0; } -/******************************************************************************* +/***************************************************************************** * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. * Return 0 on success, -1 otherwise. - ******************************************************************************/ + ***************************************************************************** + */ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info) { int ret; @@ -122,7 +124,8 @@ uint32_t bl2_plat_get_cp_count(int ap_idx) /* A8040: two CPs. * A7040: one CP. */ - if (revision == MVEBU_80X0_DEV_ID || revision == MVEBU_80X0_CP115_DEV_ID) + if (revision == MVEBU_80X0_DEV_ID || + revision == MVEBU_80X0_CP115_DEV_ID) return 2; else return 1; diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.c b/plat/marvell/a8k/common/mss/mss_pm_ipc.c index 0088f8c1..6ff4abcc 100644 --- a/plat/marvell/a8k/common/mss/mss_pm_ipc.c +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <debug.h> #include <mmio.h> #include <psci.h> @@ -12,14 +13,14 @@ #include <mss_pm_ipc.h> /* -** SISR is 32 bit interrupt register representing 32 interrupts -** -** +======+=============+=============+ -** + Bits + 31 + 30 - 00 + -** +======+=============+=============+ -** + Desc + MSS Msg Int + Reserved + -** +======+=============+=============+ -*/ + * SISR is 32 bit interrupt register representing 32 interrupts + * + * +======+=============+=============+ + * + Bits + 31 + 30 - 00 + + * +======+=============+=============+ + * + Desc + MSS Msg Int + Reserved + + * +======+=============+=============+ + */ #define MSS_SISR (MVEBU_REGS_BASE + 0x5800D0) #define MSS_SISTR (MVEBU_REGS_BASE + 0x5800D8) @@ -27,16 +28,20 @@ #define MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110) #define MSS_TRIGGER_TIMEOUT (1000) -/******************************************************************************* -* mss_pm_ipc_msg_send -* -* DESCRIPTION: create and transmit IPC message -*******************************************************************************/ -int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci_power_state_t *target_state) +/***************************************************************************** + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ***************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, + const psci_power_state_t *target_state) { /* Transmit IPC message */ #ifndef DISABLE_CLUSTER_LEVEL - mv_pm_ipc_msg_tx(channel_id, msg_id, (unsigned int)target_state->pwr_domain_state[MPIDR_AFFLVL1]); + mv_pm_ipc_msg_tx(channel_id, msg_id, + (unsigned int)target_state->pwr_domain_state[ + MPIDR_AFFLVL1]); #else mv_pm_ipc_msg_tx(channel_id, msg_id, 0); #endif @@ -44,11 +49,12 @@ int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci return 0; } -/******************************************************************************* -* mss_pm_ipc_msg_trigger -* -* DESCRIPTION: Trigger IPC message interrupt to MSS -*******************************************************************************/ +/***************************************************************************** + * mss_pm_ipc_msg_trigger + * + * DESCRIPTION: Trigger IPC message interrupt to MSS + ***************************************************************************** + */ int mss_pm_ipc_msg_trigger(void) { unsigned int timeout; @@ -65,7 +71,8 @@ int mss_pm_ipc_msg_trigger(void) /* check timeout */ t_end = mmio_read_32(MSS_TIMER_BASE); - timeout = ((t_start > t_end) ? (t_start - t_end) : (t_end - t_start)); + timeout = ((t_start > t_end) ? + (t_start - t_end) : (t_end - t_start)); if (timeout > MSS_TRIGGER_TIMEOUT) { ERROR("PM MSG Trigger Timeout\n"); break; diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.h b/plat/marvell/a8k/common/mss/mss_pm_ipc.h index b1b9cfc6..0f694570 100644 --- a/plat/marvell/a8k/common/mss/mss_pm_ipc.h +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -15,19 +15,20 @@ /***************************************************************************** -* mss_pm_ipc_msg_send -* -* DESCRIPTION: create and transmit IPC message -****************************************************************************** -*/ -int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci_power_state_t *target_state); + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ***************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, + const psci_power_state_t *target_state); /***************************************************************************** -* mss_pm_ipc_msg_trigger -* -* DESCRIPTION: Trigger IPC message interrupt to MSS -****************************************************************************** -*/ + * mss_pm_ipc_msg_trigger + * + * DESCRIPTION: Trigger IPC message interrupt to MSS + ***************************************************************************** + */ int mss_pm_ipc_msg_trigger(void); diff --git a/plat/marvell/a8k/common/plat_bl1_setup.c b/plat/marvell/a8k/common/plat_bl1_setup.c index ba8a4f78..5d851027 100644 --- a/plat/marvell/a8k/common/plat_bl1_setup.c +++ b/plat/marvell/a8k/common/plat_bl1_setup.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <mmio.h> #include <plat_marvell.h> diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c index 7d510645..7985e1d9 100644 --- a/plat/marvell/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/a8k/common/plat_bl31_setup.c @@ -1,19 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +#include <armada_common.h> #include <ap_setup.h> #include <cp110_setup.h> #include <debug.h> +#include <marvell_plat_priv.h> #include <marvell_pm.h> #include <mmio.h> #include <mci.h> -#include <plat_config.h> #include <plat_marvell.h> -#include <plat_private.h> #include <mc_trustzone/mc_trustzone.h> #include <mss_ipc_drv.h> @@ -57,7 +57,7 @@ void marvell_bl31_mss_init(void) (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; /* Check that the image was loaded successfully */ - if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGEMENT) { + if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) { NOTICE("MSS PM is not supported in this build\n"); return; } diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 359524e5..29d896a3 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -1,19 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ #include <ap_setup.h> +#include <armada_common.h> #include <aro.h> #include <ccu.h> #include <cp110_setup.h> #include <debug.h> #include <io_win.h> #include <mv_ddr_if.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* Register for skip image use */ @@ -84,18 +84,18 @@ #define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET) /* - - AVS work points in the LD0 eFuse: - SVC1 work point: LD0[88:81] - SVC2 work point: LD0[96:89] - SVC3 work point: LD0[104:97] - SVC4 work point: LD0[112:105] - - Identification information in the LD-0 eFuse: - DRO: LD0[74:65] - Not used by the SW - Revision: LD0[78:75] - Not used by the SW - Bin: LD0[80:79] - Not used by the SW - SW Revision: LD0[115:113] - Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 - resulting in 2 CPUs active only (7020) + * - AVS work points in the LD0 eFuse: + * SVC1 work point: LD0[88:81] + * SVC2 work point: LD0[96:89] + * SVC3 work point: LD0[104:97] + * SVC4 work point: LD0[112:105] + * - Identification information in the LD-0 eFuse: + * DRO: LD0[74:65] - Not used by the SW + * Revision: LD0[78:75] - Not used by the SW + * Bin: LD0[80:79] - Not used by the SW + * SW Revision: LD0[115:113] + * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 + * resulting in 2 CPUs active only (7020) */ #define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) /* Bits [94:63] - 32 data bits total */ @@ -128,7 +128,8 @@ static unsigned int ble_get_ap_type(void) unsigned int chip_rev_id; chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); - chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); + chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> + GWD_IIDR2_CHIP_ID_OFFSET); return chip_rev_id; } @@ -136,15 +137,15 @@ static unsigned int ble_get_ap_type(void) /****************************************************************************** * The routine allows to save the CCU and IO windows configuration during DRAM * setup and restore them afterwards before exiting the BLE stage. - * Such window configuration is requred since not all default settings coming - * from the HW and the BootROM allow access to periferals connected to + * Such window configuration is required since not all default settings coming + * from the HW and the BootROM allow access to peripherals connected to * all available CPn components. * For instance, when the boot device is located on CP0, the IO window to CP1 * is not opened automatically by the HW and if the DRAM SPD is located on CP1 * i2c channel, it cannot be read at BLE stage. * Therefore the DRAM init procedure have to provide access to all available - * CPn periferals during the BLE stage by setting the CCU IO window to all CPn - * addresses and by enabling the IO windows accordingly. + * CPn peripherals during the BLE stage by setting the CCU IO window to all + * CPnph addresses and by enabling the IO windows accordingly. * Additionally this function configures the CCU GCR to DRAM, which allows * usage or more than 4GB DRAM as it configured by the default CCU DRAM window. * @@ -163,28 +164,30 @@ static void ble_plat_mmap_config(int restore) /* Restore CCU */ iow_restore_win_all(MVEBU_AP0); return; - } else { + } + /* Store original values */ ccu_save_win_all(MVEBU_AP0); /* Save CCU */ iow_save_win_all(MVEBU_AP0); - } init_ccu(MVEBU_AP0); /* The configuration saved, now all the changes can be done */ init_io_win(MVEBU_AP0); } -/****************************************************************************** +/**************************************************************************** * Setup Adaptive Voltage Switching - this is required for some platforms - *****************************************************************************/ + **************************************************************************** + */ static void ble_plat_avs_config(void) { uint32_t reg_val, device_id; /* Due to a bug in A3900 device_id we need a special handling here */ if (ble_get_ap_type() == CHIP_ID_AP807) { - VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n", AVS_A3900_CLK_VALUE); + VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n", + AVS_A3900_CLK_VALUE); mmio_write_32(AVS_EN_CTRL_REG, AVS_A3900_CLK_VALUE); return; } @@ -213,16 +216,18 @@ static void ble_plat_avs_config(void) } } -/****************************************************************************** +/**************************************************************************** * SVC flow - v0.10 - * The feature is inteded to configure AVS value according to eFuse values + * The feature is intended to configure AVS value according to eFuse values * that are burned individually for each SoC during the test process. - * Primary AVS value is stored in HD efuse and processed on power on by the HW engine + * Primary AVS value is stored in HD efuse and processed on power on + * by the HW engine * Secondary AVS value is located in LD efuse and contains 4 work points for * various CPU frequencies. * The Secondary AVS value is only taken into account if the SW Revision stored * in the efuse is greater than 0 and the CPU is running in a certain speed. - *****************************************************************************/ + **************************************************************************** + */ static void ble_plat_svc_config(void) { uint32_t reg_val, avs_workpoint, freq_pidi_mode; @@ -468,7 +473,7 @@ static int ble_skip_current_image(void) struct skip_image *skip_im; /*fetching skip image info*/ - skip_im = (struct skip_image *)plat_get_skip_image_data(); + skip_im = (struct skip_image *)plat_marvell_get_skip_image_data(); if (skip_im == NULL) return 0; @@ -526,7 +531,7 @@ int ble_plat_setup(int *skip) /* * Save the current CCU configuration and make required changes: * - Allow access to DRAM larger than 4GB - * - Open memory access to all CPn periferals + * - Open memory access to all CPn peripherals */ ble_plat_mmap_config(MMAP_SAVE_AND_CONFIG); @@ -557,7 +562,7 @@ int ble_plat_setup(int *skip) ap_ble_init(); /* Update DRAM topology (scan DIMM SPDs) */ - plat_dram_update_topology(); + plat_marvell_dram_update_topology(); /* Kick it in */ ret = dram_init(); diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index 7fcbfa36..f57d18a6 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include <armada_common.h> #include <assert.h> #include <bakery_lock.h> #include <debug.h> @@ -15,7 +16,6 @@ #include <marvell_pm.h> #include <mmio.h> #include <mss_pm_ipc.h> -#include <plat_config.h> #include <plat_marvell.h> #include <platform.h> #include <plat_pm_trace.h> @@ -58,7 +58,7 @@ DEFINE_BAKERY_LOCK(pm_sys_lock); /* Weak definitions may be overridden in specific board */ -#pragma weak plat_get_pm_cfg +#pragma weak plat_marvell_get_pm_cfg /* AP806 CPU power down /power up definitions */ enum CPU_ID { @@ -70,9 +70,11 @@ enum CPU_ID { #define REG_WR_VALIDATE_TIMEOUT (2000) -#define FEATURE_DISABLE_STATUS_REG (MVEBU_REGS_BASE + 0x6F8230) +#define FEATURE_DISABLE_STATUS_REG \ + (MVEBU_REGS_BASE + 0x6F8230) #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET 4 -#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) +#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK \ + (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) #ifdef MVEBU_SOC_AP807 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1 @@ -82,21 +84,29 @@ enum CPU_ID { #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31 #endif -#define PWRC_CPUN_CR_REG(cpu_id) (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) -#define PWRC_CPUN_CR_PWR_DN_RQ_MASK (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) +#define PWRC_CPUN_CR_REG(cpu_id) \ + (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) +#define PWRC_CPUN_CR_PWR_DN_RQ_MASK \ + (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) #define PWRC_CPUN_CR_ISO_ENABLE_OFFSET 16 -#define PWRC_CPUN_CR_ISO_ENABLE_MASK (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) -#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) +#define PWRC_CPUN_CR_ISO_ENABLE_MASK \ + (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) +#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \ + (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) -#define CCU_B_PRCRN_REG(cpu_id) (MVEBU_REGS_BASE + 0x1A50 + \ +#define CCU_B_PRCRN_REG(cpu_id) \ + (MVEBU_REGS_BASE + 0x1A50 + \ ((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4)) #define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET 0 -#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) +#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK \ + (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) /* power switch fingers */ -#define AP807_PWRC_LDO_CR0_REG (MVEBU_REGS_BASE + 0x680000 + 0x100) +#define AP807_PWRC_LDO_CR0_REG \ + (MVEBU_REGS_BASE + 0x680000 + 0x100) #define AP807_PWRC_LDO_CR0_OFFSET 16 -#define AP807_PWRC_LDO_CR0_MASK (0xff << AP807_PWRC_LDO_CR0_OFFSET) +#define AP807_PWRC_LDO_CR0_MASK \ + (0xff << AP807_PWRC_LDO_CR0_OFFSET) #define AP807_PWRC_LDO_CR0_VAL 0xfd /* @@ -456,7 +466,7 @@ static void a8k_pwr_domain_off(const psci_power_state_t *target_state) } /* Get PM config to power off the SoC */ -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { return NULL; } @@ -468,9 +478,9 @@ void *plat_get_pm_cfg(void) * the system recovery * */ -static void plat_exit_bootrom(void) +static void plat_marvell_exit_bootrom(void) { - exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); + marvell_exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); } /* @@ -607,12 +617,13 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) gicv2_cpuif_disable(); mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; - mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_exit_bootrom; + mailbox[MBOX_IDX_ROM_EXIT_ADDR] = + (uintptr_t)&plat_marvell_exit_bootrom; #if PLAT_MARVELL_SHARED_RAM_CACHED flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + - MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), - 2 * sizeof(uintptr_t)); + MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), + 2 * sizeof(uintptr_t)); #endif /* Flush and disable LLC before going off-power */ llc_disable(0); @@ -636,7 +647,7 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ gicv2_pcpu_distif_init(); @@ -656,11 +667,12 @@ static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) * context. Need to implement a separate suspend finisher. ***************************************************************************** */ -static void a8k_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +static void a8k_pwr_domain_suspend_finish( + const psci_power_state_t *target_state) { if (is_pm_fw_running()) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ gicv2_cpuif_enable(); @@ -714,7 +726,7 @@ static void __dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { const struct power_off_method *pm_cfg = - (const struct power_off_method *)plat_get_pm_cfg(); + (const struct power_off_method *)plat_marvell_get_pm_cfg(); unsigned int srcmd; unsigned int sdram_reg; register_t gpio_data = 0, gpio_addr = 0; @@ -782,9 +794,6 @@ static void __dead2 a8k_system_off(void) { ERROR("%s: needs to be implemented\n", __func__); panic(); - wfi(); - ERROR("%s: operation not handled.\n", __func__); - panic(); } void plat_marvell_system_reset(void) diff --git a/plat/marvell/a8k/common/plat_pm_trace.c b/plat/marvell/a8k/common/plat_pm_trace.c index b797f77e..683e56f6 100644 --- a/plat/marvell/a8k/common/plat_pm_trace.c +++ b/plat/marvell/a8k/common/plat_pm_trace.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <mmio.h> #include <mss_mem.h> #include <platform.h> diff --git a/plat/marvell/a8k/common/plat_thermal.c b/plat/marvell/a8k/common/plat_thermal.c index fe6de66b..02fe8209 100644 --- a/plat/marvell/a8k/common/plat_thermal.c +++ b/plat/marvell/a8k/common/plat_thermal.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -8,22 +8,27 @@ #include <debug.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <thermal.h> #define THERMAL_TIMEOUT 1200 #define THERMAL_SEN_CTRL_LSB_STRT_OFFSET 0 -#define THERMAL_SEN_CTRL_LSB_STRT_MASK (0x1 << THERMAL_SEN_CTRL_LSB_STRT_OFFSET) +#define THERMAL_SEN_CTRL_LSB_STRT_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_STRT_OFFSET) #define THERMAL_SEN_CTRL_LSB_RST_OFFSET 1 -#define THERMAL_SEN_CTRL_LSB_RST_MASK (0x1 << THERMAL_SEN_CTRL_LSB_RST_OFFSET) +#define THERMAL_SEN_CTRL_LSB_RST_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_RST_OFFSET) #define THERMAL_SEN_CTRL_LSB_EN_OFFSET 2 -#define THERMAL_SEN_CTRL_LSB_EN_MASK (0x1 << THERMAL_SEN_CTRL_LSB_EN_OFFSET) +#define THERMAL_SEN_CTRL_LSB_EN_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_EN_OFFSET) #define THERMAL_SEN_CTRL_STATS_VALID_OFFSET 16 -#define THERMAL_SEN_CTRL_STATS_VALID_MASK (0x1 << THERMAL_SEN_CTRL_STATS_VALID_OFFSET) +#define THERMAL_SEN_CTRL_STATS_VALID_MASK \ + (0x1 << THERMAL_SEN_CTRL_STATS_VALID_OFFSET) #define THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET 0 -#define THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK (0x3FF << THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET) +#define THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK \ + (0x3FF << THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET) #define THERMAL_SEN_OUTPUT_MSB 512 #define THERMAL_SEN_OUTPUT_COMP 1024 @@ -55,7 +60,8 @@ static int ext_tsen_probe(struct tsen_config *tsen_cfg) mmio_write_32((uintptr_t)&base->ext_tsen_ctrl_lsb, reg); reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); - while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && timeout < THERMAL_TIMEOUT) { + while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && + timeout < THERMAL_TIMEOUT) { udelay(100); reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); timeout++; @@ -68,7 +74,7 @@ static int ext_tsen_probe(struct tsen_config *tsen_cfg) tsen_cfg->tsen_ready = 1; - INFO("thermal sensor was initialized\n"); + VERBOSE("thermal sensor was initialized\n"); return 0; } @@ -85,7 +91,8 @@ static int ext_tsen_read(struct tsen_config *tsen_cfg, int *temp) base = (struct tsen_regs *)tsen_cfg->regs_base; reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); - reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET); + reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> + THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET); /* * TSEN output format is signed as a 2s complement number diff --git a/plat/marvell/common/aarch64/marvell_common.c b/plat/marvell/common/aarch64/marvell_common.c index fe662c5c..abc501a9 100644 --- a/plat/marvell/common/aarch64/marvell_common.c +++ b/plat/marvell/common/aarch64/marvell_common.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch.h> #include <arch_helpers.h> #include <assert.h> @@ -90,9 +86,10 @@ unsigned long plat_get_ns_image_entrypoint(void) return PLAT_MARVELL_NS_IMAGE_OFFSET; } -/******************************************************************************* +/***************************************************************************** * Gets SPSR for BL32 entry - ******************************************************************************/ + ***************************************************************************** + */ uint32_t marvell_get_spsr_for_bl32_entry(void) { /* @@ -102,9 +99,10 @@ uint32_t marvell_get_spsr_for_bl32_entry(void) return 0; } -/******************************************************************************* +/***************************************************************************** * Gets SPSR for BL33 entry - ******************************************************************************/ + ***************************************************************************** + */ uint32_t marvell_get_spsr_for_bl33_entry(void) { unsigned long el_status; @@ -126,9 +124,10 @@ uint32_t marvell_get_spsr_for_bl33_entry(void) return spsr; } -/******************************************************************************* +/***************************************************************************** * Returns ARM platform specific memory map regions. - ******************************************************************************/ + ***************************************************************************** + */ const mmap_region_t *plat_marvell_get_mmap(void) { return plat_marvell_mmap; diff --git a/plat/marvell/common/aarch64/marvell_helpers.S b/plat/marvell/common/aarch64/marvell_helpers.S index 45bd2a2c..a3dc917c 100644 --- a/plat/marvell/common/aarch64/marvell_helpers.S +++ b/plat/marvell/common/aarch64/marvell_helpers.S @@ -1,39 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ + #include <asm_macros.S> +#include <cortex_a72.h> #include <marvell_def.h> #include <platform_def.h> #ifndef PLAT_a3700 @@ -52,7 +25,8 @@ .globl disable_sram .globl disable_icache .globl invalidate_icache_all - .globl exit_bootrom + .globl marvell_exit_bootrom + .globl ca72_l2_enable_unique_clean /* ----------------------------------------------------- * unsigned int plat_my_core_pos(void) @@ -202,7 +176,7 @@ endfunc disable_sram * Disable and invalidate the icache * ----------------------------------------------------- */ -func exit_bootrom +func marvell_exit_bootrom /* Save the system restore address */ mov x28, x0 @@ -234,4 +208,16 @@ func exit_bootrom mov x0, x28 br x0 -endfunc exit_bootrom +endfunc marvell_exit_bootrom + + /* + * Enable L2 UniqueClean evictions with data + */ +func ca72_l2_enable_unique_clean + + mrs x0, CORTEX_A72_L2ACTLR_EL1 + orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN + msr CORTEX_A72_L2ACTLR_EL1, x0 + + ret +endfunc ca72_l2_enable_unique_clean diff --git a/plat/marvell/common/marvell_bl1_setup.c b/plat/marvell/common/marvell_bl1_setup.c index 73ebd21c..7b498dd0 100644 --- a/plat/marvell/common/marvell_bl1_setup.c +++ b/plat/marvell/common/marvell_bl1_setup.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <bl1.h> #include <bl1/bl1_private.h> #include <bl_common.h> diff --git a/plat/marvell/common/marvell_bl2_setup.c b/plat/marvell/common/marvell_bl2_setup.c index 6a91b572..7c87ce33 100644 --- a/plat/marvell/common/marvell_bl2_setup.c +++ b/plat/marvell/common/marvell_bl2_setup.c @@ -1,14 +1,9 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ #include <arch_helpers.h> #include <bl_common.h> @@ -22,11 +17,12 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); -/******************************************************************************* +/***************************************************************************** * This structure represents the superset of information that is passed to * BL31, e.g. while passing control to it from BL2, bl31_params - * and other platform specific params - ******************************************************************************/ + * and other platform specific parameters + ***************************************************************************** + */ typedef struct bl2_to_bl31_params_mem { bl31_params_t bl31_params; image_info_t bl31_image_info; @@ -62,7 +58,7 @@ meminfo_t *bl2_plat_sec_mem_layout(void) return &bl2_tzram_layout; } -/******************************************************************************* +/***************************************************************************** * This function assigns a pointer to the memory that the platform has kept * aside to pass platform specific and trusted firmware related information * to BL31. This memory is allocated by allocating memory to @@ -70,7 +66,8 @@ meminfo_t *bl2_plat_sec_mem_layout(void) * structure whose information is passed to BL31 * NOTE: This function should be called only once and should be done * before generating params to BL31 - ******************************************************************************/ + ***************************************************************************** + */ bl31_params_t *bl2_plat_get_bl31_params(void) { bl31_params_t *bl2_to_bl31_params; @@ -122,10 +119,11 @@ void bl2_plat_flush_bl31_params(void) sizeof(bl2_to_bl31_params_mem_t)); } -/******************************************************************************* +/***************************************************************************** * This function returns a pointer to the shared memory that the platform * has kept to point to entry point information of BL31 to BL2 - ******************************************************************************/ + ***************************************************************************** + */ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { #if DEBUG @@ -135,11 +133,12 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) return &bl31_params_mem.bl31_ep_info; } -/******************************************************************************* +/***************************************************************************** * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted SRAM. * Copy it to a safe location before its reclaimed by later BL2 functionality. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ @@ -164,10 +163,11 @@ void bl2_platform_setup(void) /* Nothing to do */ } -/******************************************************************************* +/***************************************************************************** * Perform the very early platform specific architectural setup here. At the * moment this is only initializes the mmu in a quick and dirty way. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl2_plat_arch_setup(void) { marvell_setup_page_tables(bl2_tzram_layout.total_base, @@ -189,32 +189,35 @@ void bl2_plat_arch_setup(void) marvell_bl2_plat_arch_setup(); } -/******************************************************************************* +/***************************************************************************** * Populate the extents of memory available for loading SCP_BL2 (if used), * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) { *scp_bl2_meminfo = bl2_tzram_layout; } -/******************************************************************************* +/***************************************************************************** * Before calling this function BL31 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL31 and set SPSR and security state. * On MARVELL std. platforms we only set the security state of the entrypoint - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, - entry_point_info_t *bl31_ep_info) + entry_point_info_t *bl31_ep_info) { SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } -/******************************************************************************* +/***************************************************************************** * Populate the extents of memory available for loading BL32 - ******************************************************************************/ + ***************************************************************************** + */ #ifdef BL32_BASE void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) { @@ -230,36 +233,39 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) } #endif -/******************************************************************************* +/***************************************************************************** * Before calling this function BL32 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL32 and set SPSR and security state. * On MARVELL std. platforms we only set the security state of the entrypoint - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, - entry_point_info_t *bl32_ep_info) + entry_point_info_t *bl32_ep_info) { SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); bl32_ep_info->spsr = marvell_get_spsr_for_bl32_entry(); } -/******************************************************************************* +/***************************************************************************** * Before calling this function BL33 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL33 and set SPSR and security state. * On MARVELL std. platforms we only set the security state of the entrypoint - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_set_bl33_ep_info(image_info_t *image, - entry_point_info_t *bl33_ep_info) + entry_point_info_t *bl33_ep_info) { SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); bl33_ep_info->spsr = marvell_get_spsr_for_bl33_entry(); } -/******************************************************************************* +/***************************************************************************** * Populate the extents of memory available for loading BL33 - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) { bl33_meminfo->total_base = MARVELL_DRAM_BASE; diff --git a/plat/marvell/common/marvell_bl31_setup.c b/plat/marvell/common/marvell_bl31_setup.c index d281356a..a74816b7 100644 --- a/plat/marvell/common/marvell_bl31_setup.c +++ b/plat/marvell/common/marvell_bl31_setup.c @@ -1,21 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch.h> #include <assert.h> #include <console.h> #include <debug.h> #include <marvell_def.h> +#include <marvell_plat_priv.h> #include <plat_marvell.h> -#include <plat_private.h> #include <platform.h> #ifdef USE_CCI @@ -45,12 +41,13 @@ static entry_point_info_t bl33_image_ep_info; #pragma weak bl31_plat_get_next_image_ep_info #pragma weak plat_get_syscnt_freq2 -/******************************************************************************* +/***************************************************************************** * Return a pointer to the 'entry_point_info' structure of the next image for * the security state specified. BL33 corresponds to the non-secure image type * while BL32 corresponds to the secure image type. A NULL pointer is returned * if the image does not exist. - ******************************************************************************/ + ***************************************************************************** + */ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { entry_point_info_t *next_image_info; @@ -62,14 +59,15 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) return next_image_info; } -/******************************************************************************* +/***************************************************************************** * Perform any BL31 early platform setup common to ARM standard platforms. * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be * done before the MMU is initialized so that the memory layout can be used * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { @@ -153,9 +151,10 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, #endif } -/******************************************************************************* +/***************************************************************************** * Perform any BL31 platform setup common to ARM standard platforms - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_platform_setup(void) { /* Initialize the GIC driver, cpu and distributor interfaces */ @@ -163,17 +162,18 @@ void marvell_bl31_platform_setup(void) plat_marvell_gic_init(); /* For Armada-8k-plus family, the SoC includes more than - ** a single AP die, but the default die that boots is AP #0. - ** For other families there is only one die (#0). - ** Initialize psci arch from die 0 - ** */ - psci_arch_init(0); + * a single AP die, but the default die that boots is AP #0. + * For other families there is only one die (#0). + * Initialize psci arch from die 0 + */ + marvell_psci_arch_init(0); } -/******************************************************************************* +/***************************************************************************** * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM * standard platforms - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_plat_runtime_setup(void) { /* Initialize the runtime console */ @@ -192,12 +192,13 @@ void bl31_plat_runtime_setup(void) marvell_bl31_plat_runtime_setup(); } -/******************************************************************************* +/***************************************************************************** * Perform the very early platform specific architectural setup shared between * ARM standard platforms. This only does basic initialization. Later * architectural setup (bl31_arch_setup()) does not do anything platform * specific. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_plat_arch_setup(void) { marvell_setup_page_tables(BL31_BASE, @@ -210,7 +211,7 @@ void marvell_bl31_plat_arch_setup(void) , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif - ); + ); #if BL31_CACHE_DISABLE enable_mmu_el3(DISABLE_DCACHE); diff --git a/plat/marvell/common/marvell_cci.c b/plat/marvell/common/marvell_cci.c index 95c6f265..2df48024 100755 --- a/plat/marvell/common/marvell_cci.c +++ b/plat/marvell/common/marvell_cci.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <cci.h> #include <plat_marvell.h> @@ -13,34 +13,38 @@ static const int cci_map[] = { PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX }; -/****************************************************************************** +/**************************************************************************** * The following functions are defined as weak to allow a platform to override * the way ARM CCI driver is initialised and used. - *****************************************************************************/ + **************************************************************************** + */ #pragma weak plat_marvell_interconnect_init #pragma weak plat_marvell_interconnect_enter_coherency #pragma weak plat_marvell_interconnect_exit_coherency -/****************************************************************************** +/**************************************************************************** * Helper function to initialize ARM CCI driver. - *****************************************************************************/ + **************************************************************************** + */ void plat_marvell_interconnect_init(void) { cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); } -/****************************************************************************** +/**************************************************************************** * Helper function to place current master into coherency - *****************************************************************************/ + **************************************************************************** + */ void plat_marvell_interconnect_enter_coherency(void) { cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); } -/****************************************************************************** +/**************************************************************************** * Helper function to remove current master from coherency - *****************************************************************************/ + **************************************************************************** + */ void plat_marvell_interconnect_exit_coherency(void) { cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); diff --git a/plat/marvell/common/marvell_common.mk b/plat/marvell/common/marvell_common.mk index 2e03302e..3ee2f3db 100644 --- a/plat/marvell/common/marvell_common.mk +++ b/plat/marvell/common/marvell_common.mk @@ -1,4 +1,4 @@ -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses @@ -20,8 +20,8 @@ $(eval $(call add_define,ARO_ENABLE)) LLC_ENABLE := 1 $(eval $(call add_define,LLC_ENABLE)) -PLAT_INCLUDES += -I. -Iinclude/common/tbbr \ - -I$(MARVELL_PLAT_INCLUDE_BASE)/common \ +PLAT_INCLUDES += -I. -Iinclude/common/tbbr \ + -I$(MARVELL_PLAT_INCLUDE_BASE)/common \ -I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64 diff --git a/plat/marvell/common/marvell_ddr_info.c b/plat/marvell/common/marvell_ddr_info.c index ecbee3fb..68bff998 100644 --- a/plat/marvell/common/marvell_ddr_info.c +++ b/plat/marvell/common/marvell_ddr_info.c @@ -18,7 +18,8 @@ #define DRAM_AREA_LENGTH_OFFS 16 #define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) #define DRAM_START_ADDRESS_L_OFFS 23 -#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) +#define DRAM_START_ADDRESS_L_MASK \ + (0x1ff << DRAM_START_ADDRESS_L_OFFS) #define DRAM_START_ADDR_HTOL_OFFS 32 #define DRAM_MAX_CS_NUM 2 @@ -84,15 +85,21 @@ uint64_t mvebu_get_dram_size(uint64_t ap_base_addr) if (!DRAM_CS_ENABLED(iface, cs, ap_base_addr)) break; - /* Decode area length for current CS from register value */ - region_code = GET_DRAM_REGION_SIZE_CODE(iface, cs, ap_base_addr); + /* Decode area length for current CS + * from register value + */ + region_code = + GET_DRAM_REGION_SIZE_CODE(iface, cs, + ap_base_addr); if (DRAM_REGION_SIZE_EVEN(region_code)) { - mem_size += GET_DRAM_REGION_SIZE_EVEN(region_code); + mem_size += + GET_DRAM_REGION_SIZE_EVEN(region_code); } else if (DRAM_REGION_SIZE_ODD(region_code)) { - mem_size += GET_DRAM_REGION_SIZE_ODD(region_code); + mem_size += + GET_DRAM_REGION_SIZE_ODD(region_code); } else { - WARN("%s: Invalid memory region code (0x%x) for CS#%d\n", + WARN("%s: Invalid mem region (0x%x) CS#%d\n", __func__, region_code, cs); return 0; } diff --git a/plat/marvell/common/marvell_gicv2.c b/plat/marvell/common/marvell_gicv2.c index 3a667785..ba8e4096 100644 --- a/plat/marvell/common/marvell_gicv2.c +++ b/plat/marvell/common/marvell_gicv2.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <gicv2.h> #include <plat_marvell.h> #include <platform.h> @@ -46,7 +42,7 @@ static gicv2_driver_data_t marvell_gic_data = { .target_masks_num = ARRAY_SIZE(target_mask_array), }; -/*/ +/* * ARM common helper to initialize the GICv2 only driver. */ void plat_marvell_gic_driver_init(void) diff --git a/plat/marvell/common/marvell_gicv3.c b/plat/marvell/common/marvell_gicv3.c index c4d2b3de..c15d115c 100644 --- a/plat/marvell/common/marvell_gicv3.c +++ b/plat/marvell/common/marvell_gicv3.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <debug.h> #include <gicv3.h> #include <interrupt_props.h> @@ -121,7 +117,7 @@ void plat_marvell_gic_cpuif_disable(void) } /****************************************************************************** - * Marvell common helper to initialize the per-cpu redistributor interface in GICv3 + * Marvell common helper to init. the per-cpu redistributor interface in GICv3 *****************************************************************************/ void plat_marvell_gic_pcpu_init(void) { @@ -138,7 +134,7 @@ void plat_marvell_gic_irq_save(void) * If an ITS is available, save its context before * the Redistributor using: * gicv3_its_save_disable(gits_base, &its_ctx[i]) - * Additionnaly, an implementation-defined sequence may + * Additionally, an implementation-defined sequence may * be required to save the whole ITS state. */ diff --git a/plat/marvell/common/marvell_io_storage.c b/plat/marvell/common/marvell_io_storage.c index ca1d7675..cb9ece24 100644 --- a/plat/marvell/common/marvell_io_storage.c +++ b/plat/marvell/common/marvell_io_storage.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <assert.h> #include <bl_common.h> /* For ARRAY_SIZE */ #include <debug.h> diff --git a/plat/marvell/common/marvell_pm.c b/plat/marvell/common/marvell_pm.c index 822d2bc6..2a757900 100644 --- a/plat/marvell/common/marvell_pm.c +++ b/plat/marvell/common/marvell_pm.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch_helpers.h> #include <assert.h> #include <psci.h> @@ -17,11 +13,12 @@ /* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */ extern const plat_psci_ops_t plat_arm_psci_pm_ops; -/******************************************************************************* +/***************************************************************************** * Private function to program the mailbox for a cpu before it is released * from reset. This function assumes that the mail box base is within * the MARVELL_SHARED_RAM region - ******************************************************************************/ + ***************************************************************************** + */ void marvell_program_mailbox(uintptr_t address) { uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; @@ -45,10 +42,11 @@ void marvell_program_mailbox(uintptr_t address) #endif } -/******************************************************************************* +/***************************************************************************** * The ARM Standard platform definition of platform porting API * `plat_setup_psci_ops`. - ******************************************************************************/ + ***************************************************************************** + */ int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { diff --git a/plat/marvell/common/marvell_topology.c b/plat/marvell/common/marvell_topology.c index 9418307a..a40ff6f5 100644 --- a/plat/marvell/common/marvell_topology.c +++ b/plat/marvell/common/marvell_topology.c @@ -1,23 +1,20 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <plat_marvell.h> /* The power domain tree descriptor */ unsigned char marvell_power_domain_tree_desc[PLAT_MARVELL_CLUSTER_COUNT + 1]; -/******************************************************************************* +/***************************************************************************** * This function dynamically constructs the topology according to * PLAT_MARVELL_CLUSTER_COUNT and returns it. - ******************************************************************************/ + ***************************************************************************** + */ const unsigned char *plat_get_power_domain_tree_desc(void) { int i; @@ -38,18 +35,20 @@ const unsigned char *plat_get_power_domain_tree_desc(void) return marvell_power_domain_tree_desc; } -/******************************************************************************* +/***************************************************************************** * This function validates an MPIDR by checking whether it falls within the * acceptable bounds. An error code (-1) is returned if an incorrect mpidr * is passed. - ******************************************************************************/ + ***************************************************************************** + */ int marvell_check_mpidr(u_register_t mpidr) { unsigned int nb_id, cluster_id, cpu_id; mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK | MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK | + MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) return -1; /* Get north bridge ID */ @@ -69,12 +68,13 @@ int marvell_check_mpidr(u_register_t mpidr) return 0; } -/******************************************************************************* - * This function implements a part of the critical interface between the psci +/***************************************************************************** + * This function implements a part of the critical interface between the PSCI * generic layer and the platform that allows the former to query the platform * to convert an MPIDR to a unique linear index. An error code (-1) is returned * in case the MPIDR is invalid. - ******************************************************************************/ + ***************************************************************************** + */ int plat_core_pos_by_mpidr(u_register_t mpidr) { if (marvell_check_mpidr(mpidr) == -1) diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c index 4d79cd0d..ec293afa 100644 --- a/plat/marvell/common/mrvl_sip_svc.c +++ b/plat/marvell/common/mrvl_sip_svc.c @@ -8,10 +8,10 @@ #include <ap_setup.h> #include <cache_llc.h> #include <debug.h> +#include <marvell_plat_priv.h> #include <runtime_svc.h> #include <smcc.h> #include "comphy/phy-comphy-cp110.h" -#include <plat_private.h> /* #define DEBUG_COMPHY */ #ifdef DEBUG_COMPHY @@ -45,8 +45,8 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, u_register_t x2, u_register_t x3, u_register_t x4, - void *cookie, - void *handle, + void *cookie, + void *handle, u_register_t flags) { u_register_t ret; @@ -63,12 +63,14 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, x1 = (x1 & ~0xffffff) + MVEBU_COMPHY_OFFSET; if ((x1 & 0xffffff) != MVEBU_COMPHY_OFFSET) { - ERROR("%s: Wrong smc (0x%x) address: %lx\n", __func__, smc_fid, x1); + ERROR("%s: Wrong smc (0x%x) address: %lx\n", + __func__, smc_fid, x1); SMC_RET1(handle, SMC_UNK); } if (x2 >= MAX_LANE_NR) { - ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n", __func__, smc_fid, x2); + ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n", + __func__, smc_fid, x2); SMC_RET1(handle, SMC_UNK); } } diff --git a/plat/marvell/common/mss/mss_common.mk b/plat/marvell/common/mss/mss_common.mk index 83fe32c0..898b6dcc 100644 --- a/plat/marvell/common/mss/mss_common.mk +++ b/plat/marvell/common/mss/mss_common.mk @@ -1,35 +1,11 @@ # -# *************************************************************************** -# Copyright (C) 2016 Marvell International Ltd. -# *************************************************************************** +# Copyright (C) 2018 Marvell International Ltd. # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# Neither the name of Marvell nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, -# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses # + PLAT_MARVELL := plat/marvell MSS_SOURCE := $(PLAT_MARVELL)/common/mss diff --git a/plat/marvell/common/mss/mss_ipc_drv.c b/plat/marvell/common/mss/mss_ipc_drv.c index 5fde9243..731c315b 100644 --- a/plat/marvell/common/mss/mss_ipc_drv.c +++ b/plat/marvell/common/mss/mss_ipc_drv.c @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #include <plat_marvell.h> @@ -46,10 +19,10 @@ unsigned long mv_pm_ipc_msg_base; unsigned int mv_pm_ipc_queue_size; -unsigned int msg_sync = 0; +unsigned int msg_sync; int msg_index = IPC_CH_MSG_IDX; -/******************************************************************************* +/****************************************************************************** * mss_pm_ipc_init * * DESCRIPTION: Initialize PM IPC infrastructure @@ -61,17 +34,19 @@ int mv_pm_ipc_init(unsigned long ipc_control_addr) (struct mss_pm_ipc_ctrl *)ipc_control_addr; /* Initialize PM IPC control block */ - mv_pm_ipc_msg_base = ipc_control->msg_base_address | IPC_MSG_BASE_MASK; + mv_pm_ipc_msg_base = ipc_control->msg_base_address | + IPC_MSG_BASE_MASK; mv_pm_ipc_queue_size = ipc_control->queue_size; return 0; } -/******************************************************************************* -* mv_pm_ipc_queue_addr_get -* -* DESCRIPTION: Returns the IPC queue address -*******************************************************************************/ +/****************************************************************************** + * mv_pm_ipc_queue_addr_get + * + * DESCRIPTION: Returns the IPC queue address + ****************************************************************************** + */ unsigned int mv_pm_ipc_queue_addr_get(void) { unsigned int addr; @@ -81,31 +56,35 @@ unsigned int mv_pm_ipc_queue_addr_get(void) if (msg_index >= IPC_CH_NUM_OF_MSG) msg_index = 0; - addr = (unsigned int)(mv_pm_ipc_msg_base + (msg_index * mv_pm_ipc_queue_size)); + addr = (unsigned int)(mv_pm_ipc_msg_base + + (msg_index * mv_pm_ipc_queue_size)); flush_dcache_range((uint64_t)&msg_index, sizeof(msg_index)); return addr; } -/******************************************************************************* -* mv_pm_ipc_msg_rx -* -* DESCRIPTION: Retrieve message from IPC channel -*******************************************************************************/ +/****************************************************************************** + * mv_pm_ipc_msg_rx + * + * DESCRIPTION: Retrieve message from IPC channel + ****************************************************************************** + */ int mv_pm_ipc_msg_rx(unsigned int channel_id, struct mss_pm_ipc_msg *msg) { unsigned int addr = mv_pm_ipc_queue_addr_get(); + msg->msg_reply = mmio_read_32(addr + IPC_MSG_REPLY_LOC); return 0; } -/******************************************************************************* -* mv_pm_ipc_msg_tx -* -* DESCRIPTION: Send message via IPC channel -*******************************************************************************/ +/****************************************************************************** + * mv_pm_ipc_msg_tx + * + * DESCRIPTION: Send message via IPC channel + ****************************************************************************** + */ int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id, unsigned int cluster_power_state) { @@ -120,11 +99,12 @@ int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id, mmio_write_32(addr + IPC_MSG_SYNC_ID_LOC, msg_sync); mmio_write_32(addr + IPC_MSG_ID_LOC, msg_id); mmio_write_32(addr + IPC_MSG_CPU_ID_LOC, channel_id); - mmio_write_32(addr + IPC_MSG_POWER_STATE_LOC, cluster_power_state); + mmio_write_32(addr + IPC_MSG_POWER_STATE_LOC, + cluster_power_state); mmio_write_32(addr + IPC_MSG_STATE_LOC, IPC_MSG_OCCUPY); } else { - printf("mv_pm_ipc_msg_tx failed!!!\n"); + ERROR("%s: FAILED\n", __func__); } return 0; diff --git a/plat/marvell/common/mss/mss_ipc_drv.h b/plat/marvell/common/mss/mss_ipc_drv.h index ff8508ac..28eb907e 100644 --- a/plat/marvell/common/mss/mss_ipc_drv.h +++ b/plat/marvell/common/mss/mss_ipc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -101,19 +101,19 @@ struct mss_pm_ipc_ch { int mv_pm_ipc_init(unsigned long ipc_control_addr); /***************************************************************************** -* mv_pm_ipc_msg_rx -* -* DESCRIPTION: Retrieve message from IPC channel -****************************************************************************** -*/ + * mv_pm_ipc_msg_rx + * + * DESCRIPTION: Retrieve message from IPC channel + ***************************************************************************** + */ int mv_pm_ipc_msg_rx(unsigned int channel_id, struct mss_pm_ipc_msg *msg); /***************************************************************************** -* mv_pm_ipc_msg_tx -* -* DESCRIPTION: Send message via IPC channel -****************************************************************************** -*/ + * mv_pm_ipc_msg_tx + * + * DESCRIPTION: Send message via IPC channel + ***************************************************************************** + */ int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id, unsigned int cluster_power_state); diff --git a/plat/marvell/common/mss/mss_mem.h b/plat/marvell/common/mss/mss_mem.h index bed5584c..efff59e6 100644 --- a/plat/marvell/common/mss/mss_mem.h +++ b/plat/marvell/common/mss/mss_mem.h @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #ifndef __MSS_PM_MEM_H @@ -41,8 +14,8 @@ enum mss_pm_ctrl_handshake { MSS_UN_INITIALIZED = 0, MSS_COMPATIBILITY_ERROR = 1, - MSS_ACKNOWLEDGEMENT = 2, - HOST_ACKNOWLEDGEMENT = 3 + MSS_ACKNOWLEDGMENT = 2, + HOST_ACKNOWLEDGMENT = 3 }; enum mss_pm_ctrl_rtos_env { diff --git a/plat/marvell/common/mss/mss_scp_bl2_format.h b/plat/marvell/common/mss/mss_scp_bl2_format.h index 4db3a336..c04df727 100644 --- a/plat/marvell/common/mss/mss_scp_bl2_format.h +++ b/plat/marvell/common/mss/mss_scp_bl2_format.h @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2017 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #ifndef __MSS_SCP_BL2_FORMAT_H @@ -44,7 +17,8 @@ /* Types definitions */ typedef struct file_header { - uint32_t magic; /* Magic specific for concatenated file (used for validation) */ + /* Magic specific for concatenated file (used for validation) */ + uint32_t magic; uint32_t nr_of_imgs; /* Number of images concatenated */ } file_header_t; @@ -62,7 +36,9 @@ enum cm3_t { typedef struct img_header { uint32_t type; /* CM3 type, can be one of cm3_t */ uint32_t length; /* Image length */ - uint32_t version; /* For sanity checks and future extended functionality */ + uint32_t version; /* For sanity checks and future + * extended functionality + */ } img_header_t; #endif /* __MSS_SCP_BL2_FORMAT_H */ diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c index b395a393..ff8f26c8 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.c +++ b/plat/marvell/common/mss/mss_scp_bootloader.c @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #include <assert.h> @@ -76,14 +49,14 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) int timeout = MSS_HANDSHAKE_TIMEOUT; /* Wait for SCP to signal it's ready */ - while ((mss_pm_crtl->handshake != MSS_ACKNOWLEDGEMENT) && + while ((mss_pm_crtl->handshake != MSS_ACKNOWLEDGMENT) && (timeout-- > 0)) mdelay(1); - if (mss_pm_crtl->handshake != MSS_ACKNOWLEDGEMENT) + if (mss_pm_crtl->handshake != MSS_ACKNOWLEDGMENT) return -1; - mss_pm_crtl->handshake = HOST_ACKNOWLEDGEMENT; + mss_pm_crtl->handshake = HOST_ACKNOWLEDGMENT; return 0; } @@ -98,7 +71,7 @@ static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) return 1; } - NOTICE("Loading MSS image from address 0x%x Size 0x%x to MSS at 0x%lx\n", + NOTICE("Loading MSS image from addr. 0x%x Size 0x%x to MSS at 0x%lx\n", src_addr, size, mss_regs); /* load image to MSS RAM using DMA */ loop_num = (size / DMA_SIZE) + (((size & (DMA_SIZE - 1)) == 0) ? 0 : 1); @@ -153,7 +126,8 @@ static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) * firmware for AP is dedicated for PM and therefore some additional PM * initialization is required */ -static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t ap_idx) +static int mss_ap_load_image(uintptr_t single_img, + uint32_t image_size, uint32_t ap_idx) { volatile struct mss_pm_ctrl_block *mss_pm_crtl; int ret; @@ -188,7 +162,8 @@ static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t /* TODO: add checksum to image */ VERBOSE("Send info about the SCP_BL2 image to be transferred to SCP\n"); - ret = mss_image_load(single_img, image_size, bl2_plat_get_ap_mss_regs(ap_idx)); + ret = mss_image_load(single_img, image_size, + bl2_plat_get_ap_mss_regs(ap_idx)); if (ret != 0) { ERROR("SCP Image load failed\n"); return -1; @@ -203,7 +178,8 @@ static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t } /* Load CM3 image (single_img) to CM3 pointed by cm3_type */ -static int load_img_to_cm3(enum cm3_t cm3_type, uintptr_t single_img, uint32_t image_size) +static int load_img_to_cm3(enum cm3_t cm3_type, + uintptr_t single_img, uint32_t image_size) { int ret, ap_idx, cp_index; uint32_t ap_count = bl2_plat_get_ap_count(); @@ -230,14 +206,20 @@ static int load_img_to_cm3(enum cm3_t cm3_type, uintptr_t single_img, uint32_t i */ cp_index = cm3_type - 1; for (ap_idx = 0; ap_idx < ap_count; ap_idx++) { - /* Check if we should load this image according to number of CPs */ + /* Check if we should load this image + * according to number of CPs + */ if (bl2_plat_get_cp_count(ap_idx) <= cp_index) { - NOTICE("Skipping MSS CP%d related image\n", cp_index); + NOTICE("Skipping MSS CP%d related image\n", + cp_index); break; } - NOTICE("Load image to CP%d MSS AP%d\n", cp_index, ap_idx); - ret = mss_image_load(single_img, image_size, bl2_plat_get_cp_mss_regs(ap_idx, cp_index)); + NOTICE("Load image to CP%d MSS AP%d\n", + cp_index, ap_idx); + ret = mss_image_load(single_img, image_size, + bl2_plat_get_cp_mss_regs( + ap_idx, cp_index)); if (ret != 0) { ERROR("SCP Image load failed\n"); return -1; diff --git a/plat/marvell/common/mss/mss_scp_bootloader.h b/plat/marvell/common/mss/mss_scp_bootloader.h index 762bb020..67c387a0 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.h +++ b/plat/marvell/common/mss/mss_scp_bootloader.h @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #ifndef __MSS_SCP_BOOTLOADER_H__ diff --git a/plat/marvell/common/plat_delay_timer.c b/plat/marvell/common/plat_delay_timer.c index eab68ca1..dfc77c7f 100644 --- a/plat/marvell/common/plat_delay_timer.c +++ b/plat/marvell/common/plat_delay_timer.c @@ -1,17 +1,13 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch_helpers.h> #include <delay_timer.h> -#include <plat_def.h> +#include <mvebu_def.h> #define SYS_COUNTER_FREQ_IN_MHZ (COUNTER_FREQUENCY/1000000) diff --git a/plat/marvell/marvell.mk b/plat/marvell/marvell.mk index 8a1d9fcb..217ad46f 100644 --- a/plat/marvell/marvell.mk +++ b/plat/marvell/marvell.mk @@ -1,4 +1,4 @@ -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/tools/doimage/Makefile b/tools/doimage/Makefile index 07facb51..bc74369f 100644 --- a/tools/doimage/Makefile +++ b/tools/doimage/Makefile @@ -1,10 +1,9 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses - PROJECT = doimage OBJECTS = doimage.o diff --git a/tools/doimage/doimage.c b/tools/doimage/doimage.c index 299f40fa..56dabbad 100644 --- a/tools/doimage/doimage.c +++ b/tools/doimage/doimage.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <stdlib.h> #include <stdio.h> #include <stdint.h> @@ -48,7 +48,8 @@ #define AES_BLOCK_SZ 16 #define RSA_SIGN_BYTE_LEN 256 #define MAX_RSA_DER_BYTE_LEN 524 -#define CP_CTRL_EL_ARRAY_SZ 32 /* Number of address pairs in control array */ +/* Number of address pairs in control array */ +#define CP_CTRL_EL_ARRAY_SZ 32 #define VERSION_STRING "Marvell(C) doimage utility version 3.2" @@ -61,12 +62,12 @@ #define MAIN_HDR_MAGIC 0xB105B002 /* PROLOG alignment considerations: -** 128B: To allow supporting XMODEM protocol. -** 8KB: To align the boot image to the largest NAND page size, and simplify -** the read operations from NAND. -** We choose the largest page size, in order to use a single image for all -** NAND page sizes. -*/ + * 128B: To allow supporting XMODEM protocol. + * 8KB: To align the boot image to the largest NAND page size, and simplify + * the read operations from NAND. + * We choose the largest page size, in order to use a single image for all + * NAND page sizes. + */ #define PROLOG_ALIGNMENT (8 << 10) /* UART argument bitfield */ @@ -163,8 +164,8 @@ typedef struct _options { void usage_err(char *msg) { - printf("Error: %s\n", msg); - printf("run 'doimage -h' to get usage information\n"); + fprintf(stderr, "Error: %s\n", msg); + fprintf(stderr, "run 'doimage -h' to get usage information\n"); exit(-1); } @@ -176,34 +177,40 @@ void usage(void) printf("Arguments\n"); printf(" input_file name of boot image file.\n"); - printf(" if -p is used, name of bootrom image file to parse.\n"); + printf(" if -p is used, name of the bootrom image file"); + printf(" to parse.\n"); printf(" output_file name of output bootrom image file\n"); printf("\nOptions\n"); printf(" -s target SOC name. supports a8020,a7020\n"); - printf(" different SOCs may have different boot image format so\n"); - printf(" it's mandatory to know the target SOC\n"); + printf(" different SOCs may have different boot image\n"); + printf(" format so it's mandatory to know the target SOC\n"); printf(" -i boot I/F name. supports nand, spi, nor\n"); - printf(" This affects certain parameters coded in the image header\n"); + printf(" This affects certain parameters coded in the\n"); + printf(" image header\n"); printf(" -l boot image load address. default is 0x0\n"); printf(" -e boot image entry address. default is 0x0\n"); printf(" -b binary extension image file.\n"); - printf(" This image is executed before the boot image. this is typically\n"); - printf(" used to initiliaze the memory controller.\n"); + printf(" This image is executed before the boot image.\n"); + printf(" This is typically used to initialize the memory "); + printf(" controller.\n"); printf(" Currently supports only a single file.\n"); #ifdef CONFIG_MVEBU_SECURE_BOOT - printf(" -c Make trusted boot image using parameters from the configuration file.\n"); + printf(" -c Make trusted boot image using parameters\n"); + printf(" from the configuration file.\n"); #endif printf(" -p Parse and display a pre-built boot image\n"); #ifdef CONFIG_MVEBU_SECURE_BOOT - printf(" -k Key index for RSA signatures verification when parsing the boot image\n"); + printf(" -k Key index for RSA signatures verification\n"); + printf(" when parsing the boot image\n"); #endif printf(" -m Disable prints of bootrom and binary extension\n"); - printf(" -u UART baudrate used for bootrom prints. Must be multiple of 1200\n"); - printf(" -h Dispalys this help message\n"); + printf(" -u UART baudrate used for bootrom prints.\n"); + printf(" Must be multiple of 1200\n"); + printf(" -h Show this help message\n"); printf(" IO-ROM NFC-NAND boot parameters:\n"); - printf(" -n NAND device block size (in KB) [Default is 64KB].\n"); - printf(" -t NAND cell technology (SLC or MLC) [Default is SLC].\n"); + printf(" -n NAND device block size in KB [Default is 64KB].\n"); + printf(" -t NAND cell technology (SLC [Default] or MLC)\n"); exit(-1); } @@ -245,20 +252,20 @@ uint32_t checksum32(uint32_t *start, int len) } /******************************************************************************* -* create_rsa_signature (memory buffer content) -* Create RSASSA-PSS/SHA-256 signature for memory buffer -* using RSA Private Key -* INPUT: -* pk_ctx Private Key context -* input memory buffer -* ilen buffer length -* pers personalization string for seeding the RNG. -* For instance a private key file name. -* OUTPUT: -* signature RSA-2048 signature -* RETURN: -* 0 on success -*******************************************************************************/ + * create_rsa_signature (memory buffer content) + * Create RSASSA-PSS/SHA-256 signature for memory buffer + * using RSA Private Key + * INPUT: + * pk_ctx Private Key context + * input memory buffer + * ilen buffer length + * pers personalization string for seeding the RNG. + * For instance a private key file name. + * OUTPUT: + * signature RSA-2048 signature + * RETURN: + * 0 on success + */ #ifdef CONFIG_MVEBU_SECURE_BOOT int create_rsa_signature(mbedtls_pk_context *pk_ctx, const unsigned char *input, @@ -272,7 +279,9 @@ int create_rsa_signature(mbedtls_pk_context *pk_ctx, unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; int rval; - /* Not sure this is required, but it's safer to start with empty buffers */ + /* Not sure this is required, + * but it's safer to start with empty buffers + */ memset(hash, 0, sizeof(hash)); memset(buf, 0, sizeof(buf)); @@ -287,19 +296,25 @@ int create_rsa_signature(mbedtls_pk_context *pk_ctx, goto sign_exit; } - /* The PK context should be already initalized. + /* The PK context should be already initialized. * Set the padding type for this PK context */ - mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pk_ctx), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA256); + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pk_ctx), + MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA256); /* First compute the SHA256 hash for the input blob */ mbedtls_sha256(input, ilen, hash, 0); /* Then calculate the hash signature */ - rval = mbedtls_rsa_rsassa_pss_sign(mbedtls_pk_rsa(*pk_ctx), mbedtls_ctr_drbg_random, &ctr_drbg, - MBEDTLS_RSA_PRIVATE, MBEDTLS_MD_SHA256, 0, hash, buf); + rval = mbedtls_rsa_rsassa_pss_sign(mbedtls_pk_rsa(*pk_ctx), + mbedtls_ctr_drbg_random, + &ctr_drbg, + MBEDTLS_RSA_PRIVATE, + MBEDTLS_MD_SHA256, 0, hash, buf); if (rval != 0) { - fprintf(stderr, "Failed to create RSA signature for %s. Error %d\n", pers, rval); + fprintf(stderr, + "Failed to create RSA signature for %s. Error %d\n", + pers, rval); goto sign_exit; } memcpy(signature, buf, 256); @@ -312,21 +327,21 @@ sign_exit: } /* end of create_rsa_signature */ /******************************************************************************* -* verify_rsa_signature (memory buffer content) -* Verify RSASSA-PSS/SHA-256 signature for memory buffer -* using RSA Public Key -* INPUT: -* pub_key Public Key buffer -* ilen Public Key buffer length -* input memory buffer -* ilen buffer length -* pers personalization string for seeding the RNG. -* signature RSA-2048 signature -* OUTPUT: -* none -* RETURN: -* 0 on success -*******************************************************************************/ + * verify_rsa_signature (memory buffer content) + * Verify RSASSA-PSS/SHA-256 signature for memory buffer + * using RSA Public Key + * INPUT: + * pub_key Public Key buffer + * ilen Public Key buffer length + * input memory buffer + * ilen buffer length + * pers personalization string for seeding the RNG. + * signature RSA-2048 signature + * OUTPUT: + * none + * RETURN: + * 0 on success + */ int verify_rsa_signature(const unsigned char *pub_key, size_t klen, const unsigned char *input, @@ -340,7 +355,9 @@ int verify_rsa_signature(const unsigned char *pub_key, unsigned char hash[32]; int rval; - /* Not sure this is required, but it's safer to start with empty buffer */ + /* Not sure this is required, + * but it's safer to start with empty buffer + */ memset(hash, 0, sizeof(hash)); mbedtls_pk_init(&pk_ctx); @@ -356,20 +373,28 @@ int verify_rsa_signature(const unsigned char *pub_key, } /* Check ability to read the public key */ - rval = mbedtls_pk_parse_public_key(&pk_ctx, pub_key, MAX_RSA_DER_BYTE_LEN); + rval = mbedtls_pk_parse_public_key(&pk_ctx, pub_key, + MAX_RSA_DER_BYTE_LEN); if (rval != 0) { - fprintf(stderr, " Failed in pk_parse_public_key (%#x)!\n", rval); + fprintf(stderr, " Failed in pk_parse_public_key (%#x)!\n", + rval); goto verify_exit; } /* Set the padding type for the new PK context */ - mbedtls_rsa_set_padding(mbedtls_pk_rsa(pk_ctx), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA256); + mbedtls_rsa_set_padding(mbedtls_pk_rsa(pk_ctx), + MBEDTLS_RSA_PKCS_V21, + MBEDTLS_MD_SHA256); /* Compute the SHA256 hash for the input buffer */ mbedtls_sha256(input, ilen, hash, 0); - rval = mbedtls_rsa_rsassa_pss_verify(mbedtls_pk_rsa(pk_ctx), mbedtls_ctr_drbg_random, &ctr_drbg, - MBEDTLS_RSA_PUBLIC, MBEDTLS_MD_SHA256, 0, hash, signature); + rval = mbedtls_rsa_rsassa_pss_verify(mbedtls_pk_rsa(pk_ctx), + mbedtls_ctr_drbg_random, + &ctr_drbg, + MBEDTLS_RSA_PUBLIC, + MBEDTLS_MD_SHA256, 0, + hash, signature); if (rval != 0) fprintf(stderr, "Failed to verify signature (%d)!\n", rval); @@ -382,32 +407,33 @@ verify_exit: } /* end of verify_rsa_signature */ /******************************************************************************* -* image_encrypt -* Encrypt image buffer using AES-256-CBC scheme. -* The resulting image is saved into opts.sec_opts->encrypted_image -* and the adjusted image size into opts.sec_opts->enc_image_sz -* First AES_BLOCK_SZ bytes of the output image contain IV -* INPUT: -* buf Source buffer to encrypt -* blen Source buffer length -* OUTPUT: -* none -* RETURN: -* 0 on success -*******************************************************************************/ + * image_encrypt + * Encrypt image buffer using AES-256-CBC scheme. + * The resulting image is saved into opts.sec_opts->encrypted_image + * and the adjusted image size into opts.sec_opts->enc_image_sz + * First AES_BLOCK_SZ bytes of the output image contain IV + * INPUT: + * buf Source buffer to encrypt + * blen Source buffer length + * OUTPUT: + * none + * RETURN: + * 0 on success + */ int image_encrypt(uint8_t *buf, uint32_t blen) { - struct timeval tv; + struct timeval tv; char *ptmp = (char *)&tv; - unsigned char digest[32]; - unsigned char IV[AES_BLOCK_SZ]; - int i, k; - mbedtls_aes_context aes_ctx; - int rval = -1; + unsigned char digest[32]; + unsigned char IV[AES_BLOCK_SZ]; + int i, k; + mbedtls_aes_context aes_ctx; + int rval = -1; uint8_t *test_img = 0; if (AES_BLOCK_SZ > 32) { - fprintf(stderr, "Unsupported AES block size %d\n", AES_BLOCK_SZ); + fprintf(stderr, "Unsupported AES block size %d\n", + AES_BLOCK_SZ); return rval; } @@ -415,28 +441,35 @@ int image_encrypt(uint8_t *buf, uint32_t blen) memset(IV, 0, AES_BLOCK_SZ); memset(digest, 0, 32); - /* Generate initialization vector and init the AES engine */ - /* Use file name XOR current time and finaly SHA-256 [0...AES_BLOCK_SZ-1] */ + /* Generate initialization vector and init the AES engine + * Use file name XOR current time and finally SHA-256 + * [0...AES_BLOCK_SZ-1] + */ k = strlen(opts.sec_opts->aes_key_file); if (k > AES_BLOCK_SZ) k = AES_BLOCK_SZ; memcpy(IV, opts.sec_opts->aes_key_file, k); gettimeofday(&tv, 0); - for (i = 0, k = 0; i < AES_BLOCK_SZ; i++, k = (k+1) % sizeof(struct timeval)) + for (i = 0, k = 0; i < AES_BLOCK_SZ; i++, + k = (k+1) % sizeof(struct timeval)) IV[i] ^= ptmp[k]; - /* compute SHA-256 digest of the results and use it as the init vector (IV) */ + /* compute SHA-256 digest of the results + * and use it as the init vector (IV) + */ mbedtls_sha256(IV, AES_BLOCK_SZ, digest, 0); memcpy(IV, digest, AES_BLOCK_SZ); - mbedtls_aes_setkey_enc(&aes_ctx, opts.sec_opts->aes_key, AES_KEY_BIT_LEN); + mbedtls_aes_setkey_enc(&aes_ctx, opts.sec_opts->aes_key, + AES_KEY_BIT_LEN); /* The output image has to include extra space for IV * and to be aligned to the AES block size. * The input image buffer has to be already aligned to AES_BLOCK_SZ * and padded with zeroes */ - opts.sec_opts->enc_image_sz = (blen + 2 * AES_BLOCK_SZ - 1) & ~(AES_BLOCK_SZ - 1); + opts.sec_opts->enc_image_sz = (blen + 2 * AES_BLOCK_SZ - 1) & + ~(AES_BLOCK_SZ - 1); opts.sec_opts->encrypted_image = calloc(opts.sec_opts->enc_image_sz, 1); if (opts.sec_opts->encrypted_image == 0) { fprintf(stderr, "Failed to allocate encrypted image!\n"); @@ -454,7 +487,8 @@ int image_encrypt(uint8_t *buf, uint32_t blen) opts.sec_opts->enc_image_sz - AES_BLOCK_SZ, IV, buf, opts.sec_opts->encrypted_image); if (rval != 0) { - fprintf(stderr, "Failed to encrypt the image! Error %d\n", rval); + fprintf(stderr, "Failed to encrypt the image! Error %d\n", + rval); goto encrypt_exit; } @@ -462,7 +496,8 @@ int image_encrypt(uint8_t *buf, uint32_t blen) /* Try to decrypt the image and compare it with the original data */ mbedtls_aes_init(&aes_ctx); - mbedtls_aes_setkey_dec(&aes_ctx, opts.sec_opts->aes_key, AES_KEY_BIT_LEN); + mbedtls_aes_setkey_dec(&aes_ctx, opts.sec_opts->aes_key, + AES_KEY_BIT_LEN); test_img = calloc(opts.sec_opts->enc_image_sz - AES_BLOCK_SZ, 1); if (test_img == 0) { @@ -478,13 +513,15 @@ int image_encrypt(uint8_t *buf, uint32_t blen) opts.sec_opts->enc_image_sz - AES_BLOCK_SZ, IV, opts.sec_opts->encrypted_image, test_img); if (rval != 0) { - fprintf(stderr, "Failed to decrypt the image! Error %d\n", rval); + fprintf(stderr, "Failed to decrypt the image! Error %d\n", + rval); goto encrypt_exit; } for (i = 0; i < blen; i++) { if (buf[i] != test_img[i]) { - fprintf(stderr, "Failed to compare the image after decryption! Byte count %d\n", i); + fprintf(stderr, "Failed to compare the image after"); + fprintf(stderr, " decryption! Byte count is %d\n", i); rval = -1; goto encrypt_exit; } @@ -500,16 +537,16 @@ encrypt_exit: } /* end of image_encrypt */ /******************************************************************************* -* verify_secure_header_signatures -* Verify CSK array, header and image signatures and print results -* INPUT: -* main_hdr Main header -* sec_ext Secure extention -* OUTPUT: -* none -* RETURN: -* 0 on success -*******************************************************************************/ + * verify_secure_header_signatures + * Verify CSK array, header and image signatures and print results + * INPUT: + * main_hdr Main header + * sec_ext Secure extension + * OUTPUT: + * none + * RETURN: + * 0 on success + */ int verify_secure_header_signatures(header_t *main_hdr, sec_entry_t *sec_ext) { uint8_t *image = (uint8_t *)main_hdr + main_hdr->prolog_size; @@ -523,8 +560,10 @@ int verify_secure_header_signatures(header_t *main_hdr, sec_entry_t *sec_ext) fprintf(stdout, "\nCheck RSA Signatures\n"); fprintf(stdout, "#########################\n"); fprintf(stdout, "CSK Block Signature: "); - if (verify_rsa_signature(sec_ext->kak_key, MAX_RSA_DER_BYTE_LEN, - &sec_ext->csk_keys[0][0], sizeof(sec_ext->csk_keys), + if (verify_rsa_signature(sec_ext->kak_key, + MAX_RSA_DER_BYTE_LEN, + &sec_ext->csk_keys[0][0], + sizeof(sec_ext->csk_keys), "CSK Block Signature: ", sec_ext->csk_sign) != 0) { fprintf(stdout, "ERROR\n"); @@ -534,7 +573,8 @@ int verify_secure_header_signatures(header_t *main_hdr, sec_entry_t *sec_ext) if (opts.key_index != -1) { fprintf(stdout, "Image Signature: "); - if (verify_rsa_signature(sec_ext->csk_keys[opts.key_index], MAX_RSA_DER_BYTE_LEN, + if (verify_rsa_signature(sec_ext->csk_keys[opts.key_index], + MAX_RSA_DER_BYTE_LEN, image, main_hdr->boot_image_size, "Image Signature: ", sec_ext->image_sign) != 0) { @@ -544,16 +584,20 @@ int verify_secure_header_signatures(header_t *main_hdr, sec_entry_t *sec_ext) fprintf(stdout, "OK\n"); fprintf(stdout, "Header Signature: "); - if (verify_rsa_signature(sec_ext->csk_keys[opts.key_index], MAX_RSA_DER_BYTE_LEN, - (uint8_t *)main_hdr, main_hdr->prolog_size, + if (verify_rsa_signature(sec_ext->csk_keys[opts.key_index], + MAX_RSA_DER_BYTE_LEN, + (uint8_t *)main_hdr, + main_hdr->prolog_size, "Header Signature: ", signature) != 0) { fprintf(stdout, "ERROR\n"); goto ver_error; } fprintf(stdout, "OK\n"); - } else - fprintf(stdout, "SKIP Image and Header Signatures check (undefined key index)\n"); + } else { + fprintf(stdout, "SKIP Image and Header Signatures"); + fprintf(stdout, " check (undefined key index)\n"); + } rval = 0; @@ -563,25 +607,29 @@ ver_error: } /******************************************************************************* -* verify_and_copy_file_name_entry -* INPUT: -* element_name -* element -* OUTPUT: -* copy_to -* RETURN: -* 0 on success -*******************************************************************************/ -int verify_and_copy_file_name_entry(const char *element_name, const char *element, char *copy_to) + * verify_and_copy_file_name_entry + * INPUT: + * element_name + * element + * OUTPUT: + * copy_to + * RETURN: + * 0 on success + */ +int verify_and_copy_file_name_entry(const char *element_name, + const char *element, char *copy_to) { int element_length = strlen(element); if (element_length >= MAX_FILENAME) { - fprintf(stderr, "The file name %s for %s is too long (%d). Maximum allowed %d characters!\n", - element, element_name, element_length, MAX_FILENAME); + fprintf(stderr, "The file name %s for %s is too long (%d). ", + element, element_name, element_length); + fprintf(stderr, "Maximum allowed %d characters!\n", + MAX_FILENAME); return -1; } else if (element_length == 0) { - fprintf(stderr, "The file name for %s is empty!\n", element_name); + fprintf(stderr, "The file name for %s is empty!\n", + element_name); return -1; } memcpy(copy_to, element, element_length); @@ -590,16 +638,16 @@ int verify_and_copy_file_name_entry(const char *element_name, const char *elemen } /******************************************************************************* -* parse_sec_config_file -* Read the secure boot configuration from a file -* into internal structures -* INPUT: -* filename File name -* OUTPUT: -* none -* RETURN: -* 0 on success -*******************************************************************************/ + * parse_sec_config_file + * Read the secure boot configuration from a file + * into internal structures + * INPUT: + * filename File name + * OUTPUT: + * none + * RETURN: + * 0 on success + */ int parse_sec_config_file(char *filename) { config_t sec_cfg; @@ -612,29 +660,37 @@ int parse_sec_config_file(char *filename) config_init(&sec_cfg); if (config_read_file(&sec_cfg, filename) != CONFIG_TRUE) { - fprintf(stderr, "Failed to read data from config file %s\n\t%s at line %d\n", - filename, config_error_text(&sec_cfg), config_error_line(&sec_cfg)); + fprintf(stderr, "Failed to read data from config file "); + fprintf(stderr, "%s\n\t%s at line %d\n", + filename, config_error_text(&sec_cfg), + config_error_line(&sec_cfg)); goto exit_parse; } sec_opt = (sec_options *)calloc(sizeof(sec_options), 1); if (sec_opt == 0) { - fprintf(stderr, "Cannot allocate memory for secure boot options!\n"); + fprintf(stderr, + "Cannot allocate memory for secure boot options!\n"); goto exit_parse; } /* KAK file name */ - if (config_lookup_string(&sec_cfg, "kak_key_file", &cfg_string) != CONFIG_TRUE) { + if (config_lookup_string(&sec_cfg, "kak_key_file", + &cfg_string) != CONFIG_TRUE) { fprintf(stderr, "The \"kak_key_file\" undefined!\n"); goto exit_parse; } - if (verify_and_copy_file_name_entry("kak_key_file", cfg_string, sec_opt->kak_key_file)) + if (verify_and_copy_file_name_entry("kak_key_file", + cfg_string, sec_opt->kak_key_file)) goto exit_parse; /* AES file name - can be empty/undefined */ - if (config_lookup_string(&sec_cfg, "aes_key_file", &cfg_string) == CONFIG_TRUE) { - if (verify_and_copy_file_name_entry("aes_key_file", cfg_string, sec_opt->aes_key_file)) + if (config_lookup_string(&sec_cfg, "aes_key_file", + &cfg_string) == CONFIG_TRUE) { + if (verify_and_copy_file_name_entry("aes_key_file", + cfg_string, + sec_opt->aes_key_file)) goto exit_parse; } @@ -646,8 +702,8 @@ int parse_sec_config_file(char *filename) } array_sz = config_setting_length(csk_array); if (array_sz > CSK_ARR_SZ) { - fprintf(stderr, "The \"csk_key_file\" array is too big! " - "Only first %d elements will be used\n", + fprintf(stderr, "The \"csk_key_file\" array is too big! "); + fprintf(stderr, "Only first %d elements will be used\n", CSK_ARR_SZ); array_sz = CSK_ARR_SZ; } else if (array_sz == 0) { @@ -658,49 +714,62 @@ int parse_sec_config_file(char *filename) for (element = 0; element < array_sz; element++) { cfg_string = config_setting_get_string_elem(csk_array, element); if (verify_and_copy_file_name_entry( - "csk_key_file", cfg_string, sec_opt->csk_key_file[element])) { - fprintf(stderr, "Bad csk_key_file[%d] entry!\n", element); + "csk_key_file", cfg_string, + sec_opt->csk_key_file[element])) { + fprintf(stderr, "Bad csk_key_file[%d] entry!\n", + element); goto exit_parse; } } /* JTAG options */ - if (config_lookup_bool(&sec_cfg, "jtag.enable", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"jtag.enable\" element. Using default - FALSE\n"); + if (config_lookup_bool(&sec_cfg, "jtag.enable", + &cfg_int32) != CONFIG_TRUE) { + fprintf(stderr, "Error obtaining \"jtag.enable\" element. "); + fprintf(stderr, "Using default - FALSE\n"); cfg_int32 = 0; } sec_opt->jtag_enable = cfg_int32; - if (config_lookup_int(&sec_cfg, "jtag.delay", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"jtag.delay\" element. Using default - 0us\n"); + if (config_lookup_int(&sec_cfg, "jtag.delay", + &cfg_int32) != CONFIG_TRUE) { + fprintf(stderr, "Error obtaining \"jtag.delay\" element. "); + fprintf(stderr, "Using default - 0us\n"); cfg_int32 = 0; } sec_opt->jtag_delay = cfg_int32; /* eFUSE option */ - if (config_lookup_bool(&sec_cfg, "efuse_disable", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"efuse_disable\" element. Using default - TRUE\n"); + if (config_lookup_bool(&sec_cfg, "efuse_disable", + &cfg_int32) != CONFIG_TRUE) { + fprintf(stderr, "Error obtaining \"efuse_disable\" element. "); + fprintf(stderr, "Using default - TRUE\n"); cfg_int32 = 1; } sec_opt->efuse_disable = cfg_int32; /* Box ID option */ if (config_lookup_int(&sec_cfg, "box_id", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"box_id\" element. Using default - 0x0\n"); + fprintf(stderr, "Error obtaining \"box_id\" element. "); + fprintf(stderr, "Using default - 0x0\n"); cfg_int32 = 0; } sec_opt->box_id = cfg_int32; /* Flash ID option */ - if (config_lookup_int(&sec_cfg, "flash_id", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"flash_id\" element. Using default - 0x0\n"); + if (config_lookup_int(&sec_cfg, "flash_id", + &cfg_int32) != CONFIG_TRUE) { + fprintf(stderr, "Error obtaining \"flash_id\" element. "); + fprintf(stderr, "Using default - 0x0\n"); cfg_int32 = 0; } sec_opt->flash_id = cfg_int32; /* CSK index option */ - if (config_lookup_int(&sec_cfg, "csk_key_index", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"flash_id\" element. Using default - 0x0\n"); + if (config_lookup_int(&sec_cfg, "csk_key_index", + &cfg_int32) != CONFIG_TRUE) { + fprintf(stderr, "Error obtaining \"flash_id\" element. " + fprintf(stderr, "Using default - 0x0\n"); cfg_int32 = 0; } sec_opt->csk_index = cfg_int32; @@ -717,8 +786,11 @@ int parse_sec_config_file(char *filename) } for (element = 0; element < CP_CTRL_EL_ARRAY_SZ; element++) { - sec_opt->cp_ctrl_arr[element] = config_setting_get_int_elem(control_array, element * 2); - sec_opt->cp_efuse_arr[element] = config_setting_get_int_elem(control_array, element * 2 + 1); + sec_opt->cp_ctrl_arr[element] = + config_setting_get_int_elem(control_array, element * 2); + sec_opt->cp_efuse_arr[element] = + config_setting_get_int_elem(control_array, + element * 2 + 1); } opts.sec_opts = sec_opt; @@ -742,7 +814,8 @@ int format_sec_ext(char *filename, FILE *out_fd) /* First, parse the configuration file */ if (parse_sec_config_file(filename)) { - printf("failed parsing configuration file %s\n", filename); + fprintf(stderr, + "failed parsing configuration file %s\n", filename); return 1; } @@ -762,19 +835,23 @@ int format_sec_ext(char *filename, FILE *out_fd) opts.sec_opts->kak_key_file : opts.sec_opts->csk_key_file[index]; uint8_t *out_der_key = (index == CSK_ARR_SZ) ? - sec_ext.kak_key : sec_ext.csk_keys[index]; + sec_ext.kak_key : + sec_ext.csk_keys[index]; size_t output_len; unsigned char output_buf[DER_BUF_SZ]; unsigned char *der_buf_start; /* Handle invalid/reserved file names */ - if (strncmp(CSK_ARR_EMPTY_FILE, fname, strlen(CSK_ARR_EMPTY_FILE)) == 0) { + if (strncmp(CSK_ARR_EMPTY_FILE, fname, + strlen(CSK_ARR_EMPTY_FILE)) == 0) { if (opts.sec_opts->csk_index == index) { - fprintf(stderr, "CSK file name with index %d cannot be %s\n", + fprintf(stderr, + "CSK file with index %d cannot be %s\n", index, CSK_ARR_EMPTY_FILE); return 1; } else if (index == CSK_ARR_SZ) { - fprintf(stderr, "KAK file name cannot be %s\n", CSK_ARR_EMPTY_FILE); + fprintf(stderr, "KAK file name cannot be %s\n", + CSK_ARR_EMPTY_FILE); return 1; } /* this key will be empty in CSK array */ @@ -782,36 +859,50 @@ int format_sec_ext(char *filename, FILE *out_fd) } mbedtls_pk_init(pk_ctx); - /* Read the private RSA key into the context and verify it (no password) */ + /* Read the private RSA key into the context + * and verify it (no password) + */ if (mbedtls_pk_parse_keyfile(pk_ctx, fname, "") != 0) { - fprintf(stderr, "Cannot read RSA private key file %s\n", fname); + fprintf(stderr, + "Cannot read RSA private key file %s\n", fname); return 1; } - /* Create a public key out of private one and store it in DER format */ - output_len = mbedtls_pk_write_pubkey_der(pk_ctx, output_buf, DER_BUF_SZ); + /* Create a public key out of private one + * and store it in DER format + */ + output_len = mbedtls_pk_write_pubkey_der(pk_ctx, + output_buf, + DER_BUF_SZ); if (output_len < 0) { - fprintf(stderr, "Failed to create DER coded PUB key (%s)\n", fname); + fprintf(stderr, + "Failed to create DER coded PUB key (%s)\n", + fname); return 1; } /* Data in the output buffer is aligned to the buffer end */ der_buf_start = output_buf + sizeof(output_buf) - output_len; - /* In the header DER data is aligned to the start of appropriate field */ + /* In the header DER data is aligned + * to the start of appropriate field + */ memcpy(out_der_key, der_buf_start, output_len); } /* for every private key file */ /* The CSK block signature can be created here */ if (create_rsa_signature(&opts.sec_opts->kak_pk, - &sec_ext.csk_keys[0][0], sizeof(sec_ext.csk_keys), - opts.sec_opts->csk_key_file[opts.sec_opts->csk_index], + &sec_ext.csk_keys[0][0], + sizeof(sec_ext.csk_keys), + opts.sec_opts->csk_key_file[ + opts.sec_opts->csk_index], sec_ext.csk_sign) != 0) { fprintf(stderr, "Failed to sign CSK keys block!\n"); return 1; } /* Check that everything is correct */ if (verify_rsa_signature(sec_ext.kak_key, MAX_RSA_DER_BYTE_LEN, - &sec_ext.csk_keys[0][0], sizeof(sec_ext.csk_keys), + &sec_ext.csk_keys[0][0], + sizeof(sec_ext.csk_keys), opts.sec_opts->kak_key_file, sec_ext.csk_sign) != 0) { fprintf(stderr, "Failed to verify CSK keys block signature!\n"); @@ -824,15 +915,21 @@ int format_sec_ext(char *filename, FILE *out_fd) in_fd = fopen(opts.sec_opts->aes_key_file, "rb"); if (in_fd == NULL) { - fprintf(stderr, "Failed to open AES key file %s\n", opts.sec_opts->aes_key_file); + fprintf(stderr, "Failed to open AES key file %s\n", + opts.sec_opts->aes_key_file); return 1; } /* Read the AES key in ASCII format byte by byte */ for (index = 0; index < AES_KEY_BYTE_LEN; index++) { - if (fscanf(in_fd, "%02hhx", opts.sec_opts->aes_key + index) != 1) { - fprintf(stderr, "Failed to read AES key byte %d from file %s\n", - index, opts.sec_opts->aes_key_file); + if (fscanf(in_fd, "%02hhx", + opts.sec_opts->aes_key + index) != 1) { + fprintf(stderr, + "Failed to read AES key byte %d ", + index); + fprintf(stderr, + "from file %s\n", + opts.sec_opts->aes_key_file); fclose(in_fd); return 1; } @@ -850,23 +947,29 @@ int format_sec_ext(char *filename, FILE *out_fd) sec_ext.jtag_delay = opts.sec_opts->jtag_delay; sec_ext.jtag_en = opts.sec_opts->jtag_enable; - memcpy(sec_ext.cp_ctrl_arr, opts.sec_opts->cp_ctrl_arr, sizeof(uint32_t) * CP_CTRL_EL_ARRAY_SZ); - memcpy(sec_ext.cp_efuse_arr, opts.sec_opts->cp_efuse_arr, sizeof(uint32_t) * CP_CTRL_EL_ARRAY_SZ); + memcpy(sec_ext.cp_ctrl_arr, + opts.sec_opts->cp_ctrl_arr, + sizeof(uint32_t) * CP_CTRL_EL_ARRAY_SZ); + memcpy(sec_ext.cp_efuse_arr, + opts.sec_opts->cp_efuse_arr, + sizeof(uint32_t) * CP_CTRL_EL_ARRAY_SZ); - /* Write the resulting extention to file + /* Write the resulting extension to file * (image and header signature fields are still empty) */ - /* Write extention header */ + /* Write extension header */ written = fwrite(&header, sizeof(ext_header_t), 1, out_fd); if (written != 1) { - fprintf(stderr, "Failed to write SEC extension header to the file\n"); + fprintf(stderr, + "Failed to write SEC extension header to the file\n"); return 1; } - /* Write extention body */ + /* Write extension body */ written = fwrite(&sec_ext, sizeof(sec_entry_t), 1, out_fd); if (written != 1) { - fprintf(stderr, "Failed to write SEC extension body to the file\n"); + fprintf(stderr, + "Failed to write SEC extension body to the file\n"); return 1; } @@ -874,21 +977,21 @@ int format_sec_ext(char *filename, FILE *out_fd) } /******************************************************************************* -* finalize_secure_ext -* Make final changes to secure extension - calculate image and header -* signatures and encrypt the image if needed. -* The main header checksum and image size fileds are updated accordingly -* INPUT: -* header Main header -* prolog_buf the entire prolog buffer -* prolog_size prolog buffer length -* image_buf buffer containing the input binary image -* image_size image buffer size. -* OUTPUT: -* none -* RETURN: -* 0 on success -*******************************************************************************/ + * finalize_secure_ext + * Make final changes to secure extension - calculate image and header + * signatures and encrypt the image if needed. + * The main header checksum and image size fields updated accordingly + * INPUT: + * header Main header + * prolog_buf the entire prolog buffer + * prolog_size prolog buffer length + * image_buf buffer containing the input binary image + * image_size image buffer size. + * OUTPUT: + * none + * RETURN: + * 0 on success + */ int finalize_secure_ext(header_t *header, uint8_t *prolog_buf, uint32_t prolog_size, uint8_t *image_buf, int image_size) @@ -900,16 +1003,18 @@ int finalize_secure_ext(header_t *header, sec_entry_t *sec_ext = 0; /* Find the Trusted Boot Header between available extensions */ - for (cur_ext = 0, offset = sizeof(header_t); cur_ext < header->ext_count; cur_ext++) { + for (cur_ext = 0, offset = sizeof(header_t); + cur_ext < header->ext_count; cur_ext++) { ext_header_t *ext_hdr = (ext_header_t *)(prolog_buf + offset); if (ext_hdr->type == EXT_TYPE_SECURITY) { - sec_ext = (sec_entry_t *)(prolog_buf + offset + sizeof(ext_header_t) + ext_hdr->offset); + sec_ext = (sec_entry_t *)(prolog_buf + offset + + sizeof(ext_header_t) + ext_hdr->offset); break; } offset += sizeof(ext_header_t); - /* If offset is Zero, the extention follows its header */ + /* If offset is Zero, the extension follows its header */ if (ext_hdr->offset == 0) offset += ext_hdr->size; } @@ -929,47 +1034,58 @@ int finalize_secure_ext(header_t *header, } /* Image size and checksum should be updated after encryption. - * This way the image could be verified by BootROM before decryption. + * This way the image could be verified by the BootROM + * before decryption. */ final_image = opts.sec_opts->encrypted_image; final_image_sz = opts.sec_opts->enc_image_sz; header->boot_image_size = final_image_sz; - header->boot_image_checksum = checksum32((uint32_t *)final_image, final_image_sz); + header->boot_image_checksum = + checksum32((uint32_t *)final_image, final_image_sz); } /* AES encryption */ /* Create the image signature first, since it will be later * signed along with the header signature */ - if (create_rsa_signature(&opts.sec_opts->csk_pk[opts.sec_opts->csk_index], + if (create_rsa_signature(&opts.sec_opts->csk_pk[ + opts.sec_opts->csk_index], final_image, final_image_sz, - opts.sec_opts->csk_key_file[opts.sec_opts->csk_index], + opts.sec_opts->csk_key_file[ + opts.sec_opts->csk_index], sec_ext->image_sign) != 0) { fprintf(stderr, "Failed to sign image!\n"); return -1; } /* Check that the image signature is correct */ - if (verify_rsa_signature(sec_ext->csk_keys[opts.sec_opts->csk_index], MAX_RSA_DER_BYTE_LEN, + if (verify_rsa_signature(sec_ext->csk_keys[opts.sec_opts->csk_index], + MAX_RSA_DER_BYTE_LEN, final_image, final_image_sz, - opts.sec_opts->csk_key_file[opts.sec_opts->csk_index], + opts.sec_opts->csk_key_file[ + opts.sec_opts->csk_index], sec_ext->image_sign) != 0) { fprintf(stderr, "Failed to verify image signature!\n"); return -1; } /* Sign the headers and all the extensions block - when the header signature field is empty */ - if (create_rsa_signature(&opts.sec_opts->csk_pk[opts.sec_opts->csk_index], + * when the header signature field is empty + */ + if (create_rsa_signature(&opts.sec_opts->csk_pk[ + opts.sec_opts->csk_index], prolog_buf, prolog_size, - opts.sec_opts->csk_key_file[opts.sec_opts->csk_index], + opts.sec_opts->csk_key_file[ + opts.sec_opts->csk_index], hdr_sign) != 0) { fprintf(stderr, "Failed to sign header!\n"); return -1; } /* Check that the header signature is correct */ - if (verify_rsa_signature(sec_ext->csk_keys[opts.sec_opts->csk_index], MAX_RSA_DER_BYTE_LEN, + if (verify_rsa_signature(sec_ext->csk_keys[opts.sec_opts->csk_index], + MAX_RSA_DER_BYTE_LEN, prolog_buf, prolog_size, - opts.sec_opts->csk_key_file[opts.sec_opts->csk_index], + opts.sec_opts->csk_key_file[ + opts.sec_opts->csk_index], hdr_sign) != 0) { fprintf(stderr, "Failed to verify header signature!\n"); return -1; @@ -989,9 +1105,11 @@ int finalize_secure_ext(header_t *header, #define FMT_BIN 2 #define FMT_NONE 3 -void do_print_field(unsigned int value, char *name, int start, int size, int format) +void do_print_field(unsigned int value, char *name, + int start, int size, int format) { - printf("[0x%05x : 0x%05x] %-26s", start, start + size - 1, name); + fprintf(stdout, "[0x%05x : 0x%05x] %-26s", + start, start + size - 1, name); switch (format) { case FMT_HEX: @@ -1006,8 +1124,9 @@ void do_print_field(unsigned int value, char *name, int start, int size, int for } } -#define print_field(st, type, field, hex, base) do_print_field((int)st->field, #field, \ - base + offsetof(type, field), sizeof(st->field), hex) +#define print_field(st, type, field, hex, base) \ + do_print_field((int)st->field, #field, \ + base + offsetof(type, field), sizeof(st->field), hex) int print_header(uint8_t *buf, int base) { @@ -1015,7 +1134,7 @@ int print_header(uint8_t *buf, int base) main_hdr = (header_t *)buf; - printf("########### Header ##############\n"); + fprintf(stdout, "########### Header ##############\n"); print_field(main_hdr, header_t, magic, FMT_HEX, base); print_field(main_hdr, header_t, prolog_size, FMT_DEC, base); print_field(main_hdr, header_t, prolog_checksum, FMT_HEX, base); @@ -1068,21 +1187,26 @@ void print_sec_ext(ext_header_t *ext_hdr, int base) print_field(sec_entry, sec_entry_t, encrypt_en, FMT_DEC, base); print_field(sec_entry, sec_entry_t, efuse_dis, FMT_DEC, base); new_base += 6 * sizeof(uint32_t); - do_print_field(0, "header signature", new_base, RSA_SIGN_BYTE_LEN, FMT_NONE); + do_print_field(0, "header signature", + new_base, RSA_SIGN_BYTE_LEN, FMT_NONE); new_base += RSA_SIGN_BYTE_LEN; - do_print_field(0, "image signature", new_base, RSA_SIGN_BYTE_LEN, FMT_NONE); + do_print_field(0, "image signature", + new_base, RSA_SIGN_BYTE_LEN, FMT_NONE); new_base += RSA_SIGN_BYTE_LEN; - do_print_field(0, "CSK keys", new_base, CSK_ARR_SZ * MAX_RSA_DER_BYTE_LEN, FMT_NONE); + do_print_field(0, "CSK keys", new_base, + CSK_ARR_SZ * MAX_RSA_DER_BYTE_LEN, FMT_NONE); new_base += CSK_ARR_SZ * MAX_RSA_DER_BYTE_LEN; - do_print_field(0, "CSK block signature", new_base, RSA_SIGN_BYTE_LEN, FMT_NONE); + do_print_field(0, "CSK block signature", + new_base, RSA_SIGN_BYTE_LEN, FMT_NONE); new_base += RSA_SIGN_BYTE_LEN; - do_print_field(0, "control", new_base, CP_CTRL_EL_ARRAY_SZ * 2, FMT_NONE); + do_print_field(0, "control", new_base, + CP_CTRL_EL_ARRAY_SZ * 2, FMT_NONE); } void print_bin_ext(ext_header_t *ext_hdr, int base) { - printf("\n########### Binary extension ###########\n"); + fprintf(stdout, "\n########### Binary extension ###########\n"); base = print_ext_hdr(ext_hdr, base); do_print_field(0, "binary image", base, ext_hdr->size, FMT_NONE); } @@ -1100,7 +1224,6 @@ int print_extension(void *buf, int base, int count, int ext_size) print_sec_ext(ext_hdr, base); curr_size = sizeof(ext_header_t) + ext_hdr->size; - base += curr_size; pad -= curr_size; ext_hdr = (ext_header_t *)((uintptr_t)ext_hdr + curr_size); @@ -1120,34 +1243,43 @@ int parse_image(uint8_t *buf, int size) uint32_t checksum, prolog_checksum; - printf("################### Prolog Start ######################\n\n"); + fprintf(stdout, + "################### Prolog Start ######################\n\n"); main_hdr = (header_t *)buf; base += print_header(buf, base); if (main_hdr->ext_count) - base += print_extension(buf + base, base, main_hdr->ext_count, - main_hdr->prolog_size - sizeof(header_t)); + base += print_extension(buf + base, base, + main_hdr->ext_count, + main_hdr->prolog_size - + sizeof(header_t)); if (base < main_hdr->prolog_size) { - printf("\n########### Padding ##############\n"); - do_print_field(0, "prolog padding", base, main_hdr->prolog_size - base, FMT_HEX); + fprintf(stdout, "\n########### Padding ##############\n"); + do_print_field(0, "prolog padding", + base, main_hdr->prolog_size - base, FMT_HEX); base = main_hdr->prolog_size; } - printf("\n################### Prolog End ######################\n"); + fprintf(stdout, + "\n################### Prolog End ######################\n"); - printf("\n################### Boot image ######################\n"); + fprintf(stdout, + "\n################### Boot image ######################\n"); do_print_field(0, "boot image", base, size - base - 4, FMT_NONE); - printf("################### Image end ########################\n"); + fprintf(stdout, + "################### Image end ########################\n"); /* Check sanity for certain values */ printf("\nChecking values:\n"); if (main_hdr->magic == MAIN_HDR_MAGIC) { - printf("Headers magic: OK!\n"); + fprintf(stdout, "Headers magic: OK!\n"); } else { - printf("\n****** ERROR: HEADER MAGIC 0x%08x != 0x%08x\n", main_hdr->magic, MAIN_HDR_MAGIC); + fprintf(stderr, + "\n****** ERROR: HEADER MAGIC 0x%08x != 0x%08x\n", + main_hdr->magic, MAIN_HDR_MAGIC); goto error; } @@ -1158,20 +1290,23 @@ int parse_image(uint8_t *buf, int size) checksum = checksum32((uint32_t *)buf, main_hdr->prolog_size); if (checksum == prolog_checksum) { - printf("Headers checksum: OK!\n"); + fprintf(stdout, "Headers checksum: OK!\n"); } else { - printf("\n****** ERROR: BAD HEADER CHECKSUM 0x%08x != 0x%08x ********\n", - checksum, prolog_checksum); + fprintf(stderr, + "\n***** ERROR: BAD HEADER CHECKSUM 0x%08x != 0x%08x\n", + checksum, prolog_checksum); goto error; } /* boot image checksum */ - checksum = checksum32((uint32_t *)(buf + main_hdr->prolog_size), main_hdr->boot_image_size); + checksum = checksum32((uint32_t *)(buf + main_hdr->prolog_size), + main_hdr->boot_image_size); if (checksum == main_hdr->boot_image_checksum) { - printf("Image checksum: OK!\n"); + fprintf(stdout, "Image checksum: OK!\n"); } else { - printf("\n****** ERROR: BAD IMAGE CHECKSUM 0x%08x != 0x%08x ********\n", - checksum, main_hdr->boot_image_checksum); + fprintf(stderr, + "\n****** ERROR: BAD IMAGE CHECKSUM 0x%08x != 0x%08x\n", + checksum, main_hdr->boot_image_checksum); goto error; } @@ -1185,25 +1320,35 @@ int parse_image(uint8_t *buf, int size) while (ext_num--) { if (ext_hdr->type == EXT_TYPE_SECURITY) { - sec_entry_t *sec_entry = (sec_entry_t *)(ext_hdr + 1); + sec_entry_t *sec_entry = + (sec_entry_t *)(ext_hdr + 1); - ret = verify_secure_header_signatures(main_hdr, sec_entry); + ret = verify_secure_header_signatures( + main_hdr, sec_entry); if (ret != 0) { - fprintf(stderr, "\n****** FAILED TO VERIFY RSA SIGNATURES ********\n"); + fprintf(stderr, + "\n****** FAILED TO VERIFY "); + fprintf(stderr, + "RSA SIGNATURES ********\n"); goto error; } - mbedtls_sha256(sec_entry->kak_key, MAX_RSA_DER_BYTE_LEN, hash, 0); - fprintf(stdout, ">>>>>>>>>>> KAK KEY HASH >>>>>>>>>>>\n"); + mbedtls_sha256(sec_entry->kak_key, + MAX_RSA_DER_BYTE_LEN, hash, 0); + fprintf(stdout, + ">>>>>>>>>> KAK KEY HASH >>>>>>>>>>\n"); fprintf(stdout, "SHA256: "); for (i = 0; i < 32; i++) fprintf(stdout, "%02X", hash[i]); - fprintf(stdout, "\n<<<<<<<<<<< KAK KEY HASH <<<<<<<<<<<\n"); + fprintf(stdout, + "\n<<<<<<<<< KAK KEY HASH <<<<<<<<<\n"); break; } - ext_hdr = (ext_header_t *)((uint8_t *)(ext_hdr + 1) + ext_hdr->size); + ext_hdr = + (ext_header_t *)((uint8_t *)(ext_hdr + 1) + + ext_hdr->size); } } #endif @@ -1223,13 +1368,14 @@ int format_bin_ext(char *filename, FILE *out_fd) in_fd = fopen(filename, "rb"); if (in_fd == NULL) { - printf("failed to open bin extension file %s\n", filename); + fprintf(stderr, "failed to open bin extension file %s\n", + filename); return 1; } size = get_file_size(filename); if (size <= 0) { - printf("bin extension file size is bad\n"); + fprintf(stderr, "bin extension file size is bad\n"); return 1; } @@ -1245,7 +1391,7 @@ int format_bin_ext(char *filename, FILE *out_fd) /* Write header */ written = fwrite(&header, sizeof(ext_header_t), 1, out_fd); if (written != 1) { - printf("failed writing header to extension file\n"); + fprintf(stderr, "failed writing header to extension file\n"); return 1; } @@ -1277,7 +1423,8 @@ int format_extensions(char *ext_filename) out_fd = fopen(ext_filename, "wb"); if (out_fd == NULL) { - printf("failed to open extension output file %s", ext_filename); + fprintf(stderr, "failed to open extension output file %s", + ext_filename); return 1; } @@ -1321,7 +1468,8 @@ void update_uart(header_t *header) * * ****************************************/ -int write_prolog(int ext_cnt, char *ext_filename, uint8_t *image_buf, int image_size, FILE *out_fd) +int write_prolog(int ext_cnt, char *ext_filename, + uint8_t *image_buf, int image_size, FILE *out_fd) { header_t *header; int main_hdr_size = sizeof(header_t); @@ -1335,12 +1483,13 @@ int write_prolog(int ext_cnt, char *ext_filename, uint8_t *image_buf, int image_ if (ext_cnt) prolog_size += get_file_size(ext_filename); - prolog_size = ((prolog_size + PROLOG_ALIGNMENT) & (~(PROLOG_ALIGNMENT-1))); + prolog_size = ((prolog_size + PROLOG_ALIGNMENT) & + (~(PROLOG_ALIGNMENT-1))); /* Allocate a zeroed buffer to zero the padding bytes */ buf = calloc(prolog_size, 1); if (buf == NULL) { - printf("Error: failed allocating checksum buffer\n"); + fprintf(stderr, "Error: failed allocating checksum buffer\n"); return 1; } @@ -1353,7 +1502,8 @@ int write_prolog(int ext_cnt, char *ext_filename, uint8_t *image_buf, int image_ header->ext_count = ext_cnt; header->aux_flags = 0; header->boot_image_size = (image_size + 3) & (~0x3); - header->boot_image_checksum = checksum32((uint32_t *)image_buf, image_size); + header->boot_image_checksum = checksum32((uint32_t *)image_buf, + image_size); update_uart(header); @@ -1361,13 +1511,16 @@ int write_prolog(int ext_cnt, char *ext_filename, uint8_t *image_buf, int image_ if (ext_cnt) { ext_fd = fopen(ext_filename, "rb"); if (ext_fd == NULL) { - printf("Error: failed to open extensions file\n"); + fprintf(stderr, + "Error: failed to open extensions file\n"); goto error; } - read = fread(&buf[main_hdr_size], get_file_size(ext_filename), 1, ext_fd); + read = fread(&buf[main_hdr_size], + get_file_size(ext_filename), 1, ext_fd); if (read != 1) { - printf("Error: failed to open extensions file\n"); + fprintf(stderr, + "Error: failed to open extensions file\n"); goto error; } @@ -1375,9 +1528,11 @@ int write_prolog(int ext_cnt, char *ext_filename, uint8_t *image_buf, int image_ /* Secure boot mode? */ if (opts.sec_opts != 0) { ret = finalize_secure_ext(header, (uint8_t *)buf, - prolog_size, image_buf, image_size); + prolog_size, image_buf, + image_size); if (ret != 0) { - printf("Error: failed to handle secure extension!\n"); + fprintf(stderr, "Error: failed to handle "); + fprintf(stderr, "secure extension!\n"); goto error; } } /* secure boot mode */ @@ -1390,7 +1545,8 @@ int write_prolog(int ext_cnt, char *ext_filename, uint8_t *image_buf, int image_ /* Now spill everything to output file */ written = fwrite(buf, prolog_size, 1, out_fd); if (written != 1) { - printf("Error: failed to write prolog to output file\n"); + fprintf(stderr, + "Error: failed to write prolog to output file\n"); goto error; } @@ -1411,7 +1567,7 @@ int write_boot_image(uint8_t *buf, uint32_t image_size, FILE *out_fd) written = fwrite(buf, aligned_size, 1, out_fd); if (written != 1) { - printf("Error: Failed to write boot image\n"); + fprintf(stderr, "Error: Failed to write boot image\n"); goto error; } @@ -1522,22 +1678,25 @@ int main(int argc, char *argv[]) /* Read the input file to buffer */ image_size = get_file_size(in_file); - image_buf = calloc((image_size + AES_BLOCK_SZ - 1) & ~(AES_BLOCK_SZ - 1), 1); + image_buf = calloc((image_size + AES_BLOCK_SZ - 1) & + ~(AES_BLOCK_SZ - 1), 1); if (image_buf == NULL) { - printf("Error: failed allocating input buffer\n"); + fprintf(stderr, "Error: failed allocating input buffer\n"); return 1; } read = fread(image_buf, image_size, 1, in_fd); if (read != 1) { - printf("Error: failed to read input file\n"); + fprintf(stderr, "Error: failed to read input file\n"); goto main_exit; } /* Parse the input image and leave */ if (parse) { if (opts.key_index >= CSK_ARR_SZ) { - fprintf(stderr, "Wrong key index value. Supported values 0 - %d\n", CSK_ARR_SZ - 1); + fprintf(stderr, + "Wrong key IDX value. Valid values 0 - %d\n", + CSK_ARR_SZ - 1); goto main_exit; } ret = parse_image(image_buf, image_size); @@ -1553,7 +1712,8 @@ int main(int argc, char *argv[]) out_fd = fopen(out_file, "wb"); if (out_fd == NULL) { - printf("Error: Failed to open output file %s\n", out_file); + fprintf(stderr, + "Error: Failed to open output file %s\n", out_file); goto main_exit; } @@ -1562,11 +1722,13 @@ int main(int argc, char *argv[]) goto main_exit; #ifdef CONFIG_MVEBU_SECURE_BOOT - if (opts.sec_opts && (opts.sec_opts->encrypted_image != 0) && (opts.sec_opts->enc_image_sz != 0)) - ret = write_boot_image(opts.sec_opts->encrypted_image, opts.sec_opts->enc_image_sz, out_fd); - else + if (opts.sec_opts && (opts.sec_opts->encrypted_image != 0) && + (opts.sec_opts->enc_image_sz != 0)) { + ret = write_boot_image(opts.sec_opts->encrypted_image, + opts.sec_opts->enc_image_sz, out_fd); + } else #endif - ret = write_boot_image(image_buf, image_size, out_fd); + ret = write_boot_image(image_buf, image_size, out_fd); if (ret) goto main_exit; diff --git a/tools/doimage/doimage.mk b/tools/doimage/doimage.mk index 24631cee..2b751d40 100644 --- a/tools/doimage/doimage.mk +++ b/tools/doimage/doimage.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses |