mvebu: cp110: introduce porting layer for sfi

Some of the xfi parameters depends on the hw connection between the SoC
and the PHY (~SFP cage) which can vary on different boards e.g. due to
different wire length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing phy-porting-layer.h),
the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h)
and the user is warn: "Using default comphy parameters - it may be need
to suit them for your board".

Change-Id: I1ab2ad8d282e642afa9c3da128fa48aee7bff48e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/57530
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>

19 files changed, 267 insertions, 23 deletions

diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 13d1405d..4982e5a7 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -5,6 +5,7 @@
  * https://spdx.org/licenses
  */
 
+#include <ap_setup.h>
 #include <debug.h>
 #include <delay_timer.h>
 #include <errno.h>
@@ -13,6 +14,13 @@
 #include <spinlock.h>
 #include "mvebu.h"
 #include "comphy-cp110.h"
+#include "phy-comphy-cp110.h"
+
+#if __has_include("phy-porting-layer.h")
+#include "phy-porting-layer.h"
+#else
+#include "phy-default-porting-layer.h"
+#endif
 
 /* #define DEBUG_COMPHY */
 #ifdef DEBUG_COMPHY
@@ -143,6 +151,23 @@ enum pcie_link_width {
 	PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
 };
 
+static void mvebu_cp110_get_ap_and_cp_nr(uint8_t *ap_nr, uint8_t *cp_nr, uint64_t comphy_base)
+{
+#if (AP_NUM == 1)
+	*ap_nr = 0;
+#else
+	*ap_nr = (((comphy_base & ~0xffffff) - MVEBU_AP_IO_BASE(0)) /
+			 AP_IO_OFFSET);
+#endif
+
+	*cp_nr = (((comphy_base & ~0xffffff) - MVEBU_AP_IO_BASE(*ap_nr)) /
+		 MVEBU_CP_OFFSET);
+
+	debug("cp_base 0x%llx, ap_io_base 0x%lx, cp_offset 0x%lx\n",
+	       comphy_base, (unsigned long)MVEBU_AP_IO_BASE(*ap_nr),
+	       (unsigned long)MVEBU_CP_OFFSET);
+}
+
 static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val,
 		  uint32_t mask, uint32_t usec_timout, enum reg_width_type type)
 {
@@ -778,15 +803,37 @@ static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base,
 	return ret;
 }
 
-static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, uint8_t comphy_index,
+static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
+					   uint8_t comphy_index,
 					   uint32_t comphy_mode)
 {
 	uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
 	uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
 	int ret = 0;
+	uint8_t ap_nr, cp_nr;
 
 	debug_enter();
 
+	mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
+
+	const struct xfi_params *xfi_static_values =
+			     &xfi_static_values_tab[ap_nr][cp_nr][comphy_index];
+
+	debug("%s: the ap_nr = %d, cp_nr = %d, comphy_index %d\n",
+	      __func__, ap_nr, cp_nr, comphy_index);
+
+	debug("Using g1_ffe_cap_sel = 0x%x, g1_ffe_res_sel = 0x%x, g1_dfe_res = 0x%x\n",
+	       xfi_static_values->g1_ffe_cap_sel, xfi_static_values->g1_ffe_res_sel,
+	       xfi_static_values->g1_dfe_res);
+
+	if (!xfi_static_values->valid) {
+		ERROR("[ap%d][cp[%d][comphy:%d]: Has no valid static params\n",
+		      ap_nr, cp_nr, comphy_index);
+		ERROR("[ap%d][cp[%d][comphy:%d]: porting layer need to be updated\n",
+		      ap_nr, cp_nr, comphy_index);
+		return -EINVAL;
+	}
+
 	if ((speed != COMPHY_SPEED_5_15625G) &&
 	     (speed != COMPHY_SPEED_10_3125G) &&
 	     (speed != COMPHY_SPEED_DEFAULT)) {
@@ -912,16 +959,21 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, uint8_t comphy_
 		data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
 	} else {
 		mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
-		data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
+		data = xfi_static_values->g1_amp << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
 		mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
-		data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+		data |= xfi_static_values->g1_emph << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+
+		mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
+		data |= xfi_static_values->g1_emph_en << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
+		mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
+		data |= xfi_static_values->g1_tx_amp_adj << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
 	}
 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
 	/* Genration 1 setting 2 (G1_Setting_2) */
 	mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
-	data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
+	data = xfi_static_values->g1_tx_emph << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
 	mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
-	data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
+	data |= xfi_static_values->g1_tx_emph_en << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
 	/* Transmitter Slew Rate Control register (tx_reg1) */
 	mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
@@ -950,13 +1002,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, uint8_t comphy_
 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
 	} else {
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
-		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+		data |= xfi_static_values->g1_rx_selmupi << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
-		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+		data |= xfi_static_values->g1_rx_selmupf << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
-		data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
+		data |= xfi_static_values->g1_rx_selmufi << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
-		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
+		data |= xfi_static_values->g1_rx_selmuff << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
 		mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
 		data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
 	}
@@ -984,8 +1036,39 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, uint8_t comphy_
 		data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
 		data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
+		reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+	} else {
+		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
+		data |= xfi_static_values->g1_ffe_cap_sel <<
+			HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
+		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
+		data |= xfi_static_values->g1_ffe_res_sel <<
+			HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
+		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
+		data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
+		reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+
+		/* Use the value from CAL_OS_PH_EXT */
+		mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
+		data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
+		reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, data, mask);
+
+		/* Update align90 */
+		mask = HPIPE_CAL_OS_PH_EXT_MASK;
+		data = xfi_static_values->align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
+		reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, data, mask);
+
+		/* Force DFE resolution (use gen table value) */
+		mask = HPIPE_DFE_RES_FORCE_MASK;
+		data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
+		reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
+
+		/* 0x111-G1 DFE_Setting_4 */
+		mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
+		data = xfi_static_values->g1_dfe_res <<
+			HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
+		reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
 	}
-	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
 
 	/* Connfigure RX training timer */
 	mask = HPIPE_RX_TRAIN_TIMER_MASK;
@@ -1892,9 +1975,13 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
 int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 					      uint8_t comphy_index)
 {
-	uint32_t mask, data, timeout, ffe_cap, ffe_res, align90, adapted_dfe;
+	uint32_t mask, data, timeout, g1_ffe_cap_sel, g1_ffe_res_sel, align90, g1_dfe_res;
 	uintptr_t hpipe_addr, sd_ip_addr;
 
+	uint8_t ap_nr, cp_nr;
+
+	mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
+
 	hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
 				comphy_index);
 	sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index);
@@ -2001,11 +2088,11 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 	debug("Training done, reading results...\n\n");
 
 	mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK;
-	ffe_res = ((mmio_read_32(hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG)
+	g1_ffe_res_sel = ((mmio_read_32(hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG)
 		    & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET);
 
 	mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK;
-	ffe_cap = ((mmio_read_32(hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG)
+	g1_ffe_cap_sel = ((mmio_read_32(hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG)
 		    & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET);
 
 	mask = HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK;
@@ -2013,13 +2100,13 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 		    & mask) >> HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET);
 
 	mask = HPIPE_ADAPTED_DFE_RES_MASK;
-	adapted_dfe = ((mmio_read_32(hpipe_addr + HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG)
+	g1_dfe_res = ((mmio_read_32(hpipe_addr + HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG)
 		    & mask) >> HPIPE_ADAPTED_DFE_RES_OFFSET);
 
 	debug("================================================\n");
 	debug("Switching to static configuration:\n");
-	debug("FFE_RES = 0x%x FFE_CAP = 0x%x align90 = 0x%x adapted_dfe 0x%x\n",
-	       ffe_res, ffe_cap, align90, adapted_dfe);
+	debug("FFE_RES = 0x%x FFE_CAP = 0x%x align90 = 0x%x g1_dfe_res 0x%x\n",
+	       g1_ffe_res_sel, g1_ffe_cap_sel, align90, g1_dfe_res);
 	debug("Full results after training: 0x%lx = 0x%x, 0x%lx = 0x%x, 0x%lx = 0x%x\n",
 	       (hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG),
 	       mmio_read_32(hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG),
@@ -2031,12 +2118,12 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 
 	/* Update FFE_RES */
 	mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
-	data = ffe_res << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
+	data = g1_ffe_res_sel << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
 
 	/* Update FFE_CAP */
 	mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
-	data = ffe_cap << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
+	data = g1_ffe_cap_sel << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
 
 	/* Bypass the FFE table settings and use the FFE settings directly from
@@ -2063,7 +2150,7 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 
 	/* 0x111-G1 DFE_Setting_4 */
 	mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
-	data = adapted_dfe << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
+	data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
 
 	debug("PRBS31 loppback\n\n");
@@ -2098,6 +2185,21 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
 	data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
 	reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
 
+	tf_printf("#################################################################\n");
+	tf_printf("# To use trained values update the ATF sources:\n");
+	tf_printf("# plat/marvell/a8k/<board_type>/board/phy-porting-layer.h file with new values\n");
+	tf_printf("# as below (for appiorpiate AP nr %d and CP nr: %d comphy_index %d\n\n",
+		  ap_nr, cp_nr, comphy_index);
+	tf_printf("static struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {\n");
+	tf_printf("\t...\n");
+	tf_printf("\t.g1_ffe_res_sel = 0x%x,\n", g1_ffe_res_sel);
+	tf_printf("\t.g1_ffe_cap_sel = 0x%x,\n", g1_ffe_cap_sel);
+	tf_printf("\t.align90 = 0x%x,\n", align90);
+	tf_printf("\t.g1_dfe_res = 0x%x\n", g1_dfe_res);
+	tf_printf("\t...\n");
+	tf_printf("};\n\n");
+	tf_printf("#################################################################\n");
+
 	/* check */
 	debug("PRBS error counter[0x%lx] 0x%x\n\n",
 	       hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG,
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index 2dab73d1..5eebd39b 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -5,6 +5,28 @@
  * https://spdx.org/licenses
  */
 
+/* Those are parameters for xfi mode, which need to be tune for each board type.
+ * For known DB boards the parameters was already calibrated and placed under
+ * the plat/marvell/a8k/<board_type>/board/phy-porting-layer.h
+ */
+struct xfi_params {
+	uint8_t g1_ffe_res_sel;
+	uint8_t g1_ffe_cap_sel;
+	uint8_t align90;
+	uint8_t g1_dfe_res;
+	uint8_t g1_amp;
+	uint8_t g1_emph;
+	uint8_t g1_emph_en;
+	uint8_t g1_tx_amp_adj;
+	uint8_t g1_tx_emph_en;
+	uint8_t g1_tx_emph;
+	uint8_t g1_rx_selmuff;
+	uint8_t g1_rx_selmufi;
+	uint8_t g1_rx_selmupf;
+	uint8_t g1_rx_selmupi;
+	_Bool valid;
+};
+
 int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, uint8_t comphy_index);
 int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint8_t comphy_index);
 int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index, uint64_t comphy_mode);
diff --git a/drivers/marvell/comphy/phy-default-porting-layer.h b/drivers/marvell/comphy/phy-default-porting-layer.h
new file mode 100644
index 00000000..0248ac6a
--- /dev/null
+++ b/drivers/marvell/comphy/phy-default-porting-layer.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef __PHY_DEFAULT_PORTING_LAYER_H
+#define __PHY_DEFAULT_PORTING_LAYER_H
+
+
+#define MAX_LANE_NR		6
+
+#warning "Using default comphy parameters - it may be need to suit them for your board"
+
+static const struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+		.g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
+		.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
+		.g1_emph_en = 1, .g1_tx_amp_adj = 1, .g1_tx_emph_en = 1,
+		.g1_tx_emph = 0, .g1_rx_selmuff = 2, .g1_rx_selmufi = 0x3,
+		.g1_rx_selmupf = 0x1, .g1_rx_selmupi = 6, .valid = 1
+	}
+};
+
+#endif /* __PHY_DEFAULT_PORTING_LAYER_H */
diff --git a/plat/marvell/a8k-p/a8xxy/platform.mk b/plat/marvell/a8k-p/a8xxy/platform.mk
index cf37bf98..ba73a809 100644
--- a/plat/marvell/a8k-p/a8xxy/platform.mk
+++ b/plat/marvell/a8k-p/a8xxy/platform.mk
@@ -8,3 +8,5 @@
 include plat/marvell/a8k-p/common/a8kp_common.mk
 
 include plat/marvell/common/marvell_common.mk
+
+PLAT_INCLUDES		+=	-Iplat/marvell/a8k-p/a8xxy/board
diff --git a/plat/marvell/a8k-p/common/a8kp_common.mk b/plat/marvell/a8k-p/common/a8kp_common.mk
index 449703e1..d03f7fe7 100644
--- a/plat/marvell/a8k-p/common/a8kp_common.mk
+++ b/plat/marvell/a8k-p/common/a8kp_common.mk
@@ -25,6 +25,9 @@ CP_NUM			:= 2
 endif
 $(eval $(call add_define,CP_NUM))
 
+AP_NUM			:= 2
+$(eval $(call add_define,AP_NUM))
+
 DOIMAGEPATH		?=	tools/doimage
 DOIMAGETOOL		?=	${DOIMAGEPATH}/doimage
 
diff --git a/plat/marvell/a8k-p/common/include/a8kp_plat_def.h b/plat/marvell/a8k-p/common/include/a8kp_plat_def.h
index 45c17ac6..b0bc3e51 100644
--- a/plat/marvell/a8k-p/common/include/a8kp_plat_def.h
+++ b/plat/marvell/a8k-p/common/include/a8kp_plat_def.h
@@ -89,10 +89,12 @@
 #define MVEBU_CP_DEFAULT_BASE_ADDR		0xF2000000
 #define MVEBU_CP_DEFAULT_BASE_SIZE		0x2000000
 
+#define AP_IO_OFFSET				0x1d00000000
 /* 116GB per AP starting on top of DRAM region - 516GB */
-#define MVEBU_AP_IO_BASE(ap)			(0x8100000000 + (ap) * 0x1d00000000)
+#define MVEBU_AP_IO_BASE(ap)			(0x8100000000 + (ap) * AP_IO_OFFSET)
 /* 28GB per each CP starting at AP base + 4GB for SPI/STM region */
-#define MVEBU_CP_REGS_BASE(ap, cp)		(MVEBU_AP_IO_BASE(ap) + (cp) * 0x700000000)
+#define MVEBU_CP_OFFSET				0x700000000
+#define MVEBU_CP_REGS_BASE(ap, cp)		(MVEBU_AP_IO_BASE(ap) + (cp) * MVEBU_CP_OFFSET)
 
 #define MVEBU_CP_DFX_OFFSET			(0x400200)
 
diff --git a/plat/marvell/a8k/a3900/platform.mk b/plat/marvell/a8k/a3900/platform.mk
index f6673dc5..d4eb1599 100644
--- a/plat/marvell/a8k/a3900/platform.mk
+++ b/plat/marvell/a8k/a3900/platform.mk
@@ -7,10 +7,13 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/ap807_setup.c
 
 include plat/marvell/a8k/common/a8k_common.mk
 
-include plat/marvell/common/marvell_common.mk
\ No newline at end of file
+include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a3900_z1/platform.mk b/plat/marvell/a8k/a3900_z1/platform.mk
index d5861e2f..173a44ee 100644
--- a/plat/marvell/a8k/a3900_z1/platform.mk
+++ b/plat/marvell/a8k/a3900_z1/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/a70x0/platform.mk b/plat/marvell/a8k/a70x0/platform.mk
index d5861e2f..173a44ee 100644
--- a/plat/marvell/a8k/a70x0/platform.mk
+++ b/plat/marvell/a8k/a70x0/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/a70x0_amc/platform.mk b/plat/marvell/a8k/a70x0_amc/platform.mk
index d5861e2f..173a44ee 100644
--- a/plat/marvell/a8k/a70x0_amc/platform.mk
+++ b/plat/marvell/a8k/a70x0_amc/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/a70x0_cust/platform.mk b/plat/marvell/a8k/a70x0_cust/platform.mk
index d5861e2f..173a44ee 100644
--- a/plat/marvell/a8k/a70x0_cust/platform.mk
+++ b/plat/marvell/a8k/a70x0_cust/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/a70x0_pcac/platform.mk b/plat/marvell/a8k/a70x0_pcac/platform.mk
index 06ddf0ad..bc8c878f 100644
--- a/plat/marvell/a8k/a70x0_pcac/platform.mk
+++ b/plat/marvell/a8k/a70x0_pcac/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 1
 
+CP_NUM			:= 1
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_7K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
new file mode 100644
index 00000000..c670b917
--- /dev/null
+++ b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:     BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef __PHY_PORTING_LAYER_H
+#define __PHY_PORTING_LAYER_H
+
+#define MAX_LANE_NR		6
+
+static const struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+	/* AP0 */
+	{
+		/* CP 0 */
+		{
+			{ 0 }, /* Comphy0 */
+			{ 0 }, /* Comphy1 */
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
+				.g1_rx_selmuff = 0x2, .g1_rx_selmufi = 0x3,
+				.g1_rx_selmupf = 0x1, .g1_rx_selmupi = 0x6,
+				.valid = 0x1 }, /* Comphy2 */
+			{ 0 }, /* Comphy3 */
+			{ 0 }, /* Comphy4 */
+			{ 0 }, /* Comphy5 */
+		},
+
+		/* CP 1 */
+		{
+			{ 0 }, /* Comphy0 */
+			{ 0 }, /* Comphy1 */
+			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
+				.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
+				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
+				.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
+				.g1_rx_selmuff = 0x2, .g1_rx_selmufi = 0x3,
+				.g1_rx_selmupf = 0x1, .g1_rx_selmupi = 0x6,
+				.valid = 0x1 }, /* Comphy2 */
+			{ 0 }, /* Comphy3 */
+			{ 0 }, /* Comphy4 */
+			{ 0 }, /* Comphy5 */
+		},
+	},
+};
+
+#endif /* __PHY_PORTING_LAYER_H */
diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/a8k/a80x0/platform.mk
index 4c0ab006..4b96ae3f 100644
--- a/plat/marvell/a8k/a80x0/platform.mk
+++ b/plat/marvell/a8k/a80x0/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 2
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_8K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
@@ -14,3 +17,4 @@ MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
 include plat/marvell/a8k/common/a8k_common.mk
 
 include plat/marvell/common/marvell_common.mk
+PLAT_INCLUDES		+=	-Iplat/marvell/a8k/a80x0/board
diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk
index 4e90dbcc..142d987b 100644
--- a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk
+++ b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk
@@ -4,6 +4,9 @@
 # SPDX-License-Identifier:     BSD-3-Clause
 # https://spdx.org/licenses
 
+CP_NUM			:= 2
+$(eval $(call add_define,CP_NUM))
+
 include plat/marvell/a8k/common/a8k_common.mk
 
 include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a80x0_mcbin/platform.mk b/plat/marvell/a8k/a80x0_mcbin/platform.mk
index 4c0ab006..667f1d27 100644
--- a/plat/marvell/a8k/a80x0_mcbin/platform.mk
+++ b/plat/marvell/a8k/a80x0_mcbin/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 0
 
+CP_NUM			:= 2
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_8K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/a80x0_ocp/platform.mk b/plat/marvell/a8k/a80x0_ocp/platform.mk
index cb97af8c..42cbeb01 100644
--- a/plat/marvell/a8k/a80x0_ocp/platform.mk
+++ b/plat/marvell/a8k/a80x0_ocp/platform.mk
@@ -7,6 +7,9 @@
 
 PCI_EP_SUPPORT		:= 1
 
+CP_NUM			:= 2
+$(eval $(call add_define,CP_NUM))
+
 DOIMAGE_SEC     	:=	tools/doimage/secure/sec_img_8K.cfg
 
 MARVELL_MOCHI_DRV	:=	drivers/marvell/mochi/apn806_setup.c
diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk
index 3bc452fb..64886ea4 100644
--- a/plat/marvell/a8k/common/a8k_common.mk
+++ b/plat/marvell/a8k/common/a8k_common.mk
@@ -25,6 +25,10 @@ $(eval $(call add_define,BL31_CACHE_DISABLE))
 $(eval $(call add_define,PCI_EP_SUPPORT))
 $(eval $(call assert_boolean,PCI_EP_SUPPORT))
 
+
+AP_NUM			:= 1
+$(eval $(call add_define,AP_NUM))
+
 DOIMAGEPATH		?=	tools/doimage
 DOIMAGETOOL		?=	${DOIMAGEPATH}/doimage
 
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h
index 57a5c242..80607d93 100644
--- a/plat/marvell/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/a8k/common/include/a8k_plat_def.h
@@ -32,7 +32,9 @@
 #define MVEBU_REGS_BASE			0xF0000000
 #define MVEBU_REGS_BASE_MASK		0xF0000000
 #define MVEBU_REGS_BASE_AP(ap)		MVEBU_REGS_BASE
-#define MVEBU_CP_REGS_BASE(cp_index)	(0xF2000000 + (cp_index) * 0x2000000)
+#define MVEBU_AP_IO_BASE(ap)		0xF2000000
+#define MVEBU_CP_OFFSET			0x2000000
+#define MVEBU_CP_REGS_BASE(cp_index)	(MVEBU_AP_IO_BASE(0) + (cp_index) * MVEBU_CP_OFFSET)
 #define MVEBU_RFU_BASE			(MVEBU_REGS_BASE + 0x6F0000)
 #define MVEBU_IO_WIN_BASE(ap_index)	(MVEBU_RFU_BASE)
 #define MVEBU_IO_WIN_GCR_OFFSET		(0x70)