mvebu: cp110: fix XFI link down problem

This patch fixes an issue on Armada7040/8040-DB,
when a XFI port is enabled, the link is not established.

This is caused due to changes in commit:
c14a9cf9535f ('commit mvebu: cp110: introduce porting layer for sfi').

This patch has the following updates:
- Fix incorrect static values in SFI configuration:
	g1_rx_selmuff, g1_rx_selmufi,
	g1_rx_selmupf, g1_rx_selmupi
- Update HPIPE_G1_SETTINGS_3_REG configuration.
- Remove the following settings:
	HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG
	HPIPE_DFE_REG0
	HPIPE_G1_SETTINGS_4_REG

In addition, cosmetic change in xfi_static_values_tab struct -
add 0x prefix for the values, to avoid inconsistency.

Change-Id: I97cb5f63504b6d16ccbc0b73c5ea037a83e8ba49
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/58930
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

3 files changed, 8 insertions, 40 deletions

diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 6e7be7f3..3478e442 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -1131,40 +1131,8 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
 		data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
 		data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
-		reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
-	} else {
-		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
-		data |= xfi_static_values->g1_ffe_cap_sel <<
-			HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
-		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
-		data |= xfi_static_values->g1_ffe_res_sel <<
-			HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
-		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
-		data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
-		reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
-
-		/* Use the value from CAL_OS_PH_EXT */
-		mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
-		data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
-		reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, data, mask);
-
-		/* Update align90 */
-		mask = HPIPE_CAL_OS_PH_EXT_MASK;
-		data = xfi_static_values->align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
-		reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, data, mask);
-
-		/* Force DFE resolution (use gen table value) */
-		mask = HPIPE_DFE_RES_FORCE_MASK;
-		data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
-		reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
-
-		/* 0x111-G1 DFE_Setting_4 */
-		mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
-		data = xfi_static_values->g1_dfe_res <<
-			HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
-		reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
 	}
-
+	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
 	/* Connfigure RX training timer */
 	mask = HPIPE_RX_TRAIN_TIMER_MASK;
 	data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
diff --git a/drivers/marvell/comphy/phy-default-porting-layer.h b/drivers/marvell/comphy/phy-default-porting-layer.h
index 44358940..6999b5cb 100644
--- a/drivers/marvell/comphy/phy-default-porting-layer.h
+++ b/drivers/marvell/comphy/phy-default-porting-layer.h
@@ -17,9 +17,9 @@ static const struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR
 	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
 		.g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
 		.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
-		.g1_emph_en = 1, .g1_tx_amp_adj = 1, .g1_tx_emph_en = 1,
-		.g1_tx_emph = 0, .g1_rx_selmuff = 2, .g1_rx_selmufi = 0x3,
-		.g1_rx_selmupf = 0x1, .g1_rx_selmupi = 6, .valid = 1
+		.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
+		.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
+		.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, .valid = 1
 	}
 };
 
diff --git a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
index a7cfe222..08a0f150 100644
--- a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
+++ b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
@@ -21,8 +21,8 @@ static const struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR
 				.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
 				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
 				.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
-				.g1_rx_selmuff = 0x2, .g1_rx_selmufi = 0x3,
-				.g1_rx_selmupf = 0x1, .g1_rx_selmupi = 0x6,
+				.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
 				.valid = 0x1 }, /* Comphy2 */
 			{ 0 }, /* Comphy3 */
 			{ 0 }, /* Comphy4 */
@@ -37,8 +37,8 @@ static const struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR
 				.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
 				.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
 				.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
-				.g1_rx_selmuff = 0x2, .g1_rx_selmufi = 0x3,
-				.g1_rx_selmupf = 0x1, .g1_rx_selmupi = 0x6,
+				.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
+				.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
 				.valid = 0x1 }, /* Comphy2 */
 			{ 0 }, /* Comphy3 */
 			{ 0 }, /* Comphy4 */