diff options
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2018-08-20 16:00:47 +0200 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2018-08-21 17:27:48 +0300 |
| commit | efcc4ef109ecf6bbfda65e5a1dedfba5c04d1470 (patch) | |
| tree | f89468269e2a4b8ed1090255021ffe26a450fc48 | |
| parent | 799b09e05e29d147a9bd789ba89e73f9cf8b6f3e (diff) | |
mvebu: cp110: restore some sfi/xfi sequences
This commit partially reverts the "mvebu: cp110: fix XFI link down
problem" patch. The static values introduced by mentioned commit are
preserved but other registers accesses used during SFI/SFI configuration
are restored.
This partially reverts commit 3bfdf10d8b077dc1eb49d872fbf21bddbb7f7c28.
Change-Id: I40320d6db7aab14012449c3154a0bcd26f873507
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/59264
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | drivers/marvell/comphy/phy-comphy-cp110.c | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index 3478e442..a30ac8dc 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -1131,8 +1131,44 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + } else { + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; + data |= xfi_static_values->g1_ffe_cap_sel << + HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; + data |= xfi_static_values->g1_ffe_res_sel << + HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; + data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + + /* Use the value from CAL_OS_PH_EXT */ + mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK; + data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET; + reg_set(hpipe_addr + + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, + data, mask); + + /* Update align90 */ + mask = HPIPE_CAL_OS_PH_EXT_MASK; + data = xfi_static_values->align90 << HPIPE_CAL_OS_PH_EXT_OFFSET; + reg_set(hpipe_addr + + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, + data, mask); + + /* Force DFE resolution (use gen table value) */ + mask = HPIPE_DFE_RES_FORCE_MASK; + data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); + + /* 0x111-G1 DFE_Setting_4 */ + mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; + data = xfi_static_values->g1_dfe_res << + HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); } - reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + /* Connfigure RX training timer */ mask = HPIPE_RX_TRAIN_TIMER_MASK; data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; |