platform: Add support for Marvell A7K/A8K platforms

Add platform support files for Marvell A7K and A7K SoC
families.

Change-Id: I4f8b0a7cd222be5b7f43577172f1cdba58ffc124
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37918

45 files changed, 5535 insertions, 0 deletions

diff --git a/include/plat/marvell/a8k/common/arm_def.h b/include/plat/marvell/a8k/common/arm_def.h
new file mode 100644
index 00000000..d2190077
--- /dev/null
+++ b/include/plat/marvell/a8k/common/arm_def.h
@@ -0,0 +1,260 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __MARVELL_DEF_H__
+#define __MARVELL_DEF_H__
+
+#include <arch.h>
+#include <common_def.h>
+#include <platform_def.h>
+#include <tbbr_img_def.h>
+#include <xlat_tables.h>
+
+
+/******************************************************************************
+ * Definitions common to all MARVELL standard platforms
+ *****************************************************************************/
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define MARVELL_BL31_PLAT_PARAM_VAL		0x0f1e2d3c4b5a6978ULL
+
+
+#define MARVELL_CACHE_WRITEBACK_SHIFT	6
+
+/*
+ * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
+ * The power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define MARVELL_PWR_LVL0		MPIDR_AFFLVL0
+#define MARVELL_PWR_LVL1		MPIDR_AFFLVL1
+#define MARVELL_PWR_LVL2		MPIDR_AFFLVL2
+
+/*
+ *  Macros for local power states in Marvell platforms encoded by
+ *  State-ID field within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define MARVELL_LOCAL_STATE_RUN	0
+/* Local power state for retention. Valid only for CPU power domains */
+#define MARVELL_LOCAL_STATE_RET	1
+/*
+ * Local power state for OFF/power-down. Valid for CPU
+ * and cluster power domains
+ */
+#define MARVELL_LOCAL_STATE_OFF	2
+
+/* The first 4KB of Trusted SRAM are used as shared memory */
+#define MARVELL_TRUSTED_SRAM_BASE	PLAT_MARVELL_ATF_BASE
+#define MARVELL_SHARED_RAM_BASE		MARVELL_TRUSTED_SRAM_BASE
+#define MARVELL_SHARED_RAM_SIZE		0x00001000	/* 4 KB */
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define MARVELL_BL_RAM_BASE		(MARVELL_SHARED_RAM_BASE +	\
+					 MARVELL_SHARED_RAM_SIZE)
+#define MARVELL_BL_RAM_SIZE		(PLAT_MARVELL_TRUSTED_SRAM_SIZE - \
+					 MARVELL_SHARED_RAM_SIZE)
+
+#define MARVELL_NS_DRAM1_BASE		MARVELL_DRAM1_BASE
+#define MARVELL_NS_DRAM1_SIZE		MARVELL_DRAM1_SIZE
+#define MARVELL_NS_DRAM1_END		(MARVELL_NS_DRAM1_BASE + \
+					 MARVELL_NS_DRAM1_SIZE - 1)
+
+#define MARVELL_DRAM1_BASE		MAKE_ULL(0x0)
+#define MARVELL_DRAM1_SIZE		MAKE_ULL(0x80000000)
+#define MARVELL_DRAM1_END		(MARVELL_DRAM1_BASE + \
+					 MARVELL_DRAM1_SIZE - 1)
+
+#define MARVELL_IRQ_SEC_PHY_TIMER	29
+
+#define MARVELL_IRQ_SEC_SGI_0		8
+#define MARVELL_IRQ_SEC_SGI_1		9
+#define MARVELL_IRQ_SEC_SGI_2		10
+#define MARVELL_IRQ_SEC_SGI_3		11
+#define MARVELL_IRQ_SEC_SGI_4		12
+#define MARVELL_IRQ_SEC_SGI_5		13
+#define MARVELL_IRQ_SEC_SGI_6		14
+#define MARVELL_IRQ_SEC_SGI_7		15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define MARVELL_G1S_IRQS		MARVELL_IRQ_SEC_PHY_TIMER,	\
+					MARVELL_IRQ_SEC_SGI_1,		\
+					MARVELL_IRQ_SEC_SGI_2,		\
+					MARVELL_IRQ_SEC_SGI_3,		\
+					MARVELL_IRQ_SEC_SGI_4,		\
+					MARVELL_IRQ_SEC_SGI_5,		\
+					MARVELL_IRQ_SEC_SGI_7
+
+#define MARVELL_G0_IRQS			MARVELL_IRQ_SEC_SGI_0,		\
+					MARVELL_IRQ_SEC_SGI_6
+
+#define MARVELL_MAP_SHARED_RAM		MAP_REGION_FLAT(		\
+						MARVELL_SHARED_RAM_BASE,\
+						MARVELL_SHARED_RAM_SIZE,\
+						MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MARVELL_MAP_NS_DRAM1		MAP_REGION_FLAT(		\
+						MARVELL_NS_DRAM1_BASE,	\
+						MARVELL_NS_DRAM1_SIZE,	\
+						MT_MEMORY | MT_RW | MT_NS)
+
+
+/*
+ * The number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#if USE_COHERENT_MEM
+#define MARVELL_BL_REGIONS		3
+#else
+#define MARVELL_BL_REGIONS		2
+#endif
+
+#define MAX_MMAP_REGIONS		(PLAT_MARVELL_MMAP_ENTRIES +	\
+					 MARVELL_BL_REGIONS)
+
+#if PALLADIUM
+#define MARVELL_CONSOLE_BAUDRATE	24000
+#else
+#define MARVELL_CONSOLE_BAUDRATE	115200
+#endif
+
+/******************************************************************************
+ * Required platform porting definitions common to all MARVELL std. platforms
+ *****************************************************************************/
+
+#define ADDR_SPACE_SIZE			(1ull << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE		MARVELL_LOCAL_STATE_RET
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE		MARVELL_LOCAL_STATE_OFF
+
+
+#define PLATFORM_CORE_COUNT		PLAT_MARVELL_CORE_COUNT
+#define PLAT_NUM_PWR_DOMAINS		(PLAT_MARVELL_CLUSTER_COUNT +	\
+					 PLATFORM_CORE_COUNT)
+
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE		(1 << MARVELL_CACHE_WRITEBACK_SHIFT)
+
+
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
+ * addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE			PLAT_MARVELL_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT			(PLAT_MARVELL_TRUSTED_ROM_BASE	\
+					 + PLAT_MARVELL_TRUSTED_ROM_SIZE)
+/*
+ * Put BL1 RW at the top of the Trusted SRAM.
+ */
+#define BL1_RW_BASE		(MARVELL_BL_RAM_BASE +		\
+					MARVELL_BL_RAM_SIZE -	\
+					PLAT_MARVELL_MAX_BL1_RW_SIZE)
+#define BL1_RW_LIMIT		(MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
+
+/*******************************************************************************
+ * BLE specific defines.
+ ******************************************************************************/
+#define BLE_BASE			PLAT_MARVELL_SRAM_BASE
+#define BLE_LIMIT			PLAT_MARVELL_SRAM_END
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL2 just below BL31.
+ */
+#define BL2_BASE			(BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
+#define BL2_LIMIT			BL31_BASE
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL31 at the top of the Trusted SRAM.
+ */
+#define BL31_BASE			(MARVELL_BL_RAM_BASE +		\
+						MARVELL_BL_RAM_SIZE -	\
+						PLAT_MARVEL_MAX_BL31_SIZE)
+#define BL31_PROGBITS_LIMIT		BL1_RW_BASE
+#define BL31_LIMIT			(MARVELL_BL_RAM_BASE +	\
+					 MARVELL_BL_RAM_SIZE)
+
+
+#endif /* __MARVELL_DEF_H__ */
diff --git a/include/plat/marvell/a8k/common/plat_config.h b/include/plat/marvell/a8k/common/plat_config.h
new file mode 100644
index 00000000..4582d1cf
--- /dev/null
+++ b/include/plat/marvell/a8k/common/plat_config.h
@@ -0,0 +1,107 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+#ifndef __BOARD_CONFIG_H__
+#define __BOARD_CONFIG_H__
+
+#include <amb_adec.h>
+#include <rfu.h>
+#include <iob.h>
+#include <ccu.h>
+#include <pci_ep.h>
+
+/*
+ * This struct supports skip image request
+ * detection_method: the method used to detect the request "signal".
+ * info:
+ *	GPIO:
+ *		detection_method: HIGH (pressed button), LOW (unpressed button),
+ *		num (button mpp number).
+ *	i2c:
+ *		i2c_addr: the address of the i2c chosen.
+ *		i2d_reg: the i2c register chosen.
+ *	test:
+ *		choose the DIE you picked the button in (AP or CP).
+ *		in case of CP(cp_index = 0 if CP0, cp_index = 1 if CP1)
+ */
+struct skip_image {
+	enum {
+		GPIO,
+		I2C,
+		USER_DEFINED
+	} detection_method;
+
+	struct {
+		struct {
+			int num;
+			enum {
+				HIGH,
+				LOW
+			} button_state;
+
+		} gpio;
+
+		struct {
+			int i2c_addr;
+			int i2c_reg;
+		} i2c;
+
+		struct {
+			enum {
+				CP,
+				AP
+			} cp_ap;
+			int cp_index;
+		} test;
+	} info;
+};
+
+uintptr_t marvell_get_amb_reg_offs(int cp_index);
+uintptr_t marvell_get_rfu_reg_offs(void);
+uintptr_t marvell_get_iob_reg_offs(int cp_index);
+int marvell_get_iob_max_win(void);
+uintptr_t marvell_get_ccu_reg_offs(void);
+int marvell_get_ccu_max_win(void);
+
+
+/*
+ * The functions below are defined as Weak and may be overridden
+ * in specific Marvell standard platform
+ */
+int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size);
+int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size);
+int marvell_get_iob_memory_map(struct iob_win **win,
+			       uint32_t *size, int cp_index);
+int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size);
+
+#endif /* __BOARD_CONFIG_H__ */
diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h
new file mode 100644
index 00000000..cd3c9e41
--- /dev/null
+++ b/include/plat/marvell/a8k/common/plat_marvell.h
@@ -0,0 +1,136 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+#ifndef __PLAT_MARVELL_H__
+#define __PLAT_MARVELL_H__
+
+#include <cassert.h>
+#include <cpu_data.h>
+#include <stdint.h>
+#include <utils.h>
+#include <xlat_tables.h>
+
+/*
+ * Extern declarations common to Marvell standard platforms
+ */
+extern const mmap_region_t plat_marvell_mmap[];
+
+#define MARVELL_CASSERT_MMAP						\
+	CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS)	\
+		<= MAX_MMAP_REGIONS,					\
+		assert_max_mmap_regions)
+
+/*
+ * Utility functions common to Marvell standard platforms
+ */
+void marvell_setup_page_tables(uintptr_t total_base,
+			       size_t total_size,
+			       uintptr_t code_start,
+			       uintptr_t code_limit,
+			       uintptr_t rodata_start,
+			       uintptr_t rodata_limit
+#if USE_COHERENT_MEM
+			     , uintptr_t coh_start,
+			       uintptr_t coh_limit
+#endif
+);
+
+/* IO storage utility functions */
+void marvell_io_setup(void);
+
+/* Systimer utility function */
+void marvell_configure_sys_timer(void);
+
+/* Topology utility function */
+int marvell_check_mpidr(u_register_t mpidr);
+
+/* BLE utility functions */
+int ble_plat_setup(int *skip);
+void *plat_get_dram_data(void);
+void ble_plat_pcie_ep_setup(void);
+struct pci_hw_cfg *plat_get_pcie_hw_data(void);
+
+/* BL1 utility functions */
+void marvell_bl1_early_platform_setup(void);
+void marvell_bl1_platform_setup(void);
+void marvell_bl1_plat_arch_setup(void);
+
+/* BL2 utility functions */
+void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
+void marvell_bl2_platform_setup(void);
+void marvell_bl2_plat_arch_setup(void);
+uint32_t marvell_get_spsr_for_bl32_entry(void);
+uint32_t marvell_get_spsr_for_bl33_entry(void);
+
+/* BL31 utility functions */
+void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2,
+				void *plat_params_from_bl2);
+void marvell_bl31_platform_setup(void);
+void marvell_bl31_plat_runtime_setup(void);
+void marvell_bl31_plat_arch_setup(void);
+
+/* Bootrom image recovery utility functions */
+void *plat_get_skip_image_data(void);
+
+/* FIP TOC validity check */
+int marvell_io_is_toc_valid(void);
+
+/*
+ * Mandatory functions required in Marvell standard platforms
+ */
+void plat_marvell_gic_driver_init(void);
+void plat_marvell_gic_init(void);
+
+/*
+ * PSCI functionality
+ */
+void psci_arch_init(void);
+void plat_marvell_system_reset(void);
+
+/*
+ * Optional functions required in Marvell standard platforms
+ */
+void plat_marvell_io_setup(void);
+int plat_marvell_get_alt_image_source(
+	unsigned int image_id,
+	uintptr_t *dev_handle,
+	uintptr_t *image_spec);
+unsigned int plat_marvell_calc_core_pos(u_register_t mpidr);
+
+#if PALLADIUM
+void marvell_bl1_setup_mpps(void);
+#endif
+
+const mmap_region_t *plat_marvell_get_mmap(void);
+
+#endif /* __PLAT_MARVELL_H__ */
diff --git a/include/plat/marvell/a8k/common/plat_pm_trace.h b/include/plat/marvell/a8k/common/plat_pm_trace.h
new file mode 100644
index 00000000..3c69b95c
--- /dev/null
+++ b/include/plat/marvell/a8k/common/plat_pm_trace.h
@@ -0,0 +1,125 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __PLAT_PM_TRACE_H
+#define __PLAT_PM_TRACE_H
+
+
+/*
+ * PM Trace is for Debug purpose only!!!
+ * It should not be enabled during System Run time
+ */
+#undef PM_TRACE_ENABLE
+
+
+/* trace entry time */
+struct pm_trace_entry {
+	/* trace entry time stamp */
+	unsigned int timestamp;
+
+	/* trace info
+	 * [16-31] - API Trace Id
+	 * [00-15] - API Step Id
+	 */
+	unsigned int trace_info;
+};
+
+struct pm_trace_ctrl {
+	/* trace pointer - points to next free entry in trace cyclic queue */
+	unsigned int trace_pointer;
+
+	/* trace count - number of entries in the queue, clear upon read */
+	unsigned int trace_count;
+};
+
+/* trace size definition */
+#define AP_MSS_ATF_CORE_INFO_SIZE		(256)
+#define AP_MSS_ATF_CORE_ENTRY_SIZE		(8)
+#define AP_MSS_ATF_TRACE_SIZE_MASK		(0xFF)
+
+/* trace address definition */
+#define AP_MSS_TIMER_BASE		(MVEBU_REGS_BASE_MASK + 0x580110)
+
+#define AP_MSS_ATF_CORE_0_CTRL_BASE	(MVEBU_REGS_BASE_MASK + 0x522050)
+#define AP_MSS_ATF_CORE_1_CTRL_BASE	(MVEBU_REGS_BASE_MASK + 0x522060)
+#define AP_MSS_ATF_CORE_2_CTRL_BASE	(MVEBU_REGS_BASE_MASK + 0x522070)
+#define AP_MSS_ATF_CORE_3_CTRL_BASE	(MVEBU_REGS_BASE_MASK + 0x522080)
+#define AP_MSS_ATF_CORE_CTRL_BASE	(AP_MSS_ATF_CORE_0_CTRL_BASE)
+
+#define AP_MSS_ATF_CORE_0_INFO_BASE	(MVEBU_REGS_BASE_MASK + 0x5220D0)
+#define AP_MSS_ATF_CORE_0_INFO_TRACE	(MVEBU_REGS_BASE_MASK + 0x5220D4)
+#define AP_MSS_ATF_CORE_1_INFO_BASE	(MVEBU_REGS_BASE_MASK + 0x5228D0)
+#define AP_MSS_ATF_CORE_1_INFO_TRACE	(MVEBU_REGS_BASE_MASK + 0x5228D4)
+#define AP_MSS_ATF_CORE_2_INFO_BASE	(MVEBU_REGS_BASE_MASK + 0x5230D0)
+#define AP_MSS_ATF_CORE_2_INFO_TRACE	(MVEBU_REGS_BASE_MASK + 0x5230D4)
+#define AP_MSS_ATF_CORE_3_INFO_BASE	(MVEBU_REGS_BASE_MASK + 0x5238D0)
+#define AP_MSS_ATF_CORE_3_INFO_TRACE	(MVEBU_REGS_BASE_MASK + 0x5238D4)
+#define AP_MSS_ATF_CORE_INFO_BASE	(AP_MSS_ATF_CORE_0_INFO_BASE)
+
+/* trace info definition */
+#define TRACE_PWR_DOMAIN_OFF			(0x10000)
+#define TRACE_PWR_DOMAIN_SUSPEND		(0x20000)
+#define TRACE_PWR_DOMAIN_SUSPEND_FINISH		(0x30000)
+#define TRACE_PWR_DOMAIN_ON			(0x40000)
+#define TRACE_PWR_DOMAIN_ON_FINISH		(0x50000)
+
+#define TRACE_PWR_DOMAIN_ON_MASK		(0xFF)
+
+#if defined(SCP_IMAGE) && defined(PM_TRACE_ENABLE)
+
+/* trace API definition */
+void pm_core_0_trace(unsigned int trace);
+void pm_core_1_trace(unsigned int trace);
+void pm_core_2_trace(unsigned int trace);
+void pm_core_3_trace(unsigned int trace);
+
+typedef void (*core_trace_func)(unsigned int);
+
+extern core_trace_func funcTbl[PLATFORM_CORE_COUNT];
+
+#else
+
+#define PM_TRACE(trace, core)
+
+#endif
+
+/*******************************************************************************
+ * pm_trace_add
+ *
+ * DESCRIPTION: Add PM trace
+ ******************************************************************************
+ */
+void pm_trace_add(unsigned int trace, unsigned int core);
+
+#endif /* __PLAT_PM_TRACE_H */
diff --git a/plat/marvell/a8k/a7040_pcac/board/dram_port.c b/plat/marvell/a8k/a7040_pcac/board/dram_port.c
new file mode 100644
index 00000000..f6b804fa
--- /dev/null
+++ b/plat/marvell/a8k/a7040_pcac/board/dram_port.c
@@ -0,0 +1,106 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <arch_helpers.h>
+#include <plat_marvell.h>
+#include <debug.h>
+#include <dram_if.h>
+
+#include <mv_ddr_atf_wrapper.h>
+#include <apn806/mv_ddr_apn806.h>
+#include <apn806/mv_ddr_apn806_topology.h>
+#include <ddr3_topology_def.h>
+
+struct dram_config dram_cfg;
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information recieved from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+int update_dram_info(struct dram_config *cfg)
+{
+	NOTICE("Gathering DRAM information\n");
+	return 0;
+}
+
+void *plat_get_dram_data(void)
+{
+	/* Update DRAM for dynamic platforms */
+	update_dram_info(&dram_cfg);
+
+	return &dram_cfg;
+}
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+/* FIXME: MISL board 2CS 4Gb x8 devices of micron - 2133P */
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+	{ { { {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0} },
+	   SPEED_BIN_DDR_2400R,		/* speed_bin */
+	   MV_DDR_DEV_WIDTH_16BIT,	/* sdram device width */
+	   MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
+	   DDR_FREQ_SAR,		/* frequency */
+	   0, 0,			/* cas_l, cas_wl */
+	   MV_DDR_TEMP_LOW} },		/* temperature */
+	BUS_MASK_32BIT,			/* subphys mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+struct dram_config *mv_ddr_dram_config_get(void)
+{
+	/* Return dram configuration as defined in the board code */
+	return &dram_cfg;
+}
diff --git a/plat/marvell/a8k/a7040_pcac/board/marvell_plat_config.c b/plat/marvell/a8k/a7040_pcac/board/marvell_plat_config.c
new file mode 100644
index 00000000..a32dc398
--- /dev/null
+++ b/plat/marvell/a8k/a7040_pcac/board/marvell_plat_config.c
@@ -0,0 +1,193 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_config.h>
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+#include <plat_def.h>
+
+/*******************************************************************************
+ * AMB Configuration
+ ******************************************************************************/
+struct amb_win *amb_memory_map;
+
+uintptr_t marvell_get_amb_reg_offs(int cp_index)
+{
+	return MVEBU_AMB_ADEC_BASE(cp_index);
+}
+
+int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size)
+{
+	*win = amb_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(amb_memory_map)/sizeof(struct amb_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * RFU Configuration
+ ******************************************************************************/
+
+struct rfu_win rfu_memory_map[] = {
+	/* MCI 0 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(0),	0x0,	0x100000,   MCI_0_TID},
+	/* MCI 1 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(1),	0x0,	0x100000,   MCI_1_TID},
+};
+
+
+uintptr_t marvell_get_rfu_reg_offs(void)
+{
+	return MVEBU_RFU_BASE;
+}
+
+int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size)
+{
+	*win = rfu_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(rfu_memory_map)/sizeof(struct rfu_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * IOB Configuration
+ ******************************************************************************/
+#define MARVELL_IOB_MAX_WIN	16
+
+struct iob_win iob_memory_map[] = {
+	/* PEX1_X1 window */
+	{0x0,	0xf7000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xf8000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x80,	0x00000000,	0x80,	0x0000000,	PEX0_TID},
+};
+
+uintptr_t marvell_get_iob_reg_offs(int cp_index)
+{
+	return MVEBU_IOB_BASE(cp_index);
+}
+
+int marvell_get_iob_max_win(void)
+{
+	return MARVELL_IOB_MAX_WIN;
+}
+
+int marvell_get_iob_memory_map(struct iob_win **win,
+			       uint32_t *size, int cp_index)
+{
+	*win = iob_memory_map;
+	*size = sizeof(iob_memory_map)/sizeof(struct iob_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * CCU Configuration
+ ******************************************************************************/
+#define MARVELL_CCU_MAX_WIN	8
+
+struct ccu_win ccu_memory_map[] = {
+	{0x0,	0xf2000000,	0x0,	0xe000000,   IO_0_TID}, /* IO window */
+	{0x80,	0x00000000,	0x80,	0x0000000,   IO_0_TID}, /* IO window */
+};
+
+uintptr_t marvell_get_ccu_reg_offs(void)
+{
+	return MVEBU_CCU_BASE;
+}
+
+int marvell_get_ccu_max_win(void)
+{
+	return MARVELL_CCU_MAX_WIN;
+}
+
+int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = sizeof(ccu_memory_map)/sizeof(struct ccu_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * PCIe Configuration
+ ******************************************************************************/
+struct pci_hw_cfg a70x0_pci_hw_cfg = {
+	.delay_cfg	= 1,
+	.master_en	= 1,
+	.lane_width	= 4,
+	.lane_ids	= {0, 1, 2, 3},
+	.clk_src	= 0,
+	.clk_out	= 0,	/* clk is not output */
+	.is_end_point	= 0,
+	.mac_base	= MVEBU_PCIE_X4_MAC_BASE(0),
+	.comphy_base	= MVEBU_COMPHY_BASE(0),
+	.hpipe_base	= MVEBU_HPIPE_BASE(0),
+	.dfx_base	= MVEBU_CP_DFX_BASE(0),
+};
+
+struct pci_hw_cfg *plat_get_pcie_hw_data(void)
+{
+	return &a70x0_pci_hw_cfg;
+}
+/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
+#else
+/*******************************************************************************
+ * SKIP IMAGE Configuration
+ ******************************************************************************/
+
+struct skip_image skip_im = {
+	.detection_method = GPIO,
+	.info.gpio.num = 33,
+	.info.gpio.button_state = HIGH,
+	.info.test.cp_ap = CP,
+	.info.test.cp_index = 0,
+};
+
+void *plat_get_skip_image_data(void)
+{
+	/* Return the skip_image configurations */
+	return &skip_im;
+}
+#endif
diff --git a/plat/marvell/a8k/a7040_pcac/plat_def.h b/plat/marvell/a8k/a7040_pcac/plat_def.h
new file mode 100644
index 00000000..6d6a53ec
--- /dev/null
+++ b/plat/marvell/a8k/a7040_pcac/plat_def.h
@@ -0,0 +1,58 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MVEBU_DEF_H__
+#define __MVEBU_DEF_H__
+
+#include <a8k_plat_def.h>
+
+#define CP_COUNT		1	/* A70x0 has single CP0 */
+
+/*************************************************************************
+ * Required platform porting definitions common to all
+ * Mangement Compute SubSystems (MSS)
+ ************************************************************************/
+
+/*
+ * Load address of SCP_BL2
+ * SCP_BL2 is loaded to the same place as BL31.
+ * Once SCP_BL2 is transferred to the SCP,
+ * it is discarded and BL31 is loaded over the top.
+ */
+#ifdef SCP_IMAGE
+#define SCP_BL2_BASE                    BL31_BASE
+#endif
+
+
+#endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/a8k/a7040_pcac/platform.mk b/plat/marvell/a8k/a7040_pcac/platform.mk
new file mode 100644
index 00000000..5789a24b
--- /dev/null
+++ b/plat/marvell/a8k/a7040_pcac/platform.mk
@@ -0,0 +1,36 @@
+#
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+include plat/marvell/a8k/common/a8k_common.mk
+
+include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a70x0/board/dram_port.c b/plat/marvell/a8k/a70x0/board/dram_port.c
new file mode 100644
index 00000000..ae8ae7ec
--- /dev/null
+++ b/plat/marvell/a8k/a70x0/board/dram_port.c
@@ -0,0 +1,106 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <arch_helpers.h>
+#include <plat_marvell.h>
+#include <debug.h>
+#include <dram_if.h>
+
+#include <mv_ddr_atf_wrapper.h>
+#include <apn806/mv_ddr_apn806.h>
+#include <apn806/mv_ddr_apn806_topology.h>
+#include <ddr3_topology_def.h>
+
+struct dram_config dram_cfg;
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information recieved from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+int update_dram_info(struct dram_config *cfg)
+{
+	NOTICE("Gathering DRAM information\n");
+	return 0;
+}
+
+void *plat_get_dram_data(void)
+{
+	/* Update DRAM for dynamic platforms */
+	update_dram_info(&dram_cfg);
+
+	return &dram_cfg;
+}
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+/* FIXME: MISL board 2CS 4Gb x8 devices of micron - 2133P */
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+	{ { { {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0},
+	      {0x3, 0x2, 0, 0} },
+	   SPEED_BIN_DDR_2133P,		/* speed_bin */
+	   MV_DDR_DEV_WIDTH_8BIT,	/* sdram device width */
+	   MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
+	   DDR_FREQ_SAR,		/* frequency */
+	   0, 0,			/* cas_l, cas_wl */
+	   MV_DDR_TEMP_LOW} },		/* temperature */
+	MV_DDR_32BIT_ECC_PUP8_BUS_MASK,	/* subphys mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+struct dram_config *mv_ddr_dram_config_get(void)
+{
+	/* Return dram configuration as defined in the board code */
+	return &dram_cfg;
+}
diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c
new file mode 100644
index 00000000..1d6c1a01
--- /dev/null
+++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c
@@ -0,0 +1,170 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_config.h>
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+#include <plat_def.h>
+
+/*******************************************************************************
+ * AMB Configuration
+ ******************************************************************************/
+struct amb_win *amb_memory_map;
+
+uintptr_t marvell_get_amb_reg_offs(int cp_index)
+{
+	return MVEBU_AMB_ADEC_BASE(cp_index);
+}
+
+int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size)
+{
+	*win = amb_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(amb_memory_map)/sizeof(struct amb_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * RFU Configuration
+ ******************************************************************************/
+
+struct rfu_win rfu_memory_map[] = {
+	/* MCI 0 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(0),	0x0,	0x100000, MCI_0_TID},
+	/* MCI 1 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(1),	0x0,	0x100000, MCI_1_TID},
+};
+
+
+uintptr_t marvell_get_rfu_reg_offs(void)
+{
+	return MVEBU_RFU_BASE;
+}
+
+int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size)
+{
+	*win = rfu_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(rfu_memory_map)/sizeof(struct rfu_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * IOB Configuration
+ ******************************************************************************/
+#define MARVELL_IOB_MAX_WIN	16
+
+struct iob_win iob_memory_map[] = {
+	/* PEX1_X1 window */
+	{0x0,	0xf7000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xf8000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x0,	0xf6000000,	0x0,	0x1000000,	PEX0_TID},
+};
+
+uintptr_t marvell_get_iob_reg_offs(int cp_index)
+{
+	return MVEBU_IOB_BASE(cp_index);
+}
+
+int marvell_get_iob_max_win(void)
+{
+	return MARVELL_IOB_MAX_WIN;
+}
+
+int marvell_get_iob_memory_map(struct iob_win **win,
+			       uint32_t *size, int cp_index)
+{
+	*win = iob_memory_map;
+	*size = sizeof(iob_memory_map)/sizeof(struct iob_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * CCU Configuration
+ ******************************************************************************/
+#define MARVELL_CCU_MAX_WIN	8
+
+struct ccu_win ccu_memory_map[] = {	/* IO window */
+	{0x0,	0xf2000000,	0x0,	0xe000000,	IO_0_TID},
+};
+
+uintptr_t marvell_get_ccu_reg_offs(void)
+{
+	return MVEBU_CCU_BASE;
+}
+
+int marvell_get_ccu_max_win(void)
+{
+	return MARVELL_CCU_MAX_WIN;
+}
+
+int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = sizeof(ccu_memory_map)/sizeof(struct ccu_win);
+
+	return 0;
+}
+/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
+#else
+/*******************************************************************************
+ * SKIP IMAGE Configuration
+ ******************************************************************************/
+
+struct skip_image skip_im = {
+	.detection_method = GPIO,
+	.info.gpio.num = 33,
+	.info.gpio.button_state = HIGH,
+	.info.test.cp_ap = CP,
+	.info.test.cp_index = 0,
+};
+
+void *plat_get_skip_image_data(void)
+{
+	/* Return the skip_image configurations */
+	return &skip_im;
+}
+#endif
diff --git a/plat/marvell/a8k/a70x0/plat_def.h b/plat/marvell/a8k/a70x0/plat_def.h
new file mode 100644
index 00000000..f954ce93
--- /dev/null
+++ b/plat/marvell/a8k/a70x0/plat_def.h
@@ -0,0 +1,42 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MVEBU_DEF_H__
+#define __MVEBU_DEF_H__
+
+#include <a8k_plat_def.h>
+
+#define CP_COUNT		1	/* A70x0 has single CP0 */
+
+#endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/a8k/a70x0/platform.mk b/plat/marvell/a8k/a70x0/platform.mk
new file mode 100644
index 00000000..5789a24b
--- /dev/null
+++ b/plat/marvell/a8k/a70x0/platform.mk
@@ -0,0 +1,36 @@
+#
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+include plat/marvell/a8k/common/a8k_common.mk
+
+include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a70x0_cust/board/dram_port.c b/plat/marvell/a8k/a70x0_cust/board/dram_port.c
new file mode 100644
index 00000000..e235d9a5
--- /dev/null
+++ b/plat/marvell/a8k/a70x0_cust/board/dram_port.c
@@ -0,0 +1,138 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <arch_helpers.h>
+#include <plat_marvell.h>
+#include <debug.h>
+#include <dram_if.h>
+#include <plat_def.h>
+#include <mmio.h>
+#include <a8k_i2c.h>
+
+#include <mv_ddr_atf_wrapper.h>
+#include <apn806/mv_ddr_apn806.h>
+#include <apn806/mv_ddr_apn806_topology.h>
+#include <ddr3_topology_def.h>
+
+struct dram_config dram_cfg;
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+/* FIXME: Customer board with 2CS 4Gb x8 devices of Micron 2133P */
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+	{ { { {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0} },
+	   SPEED_BIN_DDR_2133P,		/* speed_bin */
+	   MV_DDR_DEV_WIDTH_8BIT,	/* sdram device width */
+	   MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
+	   DDR_FREQ_SAR,		/* frequency */
+	   0, 0,			/* cas_l, cas_wl */
+	   MV_DDR_TEMP_LOW} },		/* temperature */
+	MV_DDR_32BIT_ECC_PUP8_BUS_MASK,	/* subphys mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+struct dram_config *mv_ddr_dram_config_get(void)
+{
+	/* Return dram configuration as defined in the board code */
+	return &dram_cfg;
+}
+
+static void mpp_config(void)
+{
+	uint32_t val;
+
+	/* Enable CP0 I2C MPPs (MPP: 37-38) */
+	val = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4));
+	mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), val | 0x2200000);
+}
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information recieved from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+int update_dram_info(struct dram_config *cfg)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	NOTICE("Gathering DRAM information\n");
+
+	if (tm->cfg_src == MV_DDR_CFG_SPD) {
+		/* configure mpps for i2c functionality */
+		mpp_config();
+		/* initialize ap i2c */
+		i2c_init((void *)MVEBU_CP0_I2C_BASE);
+		/*
+		 * Dummy read to the SPD chip memory page selector.
+		 * It is needed for for selecting the SPD memory page 0
+		 * prior to accessing the DRAM configuration data
+		 */
+		i2c_read(CP0_I2C_SPD_P0_ADDR, 0x0, 2,
+			 tm->spd_data.all_bytes, 1);
+		/* read data from spd */
+		i2c_read(CP0_I2C_SPD_ADDR, 0x0, 2, tm->spd_data.all_bytes,
+			 sizeof(tm->spd_data.all_bytes));
+	}
+
+	return 0;
+}
+
+void *plat_get_dram_data(void)
+{
+	/* Update DRAM for dynamic platforms */
+	update_dram_info(&dram_cfg);
+
+	return &dram_cfg;
+}
diff --git a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c
new file mode 100644
index 00000000..86d6e334
--- /dev/null
+++ b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c
@@ -0,0 +1,171 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_config.h>
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+#include <plat_def.h>
+
+/*******************************************************************************
+ * AMB Configuration
+ ******************************************************************************/
+struct amb_win amb_memory_map[] = {
+	{0xf900,	0x1000000,	AMB_DEV_CS0_ID}, /* Device Bus window */
+};
+
+uintptr_t marvell_get_amb_reg_offs(int cp_index)
+{
+	return MVEBU_AMB_ADEC_BASE(cp_index);
+}
+
+int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size)
+{
+	*win = amb_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(amb_memory_map)/sizeof(struct amb_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * RFU Configuration
+ ******************************************************************************/
+
+struct rfu_win rfu_memory_map[] = {
+	/* MCI 0 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(0),	0x0,	0x100000, MCI_0_TID},
+	/* MCI 1 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(1),	0x0,	0x100000, MCI_1_TID},
+};
+
+uintptr_t marvell_get_rfu_reg_offs(void)
+{
+	return MVEBU_RFU_BASE;
+}
+
+int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size)
+{
+	*win = rfu_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(rfu_memory_map)/sizeof(struct rfu_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * IOB Configuration
+ ******************************************************************************/
+#define MARVELL_IOB_MAX_WIN	16
+
+struct iob_win iob_memory_map[] = {
+	/* PEX1_X1 window */
+	{0x0,	0xf7000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xf8000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x0,	0xf6000000,	0x0,	0x1000000,	PEX0_TID},
+};
+
+uintptr_t marvell_get_iob_reg_offs(int cp_index)
+{
+	return MVEBU_IOB_BASE(cp_index);
+}
+
+int marvell_get_iob_max_win(void)
+{
+	return MARVELL_IOB_MAX_WIN;
+}
+
+int marvell_get_iob_memory_map(struct iob_win **win,
+			       uint32_t *size, int cp_index)
+{
+	*win = iob_memory_map;
+	*size = sizeof(iob_memory_map)/sizeof(struct iob_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * CCU Configuration
+ ******************************************************************************/
+#define MARVELL_CCU_MAX_WIN	8
+
+struct ccu_win ccu_memory_map[] = {
+	{0x0,	0xf2000000,	0x0,	0xe000000,  IO_0_TID}, /* IO window */
+};
+
+uintptr_t marvell_get_ccu_reg_offs(void)
+{
+	return MVEBU_CCU_BASE;
+}
+
+int marvell_get_ccu_max_win(void)
+{
+	return MARVELL_CCU_MAX_WIN;
+}
+
+int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = sizeof(ccu_memory_map)/sizeof(struct ccu_win);
+
+	return 0;
+}
+/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
+#else
+/*******************************************************************************
+ * SKIP IMAGE Configuration
+ ******************************************************************************/
+
+struct skip_image skip_im = {
+	.detection_method = GPIO,
+	.info.gpio.num = 33,
+	.info.gpio.button_state = HIGH,
+	.info.test.cp_ap = CP,
+	.info.test.cp_index = 0,
+};
+
+void *plat_get_skip_image_data(void)
+{
+	/* Return the skip_image configurations */
+	return &skip_im;
+}
+#endif
diff --git a/plat/marvell/a8k/a70x0_cust/plat_def.h b/plat/marvell/a8k/a70x0_cust/plat_def.h
new file mode 100644
index 00000000..5274b1a5
--- /dev/null
+++ b/plat/marvell/a8k/a70x0_cust/plat_def.h
@@ -0,0 +1,44 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MVEBU_DEF_H__
+#define __MVEBU_DEF_H__
+
+#include <a8k_plat_def.h>
+
+#define CP_COUNT		1	/* A70x0 has single CP0 */
+#define CP0_I2C_SPD_ADDR	0x55	/* Access SPD data */
+#define CP0_I2C_SPD_P0_ADDR	0x36	/* Select SPD data page 0 */
+
+#endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/a8k/a70x0_cust/platform.mk b/plat/marvell/a8k/a70x0_cust/platform.mk
new file mode 100644
index 00000000..42fe2ce6
--- /dev/null
+++ b/plat/marvell/a8k/a70x0_cust/platform.mk
@@ -0,0 +1,35 @@
+#
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include plat/marvell/a8k/common/a8k_common.mk
+
+include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c
new file mode 100644
index 00000000..acbaec0a
--- /dev/null
+++ b/plat/marvell/a8k/a80x0/board/dram_port.c
@@ -0,0 +1,190 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <arch_helpers.h>
+#include <plat_marvell.h>
+#include <debug.h>
+#include <dram_if.h>
+#include <plat_def.h>
+#include <mmio.h>
+#include <a8k_i2c.h>
+
+#include <mv_ddr_atf_wrapper.h>
+#include <apn806/mv_ddr_apn806.h>
+#include <apn806/mv_ddr_apn806_topology.h>
+#include <ddr3_topology_def.h>
+
+#define MVEBU_AP_MPP_CTRL0_7_REG		MVEBU_AP_MPP_REGS(0)
+#define MVEBU_AP_MPP_CTRL4_OFFS			16
+#define MVEBU_AP_MPP_CTRL5_OFFS			20
+#define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA		0x3
+#define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA		0x3
+
+#define MVEBU_CP_MPP_CTRL37_OFFS		20
+#define MVEBU_CP_MPP_CTRL38_OFFS		24
+#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA	0x2
+#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA	0x2
+
+#define MVEBU_MPP_CTRL_MASK			0xf
+
+struct dram_config dram_cfg;
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	/* MISL board with 1CS 8Gb x4 devices of Micron 2400T */
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+	{ { { {0x1, 0x0, 0, 0},	/* FIXME: change the cs mask for all 64 bit */
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0} },
+	   /* TODO: double check if the speed bin is 2400S */
+	   SPEED_BIN_DDR_2400S,		/* speed_bin */
+	   MV_DDR_DEV_WIDTH_8BIT,	/* sdram device width */
+	   MV_DDR_DIE_CAP_8GBIT,	/* die capacity */
+	   DDR_FREQ_SAR,		/* frequency */
+	   0, 0,			/* cas_l, cas_wl */
+	   MV_DDR_TEMP_LOW} },		/* temperature */
+	MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
+	MV_DDR_CFG_SPD,			/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+struct dram_config *mv_ddr_dram_config_get(void)
+{
+	/* Return dram configuration as defined in the board code */
+	return &dram_cfg;
+}
+
+static void mpp_config(void)
+{
+	uintptr_t reg;
+	uint32_t val;
+
+	/*
+	 * The DRAM SPD on A0 and A1 boards is located on different i2c channels
+	 * The A80x0 A0 DB boards are using the AP i2c channel (MPP4 and MPP5),
+	 * while A80x0 A1 DB boards - the CP0 i2c one (MPP37, MPP38).
+	 */
+	if (apn806_rev_id_get() == APN806_REV_ID_A0) {
+		/* configure ap mmps 4, 5 to i2c */
+		reg = MVEBU_AP_MPP_CTRL0_7_REG;
+		val = mmio_read_32(reg);
+
+		val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_AP_MPP_CTRL4_OFFS) |
+			(MVEBU_MPP_CTRL_MASK << MVEBU_AP_MPP_CTRL5_OFFS));
+		val |= ((MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA <<
+				MVEBU_AP_MPP_CTRL4_OFFS) |
+			(MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA <<
+				MVEBU_AP_MPP_CTRL5_OFFS));
+		mmio_write_32(reg, val);
+		val = mmio_read_32(reg);
+	} else {
+		reg = MVEBU_CP_MPP_REGS(0, 4);
+		/* configure CP0 MPP 37 and 38 to i2c */
+		val = mmio_read_32(reg);
+		val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
+			(MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
+		val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
+				MVEBU_CP_MPP_CTRL37_OFFS) |
+			(MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
+				MVEBU_CP_MPP_CTRL38_OFFS);
+		mmio_write_32(reg, val);
+	}
+}
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information recieved from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+int update_dram_info(struct dram_config *cfg)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	NOTICE("Gathering DRAM information\n");
+
+	if (tm->cfg_src == MV_DDR_CFG_SPD) {
+		/* configure MPPs to enable i2c */
+		mpp_config();
+		/*
+		 * The DRAM SPD on A0 and A1 boards is located on different i2c
+		 * channels
+		 * The A80x0 A0 DB boards are using the AP i2c channel,
+		 * while A80x0 A1 DB boards - the CP0 i2c one.
+		 * In both cases the SPD device address on i2c bus is the same.
+		 */
+		if (apn806_rev_id_get() == APN806_REV_ID_A0)
+			/* initialize ap i2c */
+			i2c_init((void *)MVEBU_AP_I2C_BASE);
+		else
+			 /* initialize ap i2c */
+			i2c_init((void *)MVEBU_CP0_I2C_BASE);
+		/*
+		 * Dummy read to the SPD chip memory page selector.
+		 * It is needed for for selecting the SPD memory page 0
+		 * prior to accessing the DRAM configuration data
+		 */
+		i2c_read(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+		/* read data from spd */
+		i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
+			 sizeof(tm->spd_data.all_bytes));
+	}
+
+	return 0;
+}
+
+void *plat_get_dram_data(void)
+{
+	/* Update DRAM for dynamic platforms */
+	update_dram_info(&dram_cfg);
+
+	return &dram_cfg;
+}
diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
new file mode 100644
index 00000000..ee27a050
--- /dev/null
+++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
@@ -0,0 +1,198 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_config.h>
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+#include <plat_def.h>
+
+/*******************************************************************************
+ * AMB Configuration
+ ******************************************************************************/
+struct amb_win *amb_memory_map;
+
+uintptr_t marvell_get_amb_reg_offs(int cp_index)
+{
+	return MVEBU_AMB_ADEC_BASE(cp_index);
+}
+
+int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size)
+{
+	*win = amb_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(amb_memory_map)/sizeof(struct amb_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * RFU Configuration
+ ******************************************************************************/
+
+struct rfu_win rfu_memory_map[] = {
+	/* CP1 (MCI0) internal regs */
+	{0x0,	0xf4000000,			0x0,	0x2000000,  MCI_0_TID},
+	/* PCIe0 on CP1*/
+	{0x0,	0xfa000000,			0x0,	0x1000000,  MCI_0_TID},
+	/* PCIe1 on CP1*/
+	{0x0,	0xfb000000,			0x0,	0x1000000,  MCI_0_TID},
+	/* PCIe2 on CP1*/
+	{0x0,	0xfc000000,			0x0,	0x1000000,  MCI_0_TID},
+	/* MCI 0 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(0),	0x0,	0x100000,  MCI_0_TID},
+	/* MCI 1 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(1),	0x0,	0x100000,  MCI_1_TID},
+};
+
+uintptr_t marvell_get_rfu_reg_offs(void)
+{
+	return MVEBU_RFU_BASE;
+}
+
+int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size)
+{
+	*win = rfu_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(rfu_memory_map)/sizeof(struct rfu_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * IOB Configuration
+ ******************************************************************************/
+#define MARVELL_IOB_MAX_WIN		16
+
+struct iob_win iob_memory_map_cp0[] = {
+	/* CP0 */
+	/* PEX1_X1 window */
+	{0x0,	0xf7000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xf8000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x0,	0xf6000000,	0x0,	0x1000000,	PEX0_TID}
+};
+
+struct iob_win iob_memory_map_cp1[] = {
+	/* CP1 */
+	/* PEX1_X1 window */
+	{0x0,	0xfb000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xfc000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x0,	0xfa000000,	0x0,	0x1000000,	PEX0_TID}
+};
+
+uintptr_t marvell_get_iob_reg_offs(int cp_index)
+{
+	return MVEBU_IOB_BASE(cp_index);
+}
+
+int marvell_get_iob_max_win(void)
+{
+	return MARVELL_IOB_MAX_WIN;
+}
+
+int marvell_get_iob_memory_map(struct iob_win **win,
+			       uint32_t *size, int cp_index)
+{
+	switch (cp_index) {
+	case 0:
+		*win = iob_memory_map_cp0;
+		*size = sizeof(iob_memory_map_cp0)/sizeof(struct iob_win);
+		return 0;
+	case 1:
+		*win = iob_memory_map_cp1;
+		*size = sizeof(iob_memory_map_cp1)/sizeof(struct iob_win);
+		return 0;
+	default:
+		*size = 0;
+		*win = 0;
+		return 1;
+	}
+}
+
+/*******************************************************************************
+ * CCU Configuration
+ ******************************************************************************/
+#define MARVELL_CCU_MAX_WIN	8
+
+struct ccu_win ccu_memory_map[] = {
+	{0x0,	0xf2000000,	0x0,	0xe000000,  IO_0_TID}, /* IO window */
+};
+
+uintptr_t marvell_get_ccu_reg_offs(void)
+{
+	return MVEBU_CCU_BASE;
+}
+
+int marvell_get_ccu_max_win(void)
+{
+	return MARVELL_CCU_MAX_WIN;
+}
+
+int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = sizeof(ccu_memory_map)/sizeof(struct ccu_win);
+
+	return 0;
+}
+/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
+#else
+/*******************************************************************************
+ * SKIP IMAGE Configuration
+ ******************************************************************************/
+
+struct skip_image skip_im = {
+	.detection_method = GPIO,
+	.info.gpio.num = 33,
+	.info.gpio.button_state = HIGH,
+	.info.test.cp_ap = CP,
+	.info.test.cp_index = 0,
+};
+
+void *plat_get_skip_image_data(void)
+{
+	/* Return the skip_image configurations */
+	return &skip_im;
+}
+#endif
diff --git a/plat/marvell/a8k/a80x0/plat_def.h b/plat/marvell/a8k/a80x0/plat_def.h
new file mode 100644
index 00000000..68987dcf
--- /dev/null
+++ b/plat/marvell/a8k/a80x0/plat_def.h
@@ -0,0 +1,44 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MVEBU_DEF_H__
+#define __MVEBU_DEF_H__
+
+#include <a8k_plat_def.h>
+
+#define CP_COUNT		2	/* A80x0 has both CP0 & CP1 */
+#define I2C_SPD_ADDR		0x53	/* Access SPD data */
+#define I2C_SPD_P0_ADDR		0x36	/* Select SPD data page 0 */
+
+#endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/a8k/a80x0/platform.mk
new file mode 100644
index 00000000..42fe2ce6
--- /dev/null
+++ b/plat/marvell/a8k/a80x0/platform.mk
@@ -0,0 +1,35 @@
+#
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include plat/marvell/a8k/common/a8k_common.mk
+
+include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/a80x0_cust/board/dram_port.c b/plat/marvell/a8k/a80x0_cust/board/dram_port.c
new file mode 100644
index 00000000..01cfdc92
--- /dev/null
+++ b/plat/marvell/a8k/a80x0_cust/board/dram_port.c
@@ -0,0 +1,150 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <arch_helpers.h>
+#include <plat_marvell.h>
+#include <debug.h>
+#include <dram_if.h>
+#include <plat_def.h>
+#include <mmio.h>
+#include <a8k_i2c.h>
+
+#include <mv_ddr_atf_wrapper.h>
+#include <apn806/mv_ddr_apn806.h>
+#include <apn806/mv_ddr_apn806_topology.h>
+#include <ddr3_topology_def.h>
+
+#define MVEBU_CP_MPP_CTRL37_OFFS		20
+#define MVEBU_CP_MPP_CTRL38_OFFS		24
+#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA	0x2
+#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA	0x2
+
+#define MVEBU_MPP_CTRL_MASK			0xf
+
+struct dram_config dram_cfg;
+
+/*
+ * This struct provides the DRAM training code with
+ * the appropriate board DRAM configuration
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	/* Board with 1CS 8Gb x4 devices of Micron 2400T */
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
+	{ { { {0x1, 0x0, 0, 0},	/* FIXME: change the cs mask for all 64 bit */
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0},
+	      {0x1, 0x0, 0, 0} },
+	   /* TODO: double check if the speed bin is 2400S */
+	   SPEED_BIN_DDR_2400S,		/* speed_bin */
+	   MV_DDR_DEV_WIDTH_8BIT,	/* sdram device width */
+	   MV_DDR_DIE_CAP_8GBIT,	/* die capacity */
+	   DDR_FREQ_SAR,		/* frequency */
+	   0, 0,			/* cas_l, cas_wl */
+	   MV_DDR_TEMP_LOW} },		/* temperature */
+	   MV_DDR_64BIT_BUS_MASK,	/* subphys mask */
+	   MV_DDR_CFG_SPD,		/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+struct dram_config *mv_ddr_dram_config_get(void)
+{
+	/* Return dram configuration as defined in the board code */
+	return &dram_cfg;
+}
+
+static void mpp_config(void)
+{
+	uint32_t val;
+	uintptr_t reg = MVEBU_CP_MPP_REGS(0, 4);
+
+	/* configure CP0 MPP 37 and 38 to i2c */
+	val = mmio_read_32(reg);
+	val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
+		(MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
+	val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << MVEBU_CP_MPP_CTRL37_OFFS) |
+		(MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << MVEBU_CP_MPP_CTRL38_OFFS);
+	mmio_write_32(reg, val);
+}
+
+/*
+ * This function may modify the default DRAM parameters
+ * based on information recieved from SPD or bootloader
+ * configuration located on non volatile storage
+ */
+int update_dram_info(struct dram_config *cfg)
+{
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
+
+	NOTICE("Gathering DRAM information\n");
+
+	if (tm->cfg_src == MV_DDR_CFG_SPD) {
+		/* configure MPPs to enable i2c */
+		mpp_config();
+		/* initialize the i2c */
+		i2c_init((void *)MVEBU_CP0_I2C_BASE);
+		/*
+		 * Dummy read to the SPD chip memory page selector.
+		 * It is needed for for selecting the SPD memory page 0
+		 * prior to accessing the DRAM configuration data
+		 */
+		i2c_read(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+		/* read data from spd */
+		i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
+			 sizeof(tm->spd_data.all_bytes));
+	}
+
+	return 0;
+}
+
+void *plat_get_dram_data(void)
+{
+	/* Update DRAM for dynamic platforms */
+	update_dram_info(&dram_cfg);
+
+	return &dram_cfg;
+}
diff --git a/plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c
new file mode 100644
index 00000000..ba4eeac1
--- /dev/null
+++ b/plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c
@@ -0,0 +1,198 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_config.h>
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+#include <plat_def.h>
+
+/*******************************************************************************
+ * AMB Configuration
+ ******************************************************************************/
+struct amb_win *amb_memory_map;
+
+uintptr_t marvell_get_amb_reg_offs(int cp_index)
+{
+	return MVEBU_AMB_ADEC_BASE(cp_index);
+}
+
+int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size)
+{
+	*win = amb_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(amb_memory_map)/sizeof(struct amb_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * RFU Configuration
+ ******************************************************************************/
+
+struct rfu_win rfu_memory_map[] = {
+	/* CP1 (MCI0) internal regs */
+	{0x0,	0xf4000000,			0x0,	0x2000000,  MCI_0_TID},
+	/* PCIe0 on CP1*/
+	{0x0,	0xfa000000,			0x0,	0x1000000,  MCI_0_TID},
+	/* PCIe1 on CP1*/
+	{0x0,	0xfb000000,			0x0,	0x1000000,  MCI_0_TID},
+	/* PCIe2 on CP1*/
+	{0x0,	0xfc000000,			0x0,	0x1000000,  MCI_0_TID},
+	/* MCI 0 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(0),	0x0,	0x100000,   MCI_0_TID},
+	/* MCI 1 indirect window */
+	{0x0,	MVEBU_MCI_REG_BASE_REMAP(1),	0x0,	0x100000,   MCI_1_TID},
+};
+
+uintptr_t marvell_get_rfu_reg_offs(void)
+{
+	return MVEBU_RFU_BASE;
+}
+
+int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size)
+{
+	*win = rfu_memory_map;
+	if (*win == NULL)
+		*size = 0;
+	else
+		*size = sizeof(rfu_memory_map)/sizeof(struct rfu_win);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * IOB Configuration
+ ******************************************************************************/
+#define MARVELL_IOB_MAX_WIN		16
+
+struct iob_win iob_memory_map_cp0[] = {
+	/* CP0 */
+	/* PEX1_X1 window */
+	{0x0,	0xf7000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xf8000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x0,	0xf6000000,	0x0,	0x1000000,	PEX0_TID}
+};
+
+struct iob_win iob_memory_map_cp1[] = {
+	/* CP1 */
+	/* PEX1_X1 window */
+	{0x0,	0xfb000000,	0x0,	0x1000000,	PEX1_TID},
+	/* PEX2_X1 window */
+	{0x0,	0xfc000000,	0x0,	0x1000000,	PEX2_TID},
+	/* PEX0_X4 window */
+	{0x0,	0xfa000000,	0x0,	0x1000000,	PEX0_TID}
+};
+
+uintptr_t marvell_get_iob_reg_offs(int cp_index)
+{
+	return MVEBU_IOB_BASE(cp_index);
+}
+
+int marvell_get_iob_max_win(void)
+{
+	return MARVELL_IOB_MAX_WIN;
+}
+
+int marvell_get_iob_memory_map(struct iob_win **win,
+			       uint32_t *size, int cp_index)
+{
+	switch (cp_index) {
+	case 0:
+		*win = iob_memory_map_cp0;
+		*size = sizeof(iob_memory_map_cp0)/sizeof(struct iob_win);
+		return 0;
+	case 1:
+		*win = iob_memory_map_cp1;
+		*size = sizeof(iob_memory_map_cp1)/sizeof(struct iob_win);
+		return 0;
+	default:
+		*size = 0;
+		*win = 0;
+		return 1;
+	}
+}
+
+/*******************************************************************************
+ * CCU Configuration
+ ******************************************************************************/
+#define MARVELL_CCU_MAX_WIN	8
+
+struct ccu_win ccu_memory_map[] = {
+	{0x0,	0xf2000000,	0x0,	0xe000000,  IO_0_TID}, /* IO window */
+};
+
+uintptr_t marvell_get_ccu_reg_offs(void)
+{
+	return MVEBU_CCU_BASE;
+}
+
+int marvell_get_ccu_max_win(void)
+{
+	return MARVELL_CCU_MAX_WIN;
+}
+
+int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size)
+{
+	*win = ccu_memory_map;
+	*size = sizeof(ccu_memory_map)/sizeof(struct ccu_win);
+
+	return 0;
+}
+/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
+#else
+/*******************************************************************************
+ * SKIP IMAGE Configuration
+ ******************************************************************************/
+
+struct skip_image skip_im = {
+	.detection_method = GPIO,
+	.info.gpio.num = 33,
+	.info.gpio.button_state = HIGH,
+	.info.test.cp_ap = CP,
+	.info.test.cp_index = 0,
+};
+
+void *plat_get_skip_image_data(void)
+{
+	/* Return the skip_image configurations */
+	return &skip_im;
+}
+#endif
diff --git a/plat/marvell/a8k/a80x0_cust/plat_def.h b/plat/marvell/a8k/a80x0_cust/plat_def.h
new file mode 100644
index 00000000..68987dcf
--- /dev/null
+++ b/plat/marvell/a8k/a80x0_cust/plat_def.h
@@ -0,0 +1,44 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MVEBU_DEF_H__
+#define __MVEBU_DEF_H__
+
+#include <a8k_plat_def.h>
+
+#define CP_COUNT		2	/* A80x0 has both CP0 & CP1 */
+#define I2C_SPD_ADDR		0x53	/* Access SPD data */
+#define I2C_SPD_P0_ADDR		0x36	/* Select SPD data page 0 */
+
+#endif /* __MVEBU_DEF_H__ */
diff --git a/plat/marvell/a8k/a80x0_cust/platform.mk b/plat/marvell/a8k/a80x0_cust/platform.mk
new file mode 100644
index 00000000..42fe2ce6
--- /dev/null
+++ b/plat/marvell/a8k/a80x0_cust/platform.mk
@@ -0,0 +1,35 @@
+#
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include plat/marvell/a8k/common/a8k_common.mk
+
+include plat/marvell/common/marvell_common.mk
diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk
new file mode 100644
index 00000000..4ab86dc9
--- /dev/null
+++ b/plat/marvell/a8k/common/a8k_common.mk
@@ -0,0 +1,120 @@
+
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+PLAT_FAMILY		:= a8k
+PLAT_FAMILY_BASE	:= plat/marvell/$(PLAT_FAMILY)
+PLAT_INCLUDE_BASE	:= include/plat/marvell/$(PLAT_FAMILY)
+PLAT_COMMON_BASE	:= $(PLAT_FAMILY_BASE)/common
+MARVELL_DRV_BASE	:= drivers/marvell
+
+CALL_DOIMAGE		:= y
+
+# This define specifies DDR type for BLE
+$(eval $(call add_define,CONFIG_DDR4))
+
+MARVELL_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
+				drivers/arm/gic/v2/gicv2_main.c		\
+				drivers/arm/gic/v2/gicv2_helpers.c	\
+				plat/common/plat_gicv2.c
+
+ATF_INCLUDES		:=	-Iinclude/common/tbbr
+
+PLAT_INCLUDES		:=	-I$(PLAT_FAMILY_BASE)/$(PLAT)		\
+				-I$(PLAT_COMMON_BASE)/include		\
+				-I$(PLAT_INCLUDE_BASE)/common		\
+				-Iinclude/drivers/marvell		\
+				-Iinclude/drivers/marvell/mochi		\
+				$(ATF_INCLUDES)
+
+PLAT_BL_COMMON_SOURCES	:=	$(PLAT_COMMON_BASE)/aarch64/a8k_common.c \
+				drivers/console/aarch64/console.S	 \
+				drivers/ti/uart/aarch64/16550_console.S
+
+BLE_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \
+			$(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
+
+BLE_SOURCES		:=	plat/marvell/common/sys_info.c		 \
+				plat/marvell/a8k/common/plat_ble_setup.c \
+				$(MARVELL_DRV_BASE)/mochi/cp110_setup.c	 \
+				$(MARVELL_DRV_BASE)/i2c/a8k_i2c.c	 \
+				$(BLE_PORTING_SOURCES)
+ifeq (${PCI_EP_SUPPORT}, 1)
+BLE_SOURCES		+=	plat/marvell/common/pci_ep_setup.c	 \
+				$(MARVELL_DRV_BASE)/dw-pcie-ep.c	 \
+				$(MARVELL_DRV_BASE)/pcie-comphy-cp110.c
+endif
+
+ifeq (${PALLADIUM}, 1)
+BL1_SOURCES		+=	$(PLAT_COMMON_BASE)/plat_bl1_setup.c
+endif
+
+BL1_SOURCES		+=	$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
+				lib/cpus/aarch64/cortex_a72.S
+
+MARVELL_DRV		:= 	$(MARVELL_DRV_BASE)/rfu.c	\
+				$(MARVELL_DRV_BASE)/iob.c	\
+				$(MARVELL_DRV_BASE)/mci.c	\
+				$(MARVELL_DRV_BASE)/amb_adec.c	\
+				$(MARVELL_DRV_BASE)/ccu.c	\
+				$(MARVELL_DRV_BASE)/icu.c	\
+				$(MARVELL_DRV_BASE)/cache_llc.c
+
+MARVELL_MOCHI_DRV	:=	$(MARVELL_DRV_BASE)/mochi/apn806_setup.c \
+				$(MARVELL_DRV_BASE)/mochi/cp110_setup.c
+
+BL31_PORTING_SOURCES	:=	$(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
+
+BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		       \
+				$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S     \
+				$(PLAT_COMMON_BASE)/aarch64/plat_arch_config.c \
+				$(PLAT_COMMON_BASE)/plat_pm.c		       \
+				$(PLAT_COMMON_BASE)/plat_bl31_setup.c	       \
+				plat/marvell/common/marvell_gicv2.c	       \
+				$(BL31_PORTING_SOURCES)			       \
+				$(MARVELL_DRV)				       \
+				$(MARVELL_MOCHI_DRV)			       \
+				$(MARVELL_GIC_SOURCES)
+
+# Add trace functionality for PM
+ifneq (${SCP_BL2},)
+BL31_SOURCES		+=	$(PLAT_COMMON_BASE)/plat_pm_trace.c
+endif
+
+# Disable the PSCI platform compatibility layer (allows porting
+# from Old Platform APIs to the new APIs).
+# It is not needed since Marvell platform already used the new platform APIs.
+ENABLE_PLAT_COMPAT	:= 	0
+
+# MSS (SCP) build
+ifneq (${SCP_BL2},)
+include plat/marvell/a8k/common/mss/mss_common.mk
+endif
diff --git a/plat/marvell/a8k/common/aarch64/a8k_common.c b/plat/marvell/a8k/common/aarch64/a8k_common.c
new file mode 100644
index 00000000..44a7f2cd
--- /dev/null
+++ b/plat/marvell/a8k/common/aarch64/a8k_common.c
@@ -0,0 +1,91 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_marvell.h>
+
+
+/* MMU entry for internal (register) space access */
+#define MAP_DEVICE0	MAP_REGION_FLAT(DEVICE0_BASE,			\
+					DEVICE0_SIZE,			\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
+ * Table of regions for various BL stages to map using the MMU.
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_marvell_mmap[] = {
+	MARVELL_MAP_SHARED_RAM,
+	MAP_DEVICE0,
+	{0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_marvell_mmap[] = {
+	MARVELL_MAP_SHARED_RAM,
+	MAP_DEVICE0,
+	MARVELL_MAP_NS_DRAM1,
+	{0}
+};
+#endif
+
+#if IMAGE_BL2U
+const mmap_region_t plat_marvell_mmap[] = {
+	MAP_DEVICE0,
+	{0}
+};
+#endif
+
+#if IMAGE_BLE
+const mmap_region_t plat_marvell_mmap[] = {
+	MAP_DEVICE0,
+	{0}
+};
+#endif
+
+#if IMAGE_BL31
+const mmap_region_t plat_marvell_mmap[] = {
+	MARVELL_MAP_SHARED_RAM,
+	MAP_DEVICE0,
+	MARVELL_MAP_NS_DRAM1,
+	{0}
+};
+#endif
+#if IMAGE_BL32
+const mmap_region_t plat_marvell_mmap[] = {
+	MAP_DEVICE0,
+	{0}
+};
+#endif
+
+MARVELL_CASSERT_MMAP;
diff --git a/plat/marvell/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/a8k/common/aarch64/plat_arch_config.c
new file mode 100644
index 00000000..f3840a0a
--- /dev/null
+++ b/plat/marvell/a8k/common/aarch64/plat_arch_config.c
@@ -0,0 +1,73 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <platform.h>
+#include <arch_helpers.h>
+#include <mmio.h>
+#include <debug.h>
+#include <cache_llc.h>
+
+
+#define CCU_HTC_ASET			(MVEBU_CCU_BASE + 0x264)
+#define MVEBU_IO_AFFINITY		(0xF00)
+
+
+void plat_enable_affinity(void)
+{
+	int cluster_id;
+	int affinity;
+
+	/* set CPU Affinity */
+	cluster_id = plat_my_core_pos() / PLAT_MARVELL_CLUSTER_CORE_COUNT;
+	affinity = (MVEBU_IO_AFFINITY | (1 << cluster_id));
+	mmio_write_32(CCU_HTC_ASET, affinity);
+
+	/* set barier */
+	__asm__ volatile("isb");
+}
+
+void psci_arch_init(void)
+{
+#if !LLC_DISABLE
+	/* check if LLC is in exclusive mode
+	 * as L2 is configured to UniqueClean eviction
+	 * (in a8k reset handler)
+	 */
+	if (llc_is_exclusive() == 0)
+		ERROR("LLC should be configured to exclusice mode\n");
+#endif
+
+	/* Enable Affinity */
+	plat_enable_affinity();
+}
diff --git a/plat/marvell/a8k/common/aarch64/plat_helpers.S b/plat/marvell/a8k/common/aarch64/plat_helpers.S
new file mode 100644
index 00000000..acc9d045
--- /dev/null
+++ b/plat/marvell/a8k/common/aarch64/plat_helpers.S
@@ -0,0 +1,125 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_get_my_entrypoint
+	.globl	plat_is_my_cpu_primary
+	.globl  plat_reset_handler
+
+	/* -----------------------------------------------------
+	 * void plat_secondary_cold_boot_setup (void);
+	 *
+	 * This function performs any platform specific actions
+	 * needed for a secondary cpu after a cold reset. Right
+	 * now this is a stub function.
+	 * -----------------------------------------------------
+	 */
+func plat_secondary_cold_boot_setup
+	mov	x0, #0
+	ret
+endfunc plat_secondary_cold_boot_setup
+
+	/* ---------------------------------------------------------------------
+	 * unsigned long plat_get_my_entrypoint (void);
+	 *
+	 * Main job of this routine is to distinguish
+	 * between a cold and warm boot
+	 * For a cold boot, return 0.
+	 * For a warm boot, read the mailbox and return the address it contains.
+	 *
+	 * ---------------------------------------------------------------------
+	 */
+func plat_get_my_entrypoint
+	mov_imm x0, PLAT_MARVELL_MAILBOX_BASE
+	ldr     x0, [x0]
+	ret
+endfunc plat_get_my_entrypoint
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_is_my_cpu_primary (void);
+	 *
+	 * Find out whether the current cpu is the primary
+	 * cpu.
+	 * -----------------------------------------------------
+	 */
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, #MVEBU_PRIMARY_CPU
+	cset	w0, eq
+	ret
+endfunc plat_is_my_cpu_primary
+
+        /* -----------------------------------------------------
+	 * void plat_reset_handler (void);
+         *
+	 * Platform specific configuration right after cpu is
+	 * is our of reset.
+	 *
+         * The plat_reset_handler can clobber x0 - x18, x30.
+         * -----------------------------------------------------
+         */
+func plat_reset_handler
+	/*
+	 * Note: the configurations below  should be done before MMU,
+	 *	  I Cache and L2are enabled.
+	 *	  The reset handler is executed right after reset
+	 * 	  and before Caches are enabled.
+	 */
+
+	/* Enable L1/L2 ECC and Parity */
+	mrs x5, s3_1_c11_c0_2  /* L2 Ctrl */
+	orr x5, x5, #(1 << 21) /* Enable L1/L2 cache ECC & Parity */
+	msr s3_1_c11_c0_2, x5  /* L2 Ctrl */
+
+#if !LLC_DISABLE
+	/*
+	 * Enable L2 UniqueClean evictions
+	 *  Note: this configuration assumes that LLC is configured
+	 *	  in exclusive mode.
+	 *	  Later on in the code this assumption will be validated
+	 */
+	mrs x5, s3_1_c15_c0_0  /* L2 Ctrl */
+	orr x5, x5, #(1 << 14) /* Enable UniqueClean evictions with data */
+	msr s3_1_c15_c0_0, x5  /* L2 Ctrl */
+#endif
+
+	/* Instruction Barrier to allow msr command completion */
+	isb
+
+        ret
+endfunc plat_reset_handler
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h
new file mode 100644
index 00000000..de218444
--- /dev/null
+++ b/plat/marvell/a8k/common/include/a8k_plat_def.h
@@ -0,0 +1,148 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MVEBU_A8K_DEF_H__
+#define __MVEBU_A8K_DEF_H__
+
+#include <arm_def.h>
+
+#define MVEBU_PRIMARY_CPU		0x0
+
+#if PALLADIUM
+#define COUNTER_FREQUENCY		48000
+#else
+#define COUNTER_FREQUENCY		25000000
+#endif
+
+#define MVEBU_REGS_BASE			0xF0000000
+#define MVEBU_REGS_BASE_MASK		0xF0000000
+#define MVEBU_CP_REGS_BASE(cp_index)	(0xF2000000 + (cp_index) * 0x2000000)
+#define MVEBU_RFU_BASE			(MVEBU_REGS_BASE + 0x6F0000)
+#define MVEBU_CCU_BASE			(MVEBU_REGS_BASE + 0x4000)
+#define MVEBU_LLC_BASE			(MVEBU_REGS_BASE + 0x8000)
+#define MVEBU_IOB_BASE(cp_index)	(MVEBU_CP_REGS_BASE(cp_index) + \
+								0x190000)
+#define MVEBU_DRAM_MAC_BASE		(MVEBU_REGS_BASE + 0x20000)
+#define MVEBU_DRAM_PHY_BASE		(MVEBU_REGS_BASE + 0x20000)
+#define MVEBU_AMB_IP_BASE(cp_index)	(MVEBU_CP_REGS_BASE(cp_index) + \
+								0x13ff00)
+#define MVEBU_AMB_ADEC_BASE(cp_index)	(MVEBU_CP_REGS_BASE(cp_index) + \
+								0x70ff00)
+#define MVEBU_SMMU_BASE			(MVEBU_REGS_BASE + 0x100000)
+#define MVEBU_CP_MPP_REGS(cp_index, n)	(MVEBU_CP_REGS_BASE(cp_index) + \
+							0x440000 + ((n) << 2))
+#define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
+					0x440110 + ((n > 32) ? 0x40 : 0x00))
+#define MVEBU_ICU_REG_BASE(cp_index)	(MVEBU_CP_REGS_BASE(cp_index) + \
+								0x1E0000)
+#define MVEBU_AP_MPP_REGS(n)		(MVEBU_RFU_BASE + 0x4000 + ((n) << 2))
+#define MVEBU_AP_GPIO_REGS		(MVEBU_RFU_BASE + 0x5040)
+#define MVEBU_AP_GPIO_DATA_IN		(MVEBU_AP_GPIO_REGS + 0x10)
+#define MVEBU_AP_I2C_BASE		(MVEBU_REGS_BASE + 0x511000)
+#define MVEBU_CP0_I2C_BASE		(MVEBU_CP_REGS_BASE(0) + 0x701000)
+
+#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + ((index) * 0x1000000))
+
+#define MVEBU_PCIE_X4_MAC_BASE(x)	(MVEBU_CP_REGS_BASE(x) + 0x600000)
+#define MVEBU_COMPHY_BASE(x)		(MVEBU_CP_REGS_BASE(x) + 0x441000)
+#define MVEBU_HPIPE_BASE(x)		(MVEBU_CP_REGS_BASE(x) + 0x120000)
+#define MVEBU_CP_DFX_BASE(x)		(MVEBU_CP_REGS_BASE(x) + 0x400200)
+
+/*******************************************************************************
+ * MVEBU memory map related constants
+ ******************************************************************************/
+
+/* Aggregate of all devices in the first GB */
+#define DEVICE0_BASE			MVEBU_REGS_BASE
+#define DEVICE0_SIZE			0x10000000
+
+/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MVEBU compatible GIC memory map */
+#define MVEBU_GICD_BASE			0x210000
+#define MVEBU_GICC_BASE			0x220000
+
+
+/*******************************************************************************
+ * AXI Configuration
+ ******************************************************************************/
+#define MVEBU_AXI_ATTR_ARCACHE_OFFSET		4
+#define MVEBU_AXI_ATTR_ARCACHE_MASK		(0xF << \
+						 MVEBU_AXI_ATTR_ARCACHE_OFFSET)
+#define MVEBU_AXI_ATTR_ARDOMAIN_OFFSET		12
+#define MVEBU_AXI_ATTR_ARDOMAIN_MASK		(0x3 << \
+						 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET)
+#define MVEBU_AXI_ATTR_AWCACHE_OFFSET		20
+#define MVEBU_AXI_ATTR_AWCACHE_MASK		(0xF << \
+						 MVEBU_AXI_ATTR_AWCACHE_OFFSET)
+#define MVEBU_AXI_ATTR_AWDOMAIN_OFFSET		28
+#define MVEBU_AXI_ATTR_AWDOMAIN_MASK		(0x3 << \
+						 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET)
+
+/* SATA MBUS to AXI configuration */
+#define MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET	1
+#define MVEBU_SATA_M2A_AXI_ARCACHE_MASK		(0xF << \
+					MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET)
+#define MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET	5
+#define MVEBU_SATA_M2A_AXI_AWCACHE_MASK		(0xF << \
+					MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET)
+
+/* ARM cache attributes */
+#define CACHE_ATTR_BUFFERABLE			0x1
+#define CACHE_ATTR_CACHEABLE			0x2
+#define CACHE_ATTR_READ_ALLOC			0x4
+#define CACHE_ATTR_WRITE_ALLOC			0x8
+/* Domain */
+#define DOMAIN_NON_SHAREABLE			0x0
+#define DOMAIN_INNER_SHAREABLE			0x1
+#define DOMAIN_OUTER_SHAREABLE			0x2
+#define DOMAIN_SYSTEM_SHAREABLE			0x3
+
+/*************************************************************************
+ * Required platform porting definitions common to all
+ * Mangement Compute SubSystems (MSS)
+ ************************************************************************
+ */
+/*
+ * Load address of SCP_BL2
+ * SCP_BL2 is loaded to the same place as BL31.
+ * Once SCP_BL2 is transferred to the SCP,
+ * it is discarded and BL31 is loaded over the top.
+ */
+#ifdef SCP_IMAGE
+#define SCP_BL2_BASE                    BL31_BASE
+#endif
+
+#endif /* __MVEBU_A8K_DEF_H__ */
diff --git a/plat/marvell/a8k/common/include/plat_macros.S b/plat/marvell/a8k/common/include/plat_macros.S
new file mode 100644
index 00000000..8a555e2e
--- /dev/null
+++ b/plat/marvell/a8k/common/include/plat_macros.S
@@ -0,0 +1,47 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+#include <arm_macros.S>
+
+/*
+ * Required platform porting macros
+ * (Provided by included headers)
+ */
+.macro plat_crash_print_regs
+.endm
+
+#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h
new file mode 100644
index 00000000..773822e2
--- /dev/null
+++ b/plat/marvell/a8k/common/include/platform_def.h
@@ -0,0 +1,202 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <board_marvell_def.h>
+#include <plat_def.h>
+#ifndef __ASSEMBLY__
+#include <stdio.h>
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Most platform porting definitions provided by included headers
+ */
+
+/*
+ * DRAM Memory layout:
+ *		+-----------------------+
+ *		:			:
+ *		:	Linux		:
+ * 0x04X00000-->+-----------------------+
+ *		|	BL3-3(u-boot)	|>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
+ *		|-----------------------|  }				       |
+ *		|	BL3-[0,1, 2]	|  }---------------------------------> |
+ *		|-----------------------|  }				||     |
+ *		|	BL2		|  }->FIP (loaded by            ||     |
+ *		|-----------------------|  }       BootROM to DRAM)     ||     |
+ *		|	FIP_TOC		|  }                            ||     |
+ * 0x04120000-->|-----------------------|				||     |
+ *		|	BL1 (RO)	|				||     |
+ * 0x04100000-->+-----------------------+				||     |
+ *		:			:				||     |
+ *		: Trusted SRAM section	:				\/     |
+ * 0x04040000-->+-----------------------+  Replaced by BL2  +----------------+ |
+ *		|	BL1 (RW)	|  <<<<<<<<<<<<<<<< | BL3-1 NOBITS   | |
+ * 0x04037000-->|-----------------------|  <<<<<<<<<<<<<<<< |----------------| |
+ *		|			|  <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | |
+ * 0x04023000-->|-----------------------|		    +----------------+ |
+ *		|	BL2		|				       |
+ *		|-----------------------|				       |
+ *		|			|				       |
+ * 0x04001000-->|-----------------------|				       |
+ *		|	Shared		|				       |
+ * 0x04000000-->+-----------------------+				       |
+ *		:			:				       |
+ *		:	Linux		:				       |
+ *		:			:				       |
+ *		|-----------------------|				       |
+ *		|			|	U-Boot(BL3-3) Loaded by BL2    |
+ *		|	U-Boot		|	<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+ * 0x00000000-->+-----------------------+
+ *
+ * Trusted SRAM section 0x4000000..0x4200000:
+ * ----------------------------------------
+ * SRAM_BASE		= 0x4001000
+ * BL2_BASE			= 0x4006000
+ * BL2_LIMIT		= BL31_BASE
+ * BL31_BASE		= 0x4023000 = (64MB + 256KB - 0x1D000)
+ * BL31_PROGBITS_LIMIT	= BL1_RW_BASE
+ * BL1_RW_BASE		= 0x4037000 = (64MB + 256KB - 0x9000)
+ * BL1_RW_LIMIT		= BL31_LIMIT = 0x4040000
+ *
+ *
+ * PLAT_MARVELL_FIP_BASE	= 0x4120000
+ */
+
+/*
+ * Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0,
+ * it is allowed to load/copy images to 'NULL' pointers
+ */
+#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
+#define PLAT_ALLOW_ZERO_ADDR_COPY
+#endif
+
+#define PLAT_MARVELL_SRAM_BASE			0xFFE1C048
+#define PLAT_MARVELL_SRAM_END			0xFFE3F000
+
+#define PLAT_MARVELL_ATF_BASE			0x4000000
+#define PLAT_MARVELL_ATF_LOAD_ADDR		(PLAT_MARVELL_ATF_BASE + \
+								0x100000)
+
+#define PLAT_MARVELL_FIP_BASE			(PLAT_MARVELL_ATF_LOAD_ADDR + \
+								0x20000)
+#define PLAT_MARVELL_FIP_MAX_SIZE		0x4000000
+
+#define PLAT_MARVELL_CLUSTER_COUNT		2
+#define PLAT_MARVELL_CLUSTER_CORE_COUNT		2
+
+#define PLAT_MARVELL_CORE_COUNT			(PLAT_MARVELL_CLUSTER_COUNT * \
+						PLAT_MARVELL_CLUSTER_CORE_COUNT)
+
+/* DRAM[2MB..66MB] is used as Trusted ROM */
+#define PLAT_MARVELL_TRUSTED_ROM_BASE		PLAT_MARVELL_ATF_LOAD_ADDR
+/* 64 MB TODO: reduce this to minimum needed according to fip image size */
+#define PLAT_MARVELL_TRUSTED_ROM_SIZE		0x04000000
+/* TODO: update SCP (Secure PayLoad) Trusted DRAM actual BASE & size */
+#define PLAT_MARVELL_TRUSTED_DRAM_BASE		0x06000000
+#define PLAT_MARVELL_TRUSTED_DRAM_SIZE		0x02000000	/* 32 MB */
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_MARVELL_MAX_BL1_RW_SIZE		0xA000
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#define PLAT_MARVELL_MAX_BL2_SIZE		0xF000
+
+/*
+ * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
+ * little space for growth.
+ */
+#define PLAT_MARVEL_MAX_BL31_SIZE		0x1D000
+
+#define PLAT_MARVELL_CPU_ENTRY_ADDR		BL1_RO_BASE
+
+/* GIC related definitions */
+#define PLAT_MARVELL_GICD_BASE		(MVEBU_REGS_BASE + MVEBU_GICD_BASE)
+#define PLAT_MARVELL_GICC_BASE		(MVEBU_REGS_BASE + MVEBU_GICC_BASE)
+
+#define PLAT_MARVELL_G0_IRQS			MARVELL_G1S_IRQS
+#define PLAT_MARVELL_G1S_IRQS			MARVELL_G0_IRQS
+
+#define PLAT_MARVELL_SHARED_RAM_CACHED		1
+
+/*
+ * Load address of BL3-3 for this platform port
+ */
+#if PALLADIUM
+#define PLAT_MARVELL_NS_IMAGE_OFFSET		0x1000
+#else
+#define PLAT_MARVELL_NS_IMAGE_OFFSET		0x0
+#endif
+
+/* System Reference Clock*/
+#define PLAT_REF_CLK_IN_HZ			COUNTER_FREQUENCY
+
+/*
+ * PL011 related constants
+ */
+#define PLAT_MARVELL_BOOT_UART_BASE		(MVEBU_REGS_BASE + 0x512000)
+#if PALLADIUM
+#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ	384000
+#else
+#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ	200000000
+#endif
+
+#define PLAT_MARVELL_CRASH_UART_BASE		PLAT_MARVELL_BOOT_UART_BASE
+#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ	PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+
+#define PLAT_MARVELL_BL31_RUN_UART_BASE		PLAT_MARVELL_BOOT_UART_BASE
+#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ	PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+
+/* Required platform porting definitions */
+#define PLAT_MAX_PWR_LVL			MPIDR_AFFLVL1
+
+/* System timer related constants */
+#define PLAT_MARVELL_NSTIMER_FRAME_ID		1
+
+/*
+ * Mailbox base address
+ * (note the lower memory space are reserved for BLE data)
+ */
+#define PLAT_MARVELL_MAILBOX_BASE	(MARVELL_TRUSTED_SRAM_BASE + 0x400)
+#define PLAT_MARVELL_MAILBOX_SIZE	0x100
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c
new file mode 100644
index 00000000..e5f4f6b8
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c
@@ -0,0 +1,64 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <bl_common.h>
+#include <debug.h>
+#include <plat_private.h> /* timer functionality */
+#include "mss_scp_bootloader.h"
+
+
+/*******************************************************************************
+ * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
+ * Return 0 on success, -1 otherwise.
+ ******************************************************************************/
+int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
+{
+	int ret;
+
+	INFO("BL2: Initiating SCP_BL2 transfer to SCP\n");
+	printf("BL2: Initiating SCP_BL2 transfer to SCP\n");
+
+	/* initialize time (for delay functionality) */
+	plat_delay_timer_init();
+
+	ret = scp_bootloader_transfer((void *)scp_bl2_image_info->image_base,
+		scp_bl2_image_info->image_size);
+
+	if (ret == 0)
+		INFO("BL2: SCP_BL2 transferred to SCP\n");
+	else
+		ERROR("BL2: SCP_BL2 transfer failure\n");
+
+	return ret;
+}
diff --git a/plat/marvell/a8k/common/mss/mss_common.mk b/plat/marvell/a8k/common/mss/mss_common.mk
new file mode 100644
index 00000000..b806dc13
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_common.mk
@@ -0,0 +1,52 @@
+#
+# ***************************************************************************
+# Copyright (C) 2016 Marvell International Ltd.
+# ***************************************************************************
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of Marvell nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+PLAT_MARVELL		:= 	plat/marvell
+MSS_SOURCE		:= 	$(PLAT_MARVELL)/a8k/common/mss
+
+BL2_SOURCES		+=	$(MSS_SOURCE)/mss_bl2_setup.c		\
+				$(MSS_SOURCE)/mss_scp_bootloader.c 	\
+                                $(PLAT_MARVELL)/common/plat_delay_timer.c \
+				drivers/delay_timer/delay_timer.c
+
+BL31_SOURCES		+=	$(MSS_SOURCE)/mss_ipc_drv.c		\
+				$(MSS_SOURCE)/mss_pm_ipc.c
+
+PLAT_INCLUDES           +=      -I$(MSS_SOURCE)
+
+ifneq (${SCP_BL2},)
+# Subsystems require a SCP_BL2 image
+$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
+
+# This define is used to inidcate the SCP image is present
+$(eval $(call add_define,SCP_IMAGE))
+endif
diff --git a/plat/marvell/a8k/common/mss/mss_ipc_drv.c b/plat/marvell/a8k/common/mss/mss_ipc_drv.c
new file mode 100644
index 00000000..e261bb44
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_ipc_drv.c
@@ -0,0 +1,147 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <debug.h>
+#include <string.h>
+#include <mss_ipc_drv.h>
+#include <mmio.h>
+
+#define IPC_MSG_BASE_MASK		MVEBU_REGS_BASE_MASK
+
+
+unsigned long mv_pm_ipc_msg_base;
+unsigned int  mv_pm_ipc_num_of_ch;
+unsigned int  mv_pm_ipc_channel_size;
+unsigned int  mv_pm_ipc_queue_size;
+
+/*******************************************************************************
+ * mss_pm_ipc_init
+ *
+ * DESCRIPTION: Initialize PM IPC infrastructure
+ ******************************************************************************
+ */
+int mv_pm_ipc_init(unsigned long ipc_control_addr)
+{
+	struct mss_pm_ipc_ctrl *ipc_control =
+			(struct mss_pm_ipc_ctrl *)ipc_control_addr;
+
+	/* Initialize PM IPC control block */
+	mv_pm_ipc_msg_base     = ipc_control->msg_base_address |
+						IPC_MSG_BASE_MASK;
+	mv_pm_ipc_num_of_ch    = ipc_control->num_of_channels;
+	mv_pm_ipc_channel_size = ipc_control->channel_size;
+	mv_pm_ipc_queue_size   = ipc_control->queue_size;
+
+	return 0;
+}
+
+/*******************************************************************************
+ * mv_pm_ipc_queue_addr_get
+ *
+ * DESCRIPTION: Returns the IPC queue address
+ ******************************************************************************
+ */
+unsigned int mv_pm_ipc_queue_addr_get(unsigned int channel_id,
+				      unsigned int direction)
+{
+	return  (unsigned int)(mv_pm_ipc_msg_base +
+			       (channel_id * mv_pm_ipc_channel_size) +
+			       (direction  * mv_pm_ipc_queue_size));
+}
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_rx
+ *
+ * DESCRIPTION: Retrieve message from IPC channel
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_rx(unsigned int channel_id, unsigned int direction,
+		     struct mss_pm_ipc_msg *msg)
+{
+	unsigned int addr = mv_pm_ipc_queue_addr_get(channel_id, direction);
+
+	msg->msg_reply = mmio_read_32(addr + IPC_MSG_REPLY_LOC);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_reply
+ *
+ * DESCRIPTION: Send message via IPC channel
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int direction,
+		     unsigned int cluster_power_state)
+{
+	unsigned int addr = mv_pm_ipc_queue_addr_get(channel_id, direction);
+
+	mmio_write_32(addr + IPC_MSG_POWER_STATE_LOC, cluster_power_state);
+	mmio_write_32(addr + IPC_MSG_STATE_LOC, IPC_MSG_OCCUPY);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_validate
+ *
+ * DESCRIPTION: Validate IPC channel state
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_validate(unsigned int channel_id, unsigned int direction,
+			   unsigned int state)
+{
+	unsigned int addr = mv_pm_ipc_queue_addr_get(channel_id, direction);
+
+	if (mmio_read_32(addr + IPC_MSG_STATE_LOC) != state)
+		return -1;
+
+	return 0;
+}
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_update
+ *
+ * DESCRIPTION: Update IPC channel state
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_update(unsigned int channel_id, unsigned int direction,
+			 unsigned int state)
+{
+	unsigned int addr = mv_pm_ipc_queue_addr_get(channel_id, direction);
+
+	mmio_write_32(addr + IPC_MSG_STATE_LOC, state);
+
+	return 0;
+}
diff --git a/plat/marvell/a8k/common/mss/mss_ipc_drv.h b/plat/marvell/a8k/common/mss/mss_ipc_drv.h
new file mode 100644
index 00000000..7c8995cf
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_ipc_drv.h
@@ -0,0 +1,168 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __PM_IPC_DRV_H
+#define __PM_IPC_DRV_H
+
+
+#include <platform_def.h>
+
+
+#define MV_PM_FW_IPC_VERSION_MAGIC	(0xCA530000) /* Do NOT change */
+/* Increament for each version */
+#define MV_PM_FW_IPC_VERSION_SEQ	(0x00000001)
+#define MV_PM_FW_IPC_VERSION		(MV_PM_FW_IPC_VERSION_MAGIC | \
+					 MV_PM_FW_IPC_VERSION_SEQ)
+
+#define IPC_MSG_STATE_LOC		(0x0)
+#define IPC_MSG_SYNC_ID_LOC		(0x4)
+#define IPC_MSG_ID_LOC			(0x8)
+#define IPC_MSG_RET_CH_ID_LOC	(0xC)
+#define IPC_MSG_CPU_ID_LOC		(0x10)
+#define IPC_MSG_CLUSTER_ID_LOC	(0x14)
+#define IPC_MSG_SYSTEM_ID_LOC	(0x18)
+#define IPC_MSG_POWER_STATE_LOC	(0x1C)
+#define IPC_MSG_REPLY_LOC		(0x20)
+#define IPC_MSG_RESERVED_LOC	(0x24)
+
+/* IPC initialization state */
+enum mss_pm_ipc_init_state {
+	IPC_UN_INITIALIZED	= 1,
+	IPC_INITIALIZED		= 2
+};
+
+/* IPC queue direction */
+enum mss_pm_ipc_init_msg_dir {
+	IPC_MSG_TX	= 0,
+	IPC_MSG_RX	= 1
+};
+
+/* IPC message state */
+enum mss_pm_ipc_msg_state {
+	IPC_MSG_FREE	= 1,
+	IPC_MSG_OCCUPY	= 2
+
+};
+
+/* IPC control block */
+struct mss_pm_ipc_ctrl {
+	unsigned int ctrl_base_address;
+	unsigned int msg_base_address;
+	unsigned int num_of_channels;
+	unsigned int channel_size;
+	unsigned int queue_size;
+};
+
+/* IPC message types */
+enum mss_pm_msg_id {
+	PM_IPC_MSG_CPU_SUSPEND		= 1,
+	PM_IPC_MSG_CPU_OFF		= 2,
+	PM_IPC_MSG_CPU_ON		= 3,
+	PM_IPC_MSG_SYSTEM_RESET		= 4,
+	PM_IPC_MSG_SYSTEM_SUSPEND	= 5,
+	PM_IPC_MAX_MSG
+};
+
+struct mss_pm_ipc_msg {
+	unsigned int	msg_sync_id;	/*
+					 * Sync number, validate message
+					 * reply corresponding to message
+					 * received
+					 */
+	unsigned int	msg_id;		/* Message Id */
+	unsigned int	ret_channel_id;	/* IPC channel reply */
+	unsigned int	cpu_id;		/* CPU Id */
+	unsigned int	cluster_id;	/* Cluster Id */
+	unsigned int	system_id;	/* System Id */
+	unsigned int	power_state;
+	unsigned int	msg_reply;	/* Message reply */
+};
+
+/* IPC queue */
+struct mss_pm_ipc_queue {
+	unsigned int	state;
+	struct mss_pm_ipc_msg		msg;
+};
+
+/* IPC channel */
+struct mss_pm_ipc_ch {
+	struct mss_pm_ipc_queue *tx_queue;
+	struct mss_pm_ipc_queue *rx_queue;
+};
+
+/*******************************************************************************
+ * mv_pm_ipc_init
+ *
+ * DESCRIPTION: Initialize PM IPC infrastructure
+ ******************************************************************************
+ */
+int mv_pm_ipc_init(unsigned long ipc_control_addr);
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_rx
+ *
+ * DESCRIPTION: Retrieve message from IPC channel
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_rx(unsigned int channel_id, unsigned int direction,
+		     struct mss_pm_ipc_msg *msg);
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_tx
+ *
+ * DESCRIPTION: Send message via IPC channel
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int direction,
+			unsigned int cluster_power_state);
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_validate
+ *
+ * DESCRIPTION: Validate IPC channel state
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_validate(unsigned int channel_id, unsigned int direction,
+			   unsigned int state);
+
+/*******************************************************************************
+ * mv_pm_ipc_msg_update
+ *
+ * DESCRIPTION: Update IPC channel state
+ ******************************************************************************
+ */
+int mv_pm_ipc_msg_update(unsigned int channel_id, unsigned int direction,
+			 unsigned int state);
+
+#endif /* __PM_IPC_DRV_H */
diff --git a/plat/marvell/a8k/common/mss/mss_mem.h b/plat/marvell/a8k/common/mss/mss_mem.h
new file mode 100644
index 00000000..bed5584c
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_mem.h
@@ -0,0 +1,87 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MSS_PM_MEM_H
+#define __MSS_PM_MEM_H
+
+/* MSS SRAM Memory base */
+#define MSS_SRAM_PM_CONTROL_BASE		(MVEBU_REGS_BASE + 0x520000)
+
+enum mss_pm_ctrl_handshake {
+	MSS_UN_INITIALIZED	= 0,
+	MSS_COMPATIBILITY_ERROR	= 1,
+	MSS_ACKNOWLEDGEMENT	= 2,
+	HOST_ACKNOWLEDGEMENT	= 3
+};
+
+enum mss_pm_ctrl_rtos_env {
+	MSS_MULTI_PROCESS_ENV	= 0,
+	MSS_SINGLE_PROCESS_ENV	= 1,
+	MSS_MAX_PROCESS_ENV
+};
+
+struct mss_pm_ctrl_block {
+	/* This field is used to synchronize the Host
+	 * and MSS initialization sequence
+	 * Valid Values
+	 * 0 - Un-Initialized
+	 * 1 - Compatibility Error
+	 * 2 - MSS Acknowledgment
+	 * 3 - Host Acknowledgment
+	 */
+	unsigned int handshake;
+
+	/*
+	 * This field include Host IPC version. Once received by the MSS
+	 * It will be compared to MSS IPC version and set MSS Acknowledge to
+	 * "compatibility error" in case there is no match
+	 */
+	unsigned int ipc_version;
+	unsigned int ipc_base_address;
+	unsigned int ipc_state;
+
+	/* Following fields defines firmware core architecture */
+	unsigned int num_of_cores;
+	unsigned int num_of_clusters;
+	unsigned int num_of_cores_per_cluster;
+
+	/* Following fields define pm trace debug base address */
+	unsigned int pm_trace_ctrl_base_address;
+	unsigned int pm_trace_info_base_address;
+	unsigned int pm_trace_info_core_size;
+
+	unsigned int ctrl_blk_size;
+};
+
+#endif /* __MSS_PM_MEM_H */
diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.c b/plat/marvell/a8k/common/mss/mss_pm_ipc.c
new file mode 100644
index 00000000..c5b01465
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.c
@@ -0,0 +1,147 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <mmio.h>
+#include <psci.h>
+#include <debug.h>
+#include <string.h>
+
+#include <mss_ipc_drv.h>
+#include <mss_pm_ipc.h>
+
+/*
+ ** SISR is 32 bit interrupt register representing 32 interrupts
+ **
+ ** +==================+==================+==================+=============+
+ ** + Suspend msg int  + Off msg int      + On msg int       + Reserved    +
+ ** +==================+==================+==================+=============+
+ ** + Bits 31 30 29 28 + Bits 27 26 25 24 + Bits 23 22 21 20 + Bits 19 - 0 +
+ ** +==================+==================+==================+=============+
+ ** + Core  3  2  1  0 + Core  3  2  1  0 + Core  3  2  1  0 +             +
+ ** +==================+==================+==================+=============+
+ **
+ ** Example: Bit 26 = Off Message Interrupt to core #2
+ */
+#define MSS_SISR		(MVEBU_REGS_BASE + 0x5800D0)
+
+#define MSS_CPU_SUSPEND_INT_SET_OFFSET		(28)
+#define MSS_CPU_OFF_INT_SET_OFFSET		(24)
+#define MSS_CPU_ON_INT_SET_OFFSET		(20)
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_send
+ *
+ * DESCRIPTION: create and transmit IPC message
+ ******************************************************************************
+ */
+int mss_pm_ipc_msg_send(unsigned int channel_id,
+			const psci_power_state_t *target_state)
+{
+	/* Transmit IPC message */
+#ifndef DISABLE_CLUSTER_LEVEL
+	mv_pm_ipc_msg_tx(channel_id, IPC_MSG_TX,
+		(unsigned int)target_state->pwr_domain_state[MPIDR_AFFLVL1]);
+#else
+	mv_pm_ipc_msg_tx(channel_id, IPC_MSG_TX, 0);
+#endif
+
+	return 0;
+}
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_recv
+ *
+ * DESCRIPTION: wait from reception of IPC message indication,
+ *              once received, read the message from IPC channel,
+ *              mark IPC channel as Free, and validate reply
+ ******************************************************************************
+ */
+int mss_pm_ipc_msg_recv(unsigned int channel_id, unsigned int msg_id)
+{
+	struct mss_pm_ipc_msg msg;
+
+	/* Wait for PC message indication */
+	do {} while (mv_pm_ipc_msg_validate(channel_id,
+					    IPC_MSG_RX, IPC_MSG_OCCUPY) != 0);
+
+	/* Read the message from IPC channel */
+	mv_pm_ipc_msg_rx(channel_id, IPC_MSG_RX, &msg);
+
+	/* Mark IPC channel as Free */
+	mv_pm_ipc_msg_update(channel_id, IPC_MSG_RX, IPC_MSG_FREE);
+
+	if (msg_id != msg.msg_reply) {
+		ERROR("MSS Error, Invalid reply message type %d\n",
+		      msg.msg_reply);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*******************************************************************************
+ * mss_pm_ipc_on_msg_trigger
+ *
+ * DESCRIPTION: Trigger IPC ON message interrupt to MSS
+ ******************************************************************************
+ */
+int mss_pm_ipc_on_msg_trigger(unsigned int cpu_id)
+{
+	mmio_write_32(MSS_SISR, 1 << (MSS_CPU_ON_INT_SET_OFFSET + cpu_id));
+	return 0;
+}
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_trigger
+ *
+ * DESCRIPTION: Trigger IPC OFF message interrupt to MSS
+ ******************************************************************************
+ */
+int mss_pm_ipc_suspend_msg_trigger(unsigned int cpu_id)
+{
+	mmio_write_32(MSS_SISR, 1 << (MSS_CPU_SUSPEND_INT_SET_OFFSET + cpu_id));
+	return 0;
+}
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_trigger
+ *
+ * DESCRIPTION: Trigger IPC SUSPEND message interrupt to MSS
+ ******************************************************************************
+ */
+int mss_pm_ipc_off_msg_trigger(unsigned int cpu_id)
+{
+	mmio_write_32(MSS_SISR, 1 << (MSS_CPU_OFF_INT_SET_OFFSET + cpu_id));
+	return 0;
+}
diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.h b/plat/marvell/a8k/common/mss/mss_pm_ipc.h
new file mode 100644
index 00000000..16044c06
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.h
@@ -0,0 +1,88 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MSS_PM_IPC_H
+#define __MSS_PM_IPC_H
+
+
+#include <mss_ipc_drv.h>
+/* Currently MSS does not support Cluster level Power Down */
+#define DISABLE_CLUSTER_LEVEL
+
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_send
+ *
+ * DESCRIPTION: create and transmit IPC message
+ ******************************************************************************
+ */
+int mss_pm_ipc_msg_send(unsigned int channel_id,
+			const psci_power_state_t *target_state);
+
+/*******************************************************************************
+ * mss_pm_ipc_msg_recv
+ *
+ * DESCRIPTION: wait from reception of IPC message indication,
+ *              once received, read the message from IPC channel,
+ *              mark IPC channel as Free, and validate reply
+ ******************************************************************************
+ */
+int mss_pm_ipc_msg_recv(unsigned int channel_id, unsigned int msg_id);
+
+/*******************************************************************************
+ * mss_pm_ipc_on_msg_trigger
+ *
+ * DESCRIPTION: Trigger IPC ON message interrupt to MSS
+ ******************************************************************************
+ */
+int mss_pm_ipc_on_msg_trigger(unsigned int cpu_id);
+
+/*******************************************************************************
+ * mss_pm_ipc_on_msg_trigger
+ *
+ * DESCRIPTION: Trigger IPC OFF message interrupt to MSS
+ ******************************************************************************
+ */
+int mss_pm_ipc_off_msg_trigger(unsigned int cpu_id);
+
+/*******************************************************************************
+ * mss_pm_ipc_on_msg_trigger
+ *
+ * DESCRIPTION: Trigger IPC SUSPEND message interrupt to MSS
+ ******************************************************************************
+ */
+int mss_pm_ipc_suspend_msg_trigger(unsigned int cpu_id);
+
+
+#endif /* __MSS_PM_IPC_H */
diff --git a/plat/marvell/a8k/common/mss/mss_scp_bootloader.c b/plat/marvell/a8k/common/mss/mss_scp_bootloader.c
new file mode 100644
index 00000000..2fc93120
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_scp_bootloader.c
@@ -0,0 +1,218 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <assert.h>
+#include <debug.h>
+#include <mmio.h>
+#include <arch_helpers.h> /* for cache maintanance operations */
+#include <platform_def.h>
+#include <delay_timer.h>
+#include <apn806_setup.h>
+
+#include <plat_pm_trace.h>
+#include <mss_scp_bootloader.h>
+#include <mss_ipc_drv.h>
+#include <mss_mem.h>
+
+
+#define MSS_DMA_SRCBR(base)		(base + 0xC0)
+#define MSS_DMA_DSTBR(base)		(base + 0xC4)
+#define MSS_DMA_CTRLR(base)		(base + 0xC8)
+#define MSS_M3_RSTCR(base)		(base + 0xFC)
+#define MSS_AEBR(base)			(base + 0x160)
+#define MSS_AIBR(base)			(base + 0x164)
+
+#define MSS_DMA_CTRLR_SIZE_OFFSET	(0)
+#define MSS_DMA_CTRLR_REQ_OFFSET	(15)
+#define MSS_DMA_CTRLR_REQ_SET		(1)
+#define MSS_DMA_CTRLR_ACK_OFFSET	(12)
+#define MSS_DMA_CTRLR_ACK_MASK		(0x1)
+#define MSS_DMA_CTRLR_ACK_READY		(1)
+#define MSS_M3_RSTCR_RST_OFFSET		(0)
+#define MSS_M3_RSTCR_RST_OFF		(1)
+#define MSS_AEBR_MASK			0xFFF
+#define MSS_AIBR_MASK			0xFFF
+
+#define MSS_DMA_TIMEOUT			1000
+#define MSS_EXTERNAL_SPACE		0x50000000
+#define MSS_EXTERNAL_ACCESS_BIT		28
+#define MSS_EXTERNAL_ADDR_MASK		0xfffffff
+#define MSS_INTERNAL_ACCESS_BIT		28
+
+#define DMA_SIZE			128
+
+#define MSS_HANDSHAKE_TIMEOUT		50
+/* TODO: Fix this */
+#define AP_MSS_REG_BASE			(MVEBU_REGS_BASE + 0x580000)
+
+
+static int mss_check_image_ready(struct mss_pm_ctrl_block *mss_pm_crtl)
+{
+	int timeout = MSS_HANDSHAKE_TIMEOUT;
+
+	/* Wait for SCP to signal it's ready */
+	while ((mss_pm_crtl->handshake != MSS_ACKNOWLEDGEMENT) &&
+						(timeout-- > 0))
+		mdelay(1);
+
+	/*
+	 * Check that the handshake was completed successfully
+	 * Note: since A0 doesn't support MSS load, this check is skipped
+	 */
+	if ((mss_pm_crtl->handshake != MSS_ACKNOWLEDGEMENT) &&
+	    (apn806_rev_id_get() != APN806_REV_ID_A0))
+		return -1;
+
+	mss_pm_crtl->handshake = HOST_ACKNOWLEDGEMENT;
+
+	return 0;
+}
+
+
+static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t  mss_regs)
+{
+	uint32_t i, loop_num, timeout;
+
+	NOTICE("Loading MSS image from address 0x%x Size 0x%x to MSS at 0x%x\n",
+	       src_addr, size, (uint32_t)mss_regs);
+	/* load image to MSS RAM using DMA */
+	loop_num = (size / DMA_SIZE) + (((size & (DMA_SIZE - 1)) == 0) ? 0 : 1);
+
+	/* set AXI External and Internal Address Bus extension */
+	mmio_write_32(MSS_AEBR(mss_regs), ((src_addr >> MSS_EXTERNAL_ACCESS_BIT)
+		      & MSS_AEBR_MASK));
+	mmio_write_32(MSS_AIBR(mss_regs), ((mss_regs >> MSS_INTERNAL_ACCESS_BIT)
+		      & MSS_AIBR_MASK));
+
+	for (i = 0; i < loop_num; i++) {
+		/* write destination and source addresses */
+		mmio_write_32(MSS_DMA_SRCBR(mss_regs),
+			      MSS_EXTERNAL_SPACE |
+			      ((src_addr & MSS_EXTERNAL_ADDR_MASK) +
+			      (i * DMA_SIZE)));
+		mmio_write_32(MSS_DMA_DSTBR(mss_regs), (i * DMA_SIZE));
+
+		dsb(); /* make sure DMA data is ready before triggering it */
+
+		/* set the DMA control register */
+		mmio_write_32(MSS_DMA_CTRLR(mss_regs), ((MSS_DMA_CTRLR_REQ_SET
+			      << MSS_DMA_CTRLR_REQ_OFFSET) |
+			      (DMA_SIZE << MSS_DMA_CTRLR_SIZE_OFFSET)));
+
+		/* Poll DMA_ACK at MSS_DMACTLR until it is ready */
+		timeout = MSS_DMA_TIMEOUT;
+		while (timeout) {
+			if ((mmio_read_32(MSS_DMA_CTRLR(mss_regs)) >>
+			     MSS_DMA_CTRLR_ACK_OFFSET & MSS_DMA_CTRLR_ACK_MASK)
+				== MSS_DMA_CTRLR_ACK_READY) {
+				break;
+			}
+
+			udelay(50);
+			timeout--;
+		}
+
+		if (timeout == 0) {
+			ERROR("\nDMA failed to load MSS image\n");
+			return 1;
+		}
+	}
+
+	/* Release M3 from reset */
+	mmio_write_32(MSS_M3_RSTCR(mss_regs), (MSS_M3_RSTCR_RST_OFF <<
+		      MSS_M3_RSTCR_RST_OFFSET));
+
+	NOTICE("Done\n");
+
+	return 0;
+}
+
+int scp_bootloader_transfer(void *image, unsigned int image_size)
+{
+	int ret;
+	struct mss_pm_ctrl_block *mss_pm_crtl;
+
+	assert((uintptr_t) image == SCP_BL2_BASE);
+
+	if ((image_size == 0) || (image_size % 4 != 0)) {
+		ERROR("SCP_BL2 image size must be a multiple of 4 bytes\n");
+		ERROR("and not zero (current size = 0x%x)\n", image_size);
+		return -1;
+	}
+
+	/* TODO: add PM Control Info from platform */
+	mss_pm_crtl = (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE;
+	mss_pm_crtl->ipc_version                = MV_PM_FW_IPC_VERSION;
+	mss_pm_crtl->num_of_clusters            = PLAT_MARVELL_CLUSTER_COUNT;
+	mss_pm_crtl->num_of_cores_per_cluster   =
+						PLAT_MARVELL_CLUSTER_CORE_COUNT;
+	mss_pm_crtl->num_of_cores               = PLAT_MARVELL_CLUSTER_COUNT *
+						PLAT_MARVELL_CLUSTER_CORE_COUNT;
+	mss_pm_crtl->pm_trace_ctrl_base_address = AP_MSS_ATF_CORE_CTRL_BASE;
+	mss_pm_crtl->pm_trace_info_base_address = AP_MSS_ATF_CORE_INFO_BASE;
+	mss_pm_crtl->pm_trace_info_core_size    = AP_MSS_ATF_CORE_INFO_SIZE;
+	VERBOSE("MSS Control Block = 0x%x\n", MSS_SRAM_PM_CONTROL_BASE);
+	VERBOSE("mss_pm_crtl->ipc_version                = 0x%x\n",
+		mss_pm_crtl->ipc_version);
+	VERBOSE("mss_pm_crtl->num_of_cores               = 0x%x\n",
+		mss_pm_crtl->num_of_cores);
+	VERBOSE("mss_pm_crtl->num_of_clusters            = 0x%x\n",
+		mss_pm_crtl->num_of_clusters);
+	VERBOSE("mss_pm_crtl->num_of_cores_per_cluster   = 0x%x\n",
+		mss_pm_crtl->num_of_cores_per_cluster);
+	VERBOSE("mss_pm_crtl->pm_trace_ctrl_base_address = 0x%x\n",
+		mss_pm_crtl->pm_trace_ctrl_base_address);
+	VERBOSE("mss_pm_crtl->pm_trace_info_base_address = 0x%x\n",
+		mss_pm_crtl->pm_trace_info_base_address);
+	VERBOSE("mss_pm_crtl->pm_trace_info_core_size    = 0x%x\n",
+		mss_pm_crtl->pm_trace_info_core_size);
+
+	/* TODO: add checksum to image */
+	VERBOSE("Send info about the SCP_BL2 image to be transferred to SCP\n");
+	NOTICE("Load image to AP MSS\n");
+	ret = mss_image_load((uintptr_t)image, image_size, AP_MSS_REG_BASE);
+	if (ret != 0) {
+		ERROR("SCP Image load failed\n");
+		return -1;
+	}
+
+	/* check that the image was loaded successfully */
+	ret = mss_check_image_ready(mss_pm_crtl);
+	if (ret != 0) {
+		ERROR("SCP Image check failed\n");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/plat/marvell/a8k/common/mss/mss_scp_bootloader.h b/plat/marvell/a8k/common/mss/mss_scp_bootloader.h
new file mode 100644
index 00000000..fe97e7a5
--- /dev/null
+++ b/plat/marvell/a8k/common/mss/mss_scp_bootloader.h
@@ -0,0 +1,40 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#ifndef __MSS_SCP_BOOTLOADER_H__
+#define __MSS_SCP_BOOTLOADER_H__
+
+int scp_bootloader_transfer(void *image, unsigned int image_size);
+
+#endif /* __MSS_SCP_BOOTLOADER_H__ */
diff --git a/plat/marvell/a8k/common/plat_bl1_setup.c b/plat/marvell/a8k/common/plat_bl1_setup.c
new file mode 100644
index 00000000..8851f0b1
--- /dev/null
+++ b/plat/marvell/a8k/common/plat_bl1_setup.c
@@ -0,0 +1,48 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_marvell.h>
+#include <mmio.h>
+#include <apn806_setup.h>
+#include <cp110_setup.h>
+
+#define MVEBU_MPP_REGS(n)	(0x6F4000 + ((n) << 2))
+void marvell_bl1_setup_mpps(void)
+{
+	/* Enable UART MPPs.
+	 ** In a normal system, this is done by Bootrom.
+	 */
+	mmio_write_32(MVEBU_REGS_BASE + MVEBU_MPP_REGS(1), 0x3000);
+	mmio_write_32(MVEBU_REGS_BASE + MVEBU_MPP_REGS(2), 0x3000);
+}
diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c
new file mode 100644
index 00000000..b736830f
--- /dev/null
+++ b/plat/marvell/a8k/common/plat_bl31_setup.c
@@ -0,0 +1,104 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_marvell.h>
+#include <plat_private.h>
+#include <apn806_setup.h>
+#include <cp110_setup.h>
+#include <mmio.h>
+#include <mci.h>
+#include <debug.h>
+
+#ifdef SCP_IMAGE
+#include <mss_ipc_drv.h>
+#include <mss_mem.h>
+#endif
+
+void marvell_bl31_mpp_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * Enable CP0 I2C MPPs (MPP: 37-38)
+	 * U-Boot rely on proper MPP settings for I2C EEPROM usage
+	 * (only for CP0)
+	 */
+	reg = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4));
+	mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
+}
+
+void marvell_bl31_mss_init(void)
+{
+#ifdef SCP_IMAGE
+	struct mss_pm_ctrl_block *mss_pm_crtl =
+			(struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE;
+
+	INFO("MSS IPC init\n");
+
+	if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
+		mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
+#else
+	INFO("MSS is not supported in this build\n");
+#endif
+}
+
+/* This function overruns the same function in marvell_bl31_setup.c */
+void bl31_plat_arch_setup(void)
+{
+	/* initiliaze the timer for mdelay/udelay functionality */
+	plat_delay_timer_init();
+
+	/* configure apn806 */
+	apn806_init();
+
+	/* In marvell_bl31_plat_arch_setup, el3 mmu is configured.
+	 * el3 mmu configuration MUST be called after apn806_init, if not,
+	 * this will cause an hang in init_rfu
+	 * (after setting the IO windows GCR values).
+	 */
+	marvell_bl31_plat_arch_setup();
+
+	/* configure cp110 for CP0*/
+	cp110_init(0);
+
+	/* initialize MCI & CP1 */
+	if (CP_COUNT == 2 && mci_initialize(0))
+		cp110_init(1);
+
+	/* Should be called only after setting IOB windows */
+	marvell_bl31_mpp_init();
+
+	/* initialize IPC between MSS and ATF */
+	marvell_bl31_mss_init();
+}
diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c
new file mode 100644
index 00000000..7f55ab4a
--- /dev/null
+++ b/plat/marvell/a8k/common/plat_ble_setup.c
@@ -0,0 +1,406 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_marvell.h>
+#include <plat_config.h>
+#include <plat_def.h>
+#include <debug.h>
+#include <sys_info.h>
+#include <dram_if.h>
+#include <ccu.h>
+#include <rfu.h>
+#include <apn806_setup.h>
+#include <cp110_setup.h>
+
+/* Register for skip image use */
+#define SCRATCH_PAD_REG2		0xF06F00A8
+#define SCRATCH_PAD_SKIP_VAL		0x01
+#define NUM_OF_GPIO_PER_REG 32
+
+/* CCU windows configuration defines */
+#define CCU_CFG_IO_WIN_NUM	(3)
+#define CCU_CFG_WIN_REGS_NUM	(4) /* CR + SCR + ALR + AHR */
+#define CCU_WIN_TARGET_OFFSET	(8)
+#define CCU_WIN_TARGET_MASK	(0xf)
+#define CCU_WIN_ADDR_SHIFT	(20)
+#define CCU_WIN_ADDR_OFFSET	(4)
+#define CCU_WIN_ADDR_MASK	(0xFFFFFFF)
+#define CCU_WIN_CR_OFFSET(w)	(0x0 + (w)*0x10)
+#define CCU_WIN_SCR_OFFSET(w)	(0x4 + (w)*0x10)
+#define CCU_WIN_ALR_OFFSET(w)	(0x8 + (w)*0x10)
+#define CCU_WIN_AHR_OFFSET(w)	(0xC + (w)*0x10)
+#define CCU_WIN_GCR_OFFSET	(0xD0)
+
+/* IO windows configuration */
+#define IOW_CFG_IO_WIN_NUM_ST	(2)
+#define IOW_CFG_IO_WIN_NUM_END	(IOW_CFG_IO_WIN_NUM_ST + CP_COUNT - 1)
+#define IOW_GCR_OFFSET		(0x70)
+#define IOW_WIN_ALR_OFFSET(w)	(0x10 + 0x10*(w))
+
+#define MMAP_SAVE_AND_CONFIG	0
+#define MMAP_RESTORE_SAVED	1
+
+/* SAR clock settings */
+#define MVEBU_AP_GEN_MGMT_BASE		(MVEBU_RFU_BASE + 0x8000)
+#define MVEBU_AP_SAR_REG_BASE(r)	(MVEBU_AP_GEN_MGMT_BASE + 0x200 +\
+								((r) << 2))
+
+#define FREQ_MODE_AP_SAR_REG_NUM	(0)
+#define SAR_CLOCK_FREQ_MODE_OFFSET	(0)
+#define SAR_CLOCK_FREQ_MODE_MASK	(0x1f << SAR_CLOCK_FREQ_MODE_OFFSET)
+
+#define AVS_EN_CTRL_REG			(MVEBU_AP_GEN_MGMT_BASE + 0x130)
+#define AVS_ENABLE_OFFSET		(0)
+#define AVS_SOFT_RESET_OFFSET		(2)
+#define AVS_LOW_VDD_LIMIT_OFFSET	(4)
+#define AVS_HIGH_VDD_LIMIT_OFFSET	(12)
+#define AVS_TARGET_DELTA_OFFSET		(21)
+/* VDD limit is 0.9V for A70x0 @ CPU frequency < 1600MHz */
+#define AVS_A7K_LOW_CLK_VALUE		((0x80 << AVS_TARGET_DELTA_OFFSET) | \
+					 (0x1A << AVS_HIGH_VDD_LIMIT_OFFSET) | \
+					 (0x1A << AVS_LOW_VDD_LIMIT_OFFSET) | \
+					 (0x1 << AVS_SOFT_RESET_OFFSET) | \
+					 (0x1 << AVS_ENABLE_OFFSET))
+/* VDD limit is 1.0V for all A80x0 devices */
+#define AVS_A8K_CLK_VALUE		((0x80 << AVS_TARGET_DELTA_OFFSET) | \
+					 (0x24 << AVS_HIGH_VDD_LIMIT_OFFSET) | \
+					 (0x24 << AVS_LOW_VDD_LIMIT_OFFSET) | \
+					 (0x1 << AVS_SOFT_RESET_OFFSET) | \
+					 (0x1 << AVS_ENABLE_OFFSET))
+
+enum cpu_clock_freq_mode {
+	CPU_2000_DDR_1200_RCLK_1200 = 0x0,
+	CPU_2000_DDR_1050_RCLK_1050 = 0x1,
+	CPU_1600_DDR_800_RCLK_800   = 0x4,
+	CPU_1800_DDR_1200_RCLK_1200 = 0x6,
+	CPU_1800_DDR_1050_RCLK_1050 = 0x7,
+	CPU_1600_DDR_900_RCLK_900   = 0x0B,
+	CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
+	CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
+	CPU_1000_DDR_650_RCLK_650   = 0x13,
+	CPU_1300_DDR_800_RCLK_800   = 0x14,
+	CPU_1300_DDR_650_RCLK_650   = 0x17,
+	CPU_1200_DDR_800_RCLK_800   = 0x19,
+	CPU_1400_DDR_800_RCLK_800   = 0x1a,
+	CPU_600_DDR_800_RCLK_800    = 0x1B,
+	CPU_800_DDR_800_RCLK_800    = 0x1C,
+	CPU_1000_DDR_800_RCLK_800   = 0x1D,
+	CPU_DDR_RCLK_INVALID
+};
+
+/* Notify bootloader on DRAM setup */
+void pass_dram_sys_info(struct dram_config *cfg)
+{
+	set_info(DRAM_BUS_WIDTH, cfg->iface[0].bus_width);
+	set_info(DRAM_CS0_SIZE, cfg->iface[0].size_mbytes);
+	set_info(DRAM_CS0, 1);
+	set_info(DRAM_CS1, 0);
+	set_info(DRAM_CS2, 0);
+	set_info(DRAM_CS3, 0);
+}
+/******************************************************************************
+ * The routine allows to save the CCU and IO windows configuration during DRAM
+ * setup and restore them afterwards before exiting the BLE stage.
+ * Such window configuration is requred since not all default settings coming
+ * from the HW and the BootROM akkow access to periferals connected to
+ * all available CPn components.
+ * For instance, when the boot device is located on CP0, the IO window to CP1
+ * is not opened automatically by the HW and if the DRAM SPD is located on CP1
+ * i2c channel, it cannot be read at BLE stage.
+ * Therefore the DRAM init procedure have to provide access to all available
+ * CPn periferals during the BLE stage by setting the CCU IO window to all CPn
+ * addresses and by enabling the IO windows accordingly.
+ * Additionally this function configures the CCU GCR to DRAM, which allows
+ * usage or more than 4GB DRAM as it configured by the default CCU DRAM window.
+ *
+ * IN:
+ *	MMAP_SAVE_AND_CONFIG	- save the existing configuration and update it
+ *	MMAP_RESTORE_SAVED	- restore saved configuration
+ * OUT:
+ *	NONE
+ ****************************************************************************
+ */
+static void ble_plat_mmap_config(int restore)
+{
+	static uint32_t ccu_win_regs[CCU_CFG_WIN_REGS_NUM];
+	static uint32_t io_win_regs[CP_COUNT];
+	static uint32_t ccu_gcr, iow_gcr;
+	uintptr_t ccu_base = MVEBU_CCU_BASE;
+	uintptr_t iow_base = MVEBU_RFU_BASE;
+	uint32_t reg_val, win_num;
+
+	if (restore == MMAP_RESTORE_SAVED) {
+		/* Restore all orig. settings that were modified by BLE stage */
+		/* Restore CCU */
+		mmio_write_32(ccu_base + CCU_WIN_CR_OFFSET(CCU_CFG_IO_WIN_NUM),
+			      ccu_win_regs[0]);
+		mmio_write_32(ccu_base + CCU_WIN_SCR_OFFSET(CCU_CFG_IO_WIN_NUM),
+			      ccu_win_regs[1]);
+		mmio_write_32(ccu_base + CCU_WIN_ALR_OFFSET(CCU_CFG_IO_WIN_NUM),
+			      ccu_win_regs[2]);
+		mmio_write_32(ccu_base + CCU_WIN_AHR_OFFSET(CCU_CFG_IO_WIN_NUM),
+			      ccu_win_regs[3]);
+		mmio_write_32(ccu_base + CCU_WIN_GCR_OFFSET, ccu_gcr);
+		/* Restore IO Windows */
+		for (win_num = IOW_CFG_IO_WIN_NUM_ST;
+		     win_num < IOW_CFG_IO_WIN_NUM_END; win_num++)
+			mmio_write_32(iow_base + IOW_WIN_ALR_OFFSET(win_num),
+				      io_win_regs[win_num -
+				      IOW_CFG_IO_WIN_NUM_ST]);
+		mmio_write_32(iow_base + IOW_GCR_OFFSET, iow_gcr);
+		return;
+	} else {
+		/* Store original values */
+		/* Save CCU */
+		ccu_win_regs[0] = mmio_read_32(ccu_base +
+					CCU_WIN_CR_OFFSET(CCU_CFG_IO_WIN_NUM));
+		ccu_win_regs[1] = mmio_read_32(ccu_base +
+					CCU_WIN_SCR_OFFSET(CCU_CFG_IO_WIN_NUM));
+		ccu_win_regs[2] = mmio_read_32(ccu_base +
+					CCU_WIN_ALR_OFFSET(CCU_CFG_IO_WIN_NUM));
+		ccu_win_regs[3] = mmio_read_32(ccu_base +
+					CCU_WIN_AHR_OFFSET(CCU_CFG_IO_WIN_NUM));
+		ccu_gcr = mmio_read_32(ccu_base + CCU_WIN_GCR_OFFSET);
+		/* Save IO Windows */
+		for (win_num = IOW_CFG_IO_WIN_NUM_ST;
+		     win_num < IOW_CFG_IO_WIN_NUM_END; win_num++)
+			io_win_regs[win_num - IOW_CFG_IO_WIN_NUM_ST] =
+				mmio_read_32(iow_base +
+					     IOW_WIN_ALR_OFFSET(win_num));
+		iow_gcr = mmio_read_32(iow_base + IOW_GCR_OFFSET);
+	}
+
+	/* The configuration saved, now all the changes can be done */
+	/* Set the default CCU target ID to DRAM 0 */
+	reg_val = ccu_gcr & ~(CCU_WIN_TARGET_MASK << CCU_WIN_TARGET_OFFSET);
+	reg_val |= (DRAM_0_TID & CCU_WIN_TARGET_MASK) << CCU_WIN_TARGET_OFFSET;
+	mmio_write_32(ccu_base + CCU_WIN_GCR_OFFSET, reg_val);
+
+	/* Set CCU IO window for covering all available CP addresses */
+	/* Set the CCU IO window Low Address to the start of CP0 region */
+	mmio_write_32(ccu_base + CCU_WIN_CR_OFFSET(CCU_CFG_IO_WIN_NUM), 0);
+	reg_val = (MVEBU_CP_REGS_BASE(0) >> CCU_WIN_ADDR_SHIFT)
+		  << CCU_WIN_ADDR_OFFSET;
+	mmio_write_32(ccu_base +
+		      CCU_WIN_ALR_OFFSET(CCU_CFG_IO_WIN_NUM), reg_val);
+
+	/*
+	 * Set the CCU IO window High Address to the end of
+	 * CPn region (n = CP_COUNT)
+	 */
+	reg_val = (MVEBU_CP_REGS_BASE(CP_COUNT - 1) >> CCU_WIN_ADDR_SHIFT)
+		   << CCU_WIN_ADDR_OFFSET;
+	reg_val |= 0xF << CCU_WIN_ADDR_OFFSET;
+	mmio_write_32(ccu_base + CCU_WIN_AHR_OFFSET(CCU_CFG_IO_WIN_NUM),
+		      reg_val);
+
+	/* Set the CCU IO window Control target to IO and enable this window */
+	reg_val = (IO_0_TID << CCU_WIN_TARGET_OFFSET) | 0x1;
+	mmio_write_32(ccu_base + CCU_WIN_CR_OFFSET(CCU_CFG_IO_WIN_NUM),
+		      reg_val);
+
+	/* Set IO windows GCR (IO decode) to PIDI as a default (CP0) */
+	mmio_write_32(iow_base + IOW_GCR_OFFSET, PIDI_TID);
+
+	/*
+	 * Optionally enable IO windows for CP1, CP2, CP3 (depends on CP_COUNT).
+	 * All the rest of windows default settings (ALR, AHR, CR) are already
+	 * set by the HW
+	 */
+	for (win_num = IOW_CFG_IO_WIN_NUM_ST;
+	     win_num < IOW_CFG_IO_WIN_NUM_END; win_num++) {
+		reg_val = mmio_read_32(iow_base + IOW_WIN_ALR_OFFSET(win_num));
+		reg_val |= 0x1;
+		mmio_write_32(iow_base + IOW_WIN_ALR_OFFSET(win_num), reg_val);
+	}
+}
+
+/******************************************************************************
+ * Setup Adaptive Voltage Switching - this is required for some platforms
+ *****************************************************************************/
+static void ble_plat_avs_config(void)
+{
+	uint32_t reg_val, device_id;
+
+	/* Do nothing on A0 revision SoCs */
+	if (apn806_rev_id_get() == APN806_REV_ID_A0)
+		return;
+
+	/* Check which SoC is running and act accordingly */
+	device_id = cp110_device_id_get();
+	switch (device_id) {
+	case MVEBU_80X0_DEV_ID:
+		/* Set the new AVS value - fix the default one on A80x0 */
+		mmio_write_32(AVS_EN_CTRL_REG, AVS_A8K_CLK_VALUE);
+		break;
+
+	case MVEBU_70X0_DEV_ID:
+		/* Only fix AVS for CPU clocks lower than 1600MHz on A70x0 */
+		reg_val = mmio_read_32(MVEBU_AP_SAR_REG_BASE(
+						FREQ_MODE_AP_SAR_REG_NUM));
+		reg_val &= SAR_CLOCK_FREQ_MODE_MASK;
+		reg_val >>= SAR_CLOCK_FREQ_MODE_OFFSET;
+		if ((reg_val > CPU_1600_DDR_900_RCLK_900_2) &&
+		    (reg_val < CPU_DDR_RCLK_INVALID))
+			mmio_write_32(AVS_EN_CTRL_REG, AVS_A7K_LOW_CLK_VALUE);
+		break;
+
+	default:
+		ERROR("Unsupported Device ID 0x%x\n", device_id);
+	}
+}
+
+static int ble_skip_image_i2c(struct skip_image *skip_im)
+{
+	ERROR("skipping image using i2c is not supported\n");
+	/* not supported */
+	return 0;
+}
+
+static int ble_skip_image_other(struct skip_image *skip_im)
+{
+	ERROR("implementation missing for skip image request\n");
+	/* not supported, make your own implementation */
+	return 0;
+}
+
+static int ble_skip_image_gpio(struct skip_image *skip_im)
+{
+	unsigned int val;
+	unsigned int mpp_address = 0;
+	unsigned int offset = 0;
+
+	switch (skip_im->info.test.cp_ap) {
+	case(CP):
+		mpp_address = MVEBU_CP_GPIO_DATA_IN(skip_im->info.test.cp_index,
+						    skip_im->info.gpio.num);
+		if (skip_im->info.gpio.num > NUM_OF_GPIO_PER_REG)
+			offset = skip_im->info.gpio.num - NUM_OF_GPIO_PER_REG;
+		else
+			offset = skip_im->info.gpio.num;
+		break;
+	case(AP):
+		mpp_address = MVEBU_AP_GPIO_DATA_IN;
+		offset = skip_im->info.gpio.num;
+		break;
+	}
+
+	val = mmio_read_32(mpp_address);
+	val &= (1 << offset);
+	if ((!val && skip_im->info.gpio.button_state == HIGH) ||
+	    (val && skip_im->info.gpio.button_state == LOW)) {
+		mmio_write_32(SCRATCH_PAD_REG2, SCRATCH_PAD_SKIP_VAL);
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * This function checks if there's a skip image request:
+ * return values:
+ * 1: (true) images request been made.
+ * 0: (false) no image request been made.
+ */
+static int  ble_skip_current_image(void)
+{
+	struct skip_image *skip_im;
+
+	/*fetching skip image info*/
+	skip_im = (struct skip_image *)plat_get_skip_image_data();
+
+	if (skip_im == NULL)
+		return 0;
+
+	/* check if skipping image request has already been made */
+	if (mmio_read_32(SCRATCH_PAD_REG2) == SCRATCH_PAD_SKIP_VAL)
+		return 0;
+
+	switch (skip_im->detection_method) {
+	case GPIO:
+		return ble_skip_image_gpio(skip_im);
+	case I2C:
+		return ble_skip_image_i2c(skip_im);
+	case USER_DEFINED:
+		return ble_skip_image_other(skip_im);
+	}
+
+	return 0;
+}
+
+int ble_plat_setup(int *skip)
+{
+	int ret;
+	struct dram_config *cfg;
+
+	/*
+	 * Save the current CCU configuration and make required changes:
+	 * - Allow access to DRAM larger than 4GB
+	 * - Open memory access to all CPn periferals
+	 */
+	ble_plat_mmap_config(MMAP_SAVE_AND_CONFIG);
+
+	/* Check if there's a skip request to bootRom recovey Image */
+	if (ble_skip_current_image()) {
+		/* close memory access to all CPn periferals. */
+		ble_plat_mmap_config(MMAP_RESTORE_SAVED);
+		*skip = 1;
+		return 0;
+	}
+
+#if PCI_EP_SUPPORT
+	/* Do basic CP-110 setups */
+	cp110_ble_init(0);
+
+	/* Enable PCIe in end point mode */
+	ble_plat_pcie_ep_setup();
+#endif
+
+	/* Setup AVS */
+	ble_plat_avs_config();
+
+	/* Get dram data from platform */
+	cfg = (struct dram_config *)plat_get_dram_data();
+
+	/* Kick it in */
+	ret = dram_init(cfg);
+
+	/* Restore the original CCU configuration before exit from BLE */
+	ble_plat_mmap_config(MMAP_RESTORE_SAVED);
+
+	/* Pass DRAM information to bootloader */
+	pass_dram_sys_info(cfg);
+
+	return ret;
+}
diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
new file mode 100644
index 00000000..7e5a8d16
--- /dev/null
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -0,0 +1,386 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <plat_marvell.h>
+#include <gicv2.h>
+#include <mmio.h>
+#include <debug.h>
+
+#ifdef SCP_IMAGE
+#include <bakery_lock.h>
+#include <platform.h>
+#include <mss_pm_ipc.h>
+#include <plat_pm_trace.h>
+#endif
+
+#define MVEBU_PRIVATE_UID_REG		0x30
+#define MVEBU_RFU_GLOBL_SW_RST		0x84
+#define MVEBU_CCU_RVBAR(i)		(MVEBU_REGS_BASE + 0x640 + (i * 4))
+#define MVEBU_CCU_CPU_UN_RESET		(MVEBU_REGS_BASE + 0x650)
+
+#define MPIDR_CPU_GET(mpidr)		((mpidr) & MPIDR_CPU_MASK)
+#define MPIDR_CLUSTER_GET(mpidr)	MPIDR_AFFLVL1_VAL((mpidr))
+
+#ifdef SCP_IMAGE
+/* this lock synchronize AP multiple cores execution with MSS */
+DEFINE_BAKERY_LOCK(pm_sys_lock);
+/*
+ * this lock ensures core flow execution
+ * "suspend->suspend finish", and "off-> on finish"
+ */
+DEFINE_BAKERY_LOCK(pm_core_lock[PLATFORM_CORE_COUNT]);
+#endif
+
+int plat_marvell_cpu_on(u_register_t mpidr)
+{
+	int cpu_id;
+	int cluster;
+
+	/* Set barierr */
+	__asm__ volatile("dsb     sy");
+
+	/* Get cpu number - use CPU ID */
+	cpu_id =  MPIDR_CPU_GET(mpidr);
+
+	/* Get cluster number - use affinity level 1 */
+	cluster = MPIDR_CLUSTER_GET(mpidr);
+
+	/* Set CPU private UID */
+	mmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4);
+
+	/* Set the cpu start address to BL1 entry point (align to 0x10000) */
+	mmio_write_32(MVEBU_CCU_RVBAR(0) + (cpu_id << 2),
+		      PLAT_MARVELL_CPU_ENTRY_ADDR >> 16);
+
+	/* Get the cpu out of reset */
+	mmio_write_32(MVEBU_CCU_CPU_UN_RESET + (cpu_id << 2), 0x10001);
+
+	return 0;
+}
+
+void plat_marvell_system_reset(void)
+{
+	mmio_write_32(MVEBU_RFU_BASE + MVEBU_RFU_GLOBL_SW_RST, 0x0);
+}
+
+/*******************************************************************************
+ * A8K handler called to check the validity of the power state
+ * parameter.
+ ******************************************************************************/
+int a8k_validate_power_state(unsigned int power_state,
+			    psci_power_state_t *req_state)
+{
+	int pstate = psci_get_pstate_type(power_state);
+	int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+	int i;
+
+	if (pwr_lvl > PLAT_MAX_PWR_LVL)
+		return PSCI_E_INVALID_PARAMS;
+
+	/* Sanity check the requested state */
+	if (pstate == PSTATE_TYPE_STANDBY) {
+		/*
+		 * It's possible to enter standby only on power level 0
+		 * Ignore any other power level.
+		 */
+		if (pwr_lvl != MARVELL_PWR_LVL0)
+			return PSCI_E_INVALID_PARAMS;
+
+		req_state->pwr_domain_state[MARVELL_PWR_LVL0] =
+					MARVELL_LOCAL_STATE_RET;
+	} else {
+		for (i = MARVELL_PWR_LVL0; i <= pwr_lvl; i++)
+			req_state->pwr_domain_state[i] =
+					MARVELL_LOCAL_STATE_OFF;
+	}
+
+	/*
+	 * We expect the 'state id' to be zero.
+	 */
+	if (psci_get_pstate_id(power_state))
+		return PSCI_E_INVALID_PARAMS;
+
+	return PSCI_E_SUCCESS;
+}
+
+/*******************************************************************************
+ * A8K handler called when a CPU is about to enter standby.
+ ******************************************************************************/
+void a8k_cpu_standby(plat_local_state_t cpu_state)
+{
+	ERROR("a8k_cpu_standby needs to be implemented\n");
+	panic();
+}
+
+/*******************************************************************************
+ * A8K handler called when a power domain is about to be turned on. The
+ * mpidr determines the CPU to be turned on.
+ ******************************************************************************/
+int a8k_pwr_domain_on(u_register_t mpidr)
+{
+#ifdef SCP_IMAGE
+	unsigned int target = ((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2));
+
+	/*
+	 * pm system synchronization - used to synchronize
+	 * multiple core access to MSS
+	 */
+	bakery_lock_get(&pm_sys_lock);
+
+	/* trace message */
+	PM_TRACE((TRACE_PWR_DOMAIN_ON | target), plat_my_core_pos());
+
+	/* trigger IPC message to MSS */
+	mss_pm_ipc_on_msg_trigger(target);
+
+	/* verify command execution before continue to ATF generic code */
+	__asm__ volatile("dsb sy");
+	__asm__ volatile("isb");
+
+	/* pm system synchronization */
+	bakery_lock_release(&pm_sys_lock);
+#else
+	/* proprietary CPU ON exection flow */
+	plat_marvell_cpu_on(mpidr);
+#endif /* SCP_IMAGE */
+
+	return 0;
+}
+
+/*******************************************************************************
+ * A8K handler called to validate the entry point.
+ ******************************************************************************/
+int a8k_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+	return PSCI_E_SUCCESS;
+}
+
+/*******************************************************************************
+ * A8K handler called when a power domain is about to be turned off. The
+ * target_state encodes the power state that each level should transition to.
+ ******************************************************************************/
+void a8k_pwr_domain_off(const psci_power_state_t *target_state)
+{
+#ifdef SCP_IMAGE
+	unsigned int idx = plat_my_core_pos();
+
+	/* Prevent interrupts from spuriously waking up this cpu */
+	gicv2_cpuif_disable();
+
+	/*
+	 * pm system synchronization - used to synchronize
+	 * multiple core access to MSS
+	 */
+	bakery_lock_get(&pm_sys_lock);
+
+	/*
+	 * pm core flow synchronization - is used to protect
+	 * core execution flow, lock is
+	 * released in a8k_pwr_domain_on_finish
+	 */
+	bakery_lock_get(&pm_core_lock[idx]);
+
+	/* trace message */
+	PM_TRACE(TRACE_PWR_DOMAIN_OFF, idx);
+
+	/* send CPU OFF IPC Message to MSS */
+	mss_pm_ipc_msg_send(idx, target_state);
+
+	/* verify command execution before triggering MSS execution */
+	__asm__ volatile("isb");
+
+	/* Trigger IPC message to MSS */
+	mss_pm_ipc_off_msg_trigger(idx);
+
+	/* verify command execution before return to ATF generic code */
+	__asm__ volatile("dsb sy");
+	__asm__ volatile("isb");
+
+	/* pm system synchronization */
+	bakery_lock_release(&pm_sys_lock);
+#else
+	INFO("a8k_pwr_domain_off is not supported without SCP\n");
+	return;
+#endif /* SCP_IMAGE */
+}
+
+/*******************************************************************************
+ * A8K handler called when a power domain is about to be suspended. The
+ * target_state encodes the power state that each level should transition to.
+ ******************************************************************************/
+void a8k_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+#ifdef SCP_IMAGE
+	unsigned int idx = plat_my_core_pos();
+
+	/* Prevent interrupts from spuriously waking up this cpu */
+	gicv2_cpuif_disable();
+
+	/*
+	 * pm system synchronization -used to synchronize
+	 * multiple core access to MSS
+	 */
+	bakery_lock_get(&pm_sys_lock);
+
+	/*
+	 * pm core flow synchronization - is used to protect
+	 * core execution flow, lock is
+	 * released in a8k_pwr_domain_suspend_finish
+	 */
+	bakery_lock_get(&pm_core_lock[idx]);
+
+	/* trace message */
+	PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND, idx);
+
+	/* send CPU Suspend IPC Message to MSS */
+	mss_pm_ipc_msg_send(idx, target_state);
+
+	/* verify command execution before triggering MSS execution */
+	__asm__ volatile("isb");
+
+	/* Trigger IPC message to MSS */
+	mss_pm_ipc_suspend_msg_trigger(idx);
+
+	/* verify command execution before return to ATF generic code */
+	__asm__ volatile("dsb sy");
+	__asm__ volatile("isb");
+
+	/* pm system synchronization */
+	bakery_lock_release(&pm_sys_lock);
+#else
+	INFO("a8k_pwr_domain_suspend is not supported without SCP\n");
+	return;
+#endif /* SCP_IMAGE */
+}
+
+/*******************************************************************************
+ * A8K handler called when a power domain has just been powered on after
+ * being turned off earlier. The target_state encodes the low power state that
+ * each level has woken up from.
+ ******************************************************************************/
+void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+#ifdef SCP_IMAGE
+	unsigned int idx = plat_my_core_pos();
+#endif
+
+	/* arch specific configuration */
+	psci_arch_init();
+
+	/* Interrupt initialization */
+	gicv2_pcpu_distif_init();
+	gicv2_cpuif_enable();
+
+#ifdef SCP_IMAGE
+	/*
+	 * pm core flow synchronization - is used to protect
+	 * core execution flow, release lock
+	 * taken in a8k_pwr_domain_off
+	 */
+	bakery_lock_release(&pm_core_lock[idx]);
+
+	/* trace message */
+	PM_TRACE(TRACE_PWR_DOMAIN_ON_FINISH, idx);
+#endif /* SCP_IMAGE */
+}
+
+/*******************************************************************************
+ * A8K handler called when a power domain has just been powered on after
+ * having been suspended earlier. The target_state encodes the low power state
+ * that each level has woken up from.
+ * TODO: At the moment we reuse the on finisher and reinitialize the secure
+ * context. Need to implement a separate suspend finisher.
+ ******************************************************************************/
+void a8k_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
+{
+#ifdef SCP_IMAGE
+	unsigned int idx = plat_my_core_pos();
+
+	/* arch specific configuration */
+	psci_arch_init();
+
+	/* Interrupt initialization */
+	gicv2_cpuif_enable();
+
+	/*
+	 * pm core flow synchronization - is used to protect
+	 * core execution flow, release lock
+	 * taken in a8k_pwr_domain_suspend
+	 */
+	bakery_lock_release(&pm_core_lock[idx]);
+
+	/* trace message */
+	PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND_FINISH, idx);
+#else
+	INFO("a8k_pwr_domain_on_finish is not supported without SCP\n");
+	return;
+#endif /* SCP_IMAGE */
+}
+
+/*******************************************************************************
+ * A8K handlers to shutdown/reboot the system
+ ******************************************************************************/
+static void __dead2 a8k_system_off(void)
+{
+	ERROR("a8k_system_off needs to be implemented\n");
+	panic();
+	wfi();
+	ERROR("A8K System Off: operation not handled.\n");
+	panic();
+}
+
+static void __dead2 a8k_system_reset(void)
+{
+	plat_marvell_system_reset();
+
+	/* we shouldn't get to this point */
+	panic();
+}
+
+/*******************************************************************************
+ * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+ * platform layer will take care of registering the handlers with PSCI.
+ ******************************************************************************/
+const plat_psci_ops_t plat_arm_psci_pm_ops = {
+	.cpu_standby = a8k_cpu_standby,
+	.pwr_domain_on = a8k_pwr_domain_on,
+	.pwr_domain_off = a8k_pwr_domain_off,
+	.pwr_domain_suspend = a8k_pwr_domain_suspend,
+	.pwr_domain_on_finish = a8k_pwr_domain_on_finish,
+	.pwr_domain_suspend_finish = a8k_pwr_domain_suspend_finish,
+	.system_off = a8k_system_off,
+	.system_reset = a8k_system_reset,
+	.validate_power_state = a8k_validate_power_state,
+	.validate_ns_entrypoint = a8k_validate_ns_entrypoint
+};
diff --git a/plat/marvell/a8k/common/plat_pm_trace.c b/plat/marvell/a8k/common/plat_pm_trace.c
new file mode 100644
index 00000000..b801ee3c
--- /dev/null
+++ b/plat/marvell/a8k/common/plat_pm_trace.c
@@ -0,0 +1,117 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2016 Marvell International Ltd.
+ * ***************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Marvell nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************
+ */
+
+#include <mmio.h>
+#include <platform.h>
+#include <plat_pm_trace.h>
+#include <mss_mem.h>
+
+#ifdef PM_TRACE_ENABLE
+
+/* core trace APIs */
+core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
+	pm_core_0_trace,
+	pm_core_1_trace,
+	pm_core_2_trace,
+	pm_core_3_trace};
+
+/*******************************************************************************
+ * pm_core0_trace
+ * pm_core1_trace
+ * pm_core2_trace
+ * pm_core_3trace
+ *
+ * This functions set trace info into core cyclic trace queue in MSS SRAM
+ * memory space
+ ******************************************************************************/
+void pm_core_0_trace(unsigned int trace)
+{
+	unsigned int current_position_core_0 =
+			mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE);
+	mmio_write_32((AP_MSS_ATF_CORE_0_INFO_BASE  +
+		     (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     mmio_read_32(AP_MSS_TIMER_BASE));
+	mmio_write_32((AP_MSS_ATF_CORE_0_INFO_TRACE +
+		     (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     trace);
+	mmio_write_32(AP_MSS_ATF_CORE_0_CTRL_BASE,
+		     ((current_position_core_0 + 1) &
+		     AP_MSS_ATF_TRACE_SIZE_MASK));
+}
+
+void pm_core_1_trace(unsigned int trace)
+{
+	unsigned int current_position_core_1 =
+			mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE);
+	mmio_write_32((AP_MSS_ATF_CORE_1_INFO_BASE +
+		     (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     mmio_read_32(AP_MSS_TIMER_BASE));
+	mmio_write_32((AP_MSS_ATF_CORE_1_INFO_TRACE +
+		     (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     trace);
+	mmio_write_32(AP_MSS_ATF_CORE_1_CTRL_BASE,
+		     ((current_position_core_1 + 1) &
+		     AP_MSS_ATF_TRACE_SIZE_MASK));
+}
+
+void pm_core_2_trace(unsigned int trace)
+{
+	unsigned int current_position_core_2 =
+			mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE);
+	mmio_write_32((AP_MSS_ATF_CORE_2_INFO_BASE +
+		     (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     mmio_read_32(AP_MSS_TIMER_BASE));
+	mmio_write_32((AP_MSS_ATF_CORE_2_INFO_TRACE +
+		     (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     trace);
+	mmio_write_32(AP_MSS_ATF_CORE_2_CTRL_BASE,
+		     ((current_position_core_2 + 1) &
+		     AP_MSS_ATF_TRACE_SIZE_MASK));
+}
+
+void pm_core_3_trace(unsigned int trace)
+{
+	unsigned int current_position_core_3 =
+			mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE);
+	mmio_write_32((AP_MSS_ATF_CORE_3_INFO_BASE +
+		     (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     mmio_read_32(AP_MSS_TIMER_BASE));
+	mmio_write_32((AP_MSS_ATF_CORE_3_INFO_TRACE +
+		     (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
+		     trace);
+	mmio_write_32(AP_MSS_ATF_CORE_3_CTRL_BASE,
+		     ((current_position_core_3 + 1) &
+		     AP_MSS_ATF_TRACE_SIZE_MASK));
+}
+#endif /* PM_TRACE_ENABLE */