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| author | Soby Mathew <soby.mathew@arm.com> | 2016-05-17 14:01:32 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2016-06-03 10:50:52 +0100 |
| commit | 8cd16e6b5b4a83a2cf704362b9acb1c2eea1417e (patch) | |
| tree | b514a455aa4ab76bb08f0313c170b6c160448ac0 /Makefile | |
| parent | e141aa0357fd4977ba874f4f86874e2cadc73498 (diff) | |
Build option to include AArch32 registers in cpu context
The system registers that are saved and restored in CPU context include
AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ,
DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an
AArch64-only (i.e. on hardware that does not implement AArch32, or at
least not at EL1 and higher ELs) platform leads to an exception. This patch
introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to
include these AArch32 systems registers in the cpu context or not. By default
this build option is set to 1 to ensure compatibility. AArch64-only platforms
must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to
verify this.
Fixes ARM-software/tf-issues#386
Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -62,6 +62,9 @@ NS_TIMER_SWITCH := 0 RESET_TO_BL31 := 0 # Include FP registers in cpu context CTX_INCLUDE_FPREGS := 0 +# Build flag to include AArch32 registers in cpu context save and restore +# during world switch. This flag must be set to 0 for AArch64-only platforms. +CTX_INCLUDE_AARCH32_REGS := 1 # Determine the version of ARM GIC architecture to use for interrupt management # in EL3. The platform port can change this value if needed. ARM_GIC_ARCH := 2 @@ -392,6 +395,7 @@ $(eval $(call assert_boolean,DEBUG)) $(eval $(call assert_boolean,NS_TIMER_SWITCH)) $(eval $(call assert_boolean,RESET_TO_BL31)) $(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) +$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call assert_boolean,ASM_ASSERTION)) $(eval $(call assert_boolean,USE_COHERENT_MEM)) $(eval $(call assert_boolean,DISABLE_PEDANTIC)) @@ -419,6 +423,7 @@ $(eval $(call add_define,SPD_${SPD})) $(eval $(call add_define,NS_TIMER_SWITCH)) $(eval $(call add_define,RESET_TO_BL31)) $(eval $(call add_define,CTX_INCLUDE_FPREGS)) +$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call add_define,ARM_GIC_ARCH)) $(eval $(call add_define,ARM_CCI_PRODUCT_ID)) $(eval $(call add_define,ASM_ASSERTION)) |