diff options
| author | Konstantin Porotchkin <kostap@marvell.com> | 2018-01-02 11:41:51 +0200 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2018-01-16 19:08:17 +0200 |
| commit | 80dd6eb15083bf4672011cd78e828848d2c19fed (patch) | |
| tree | 5c1fc5cd68feca15b8bb1c9baa41908ba6b41b2e /Makefile | |
| parent | 8d43cc497cda4bfd2802163912ece9cf217563c0 (diff) | |
a8k-p: Introduce new address translation scheme for Armada8K-p family
Introduce the address decoding scheme v5 that supports up to
4 interconnected APs with up to 4 CPs attached to every AP.
Physical memory map:
0x0000_0000_0000 - 0x0080_FFFF_FFFF - DRAM - 512GB + 4GB
0x0081_0000_0000 - 0x009D_FFFF_FFFF - AP0 IO - 116GB
0x009E_0000_0000 - 0x00BA_FFFF_FFFF - AP1 IO - 116GB
0x00BB_0000_0000 - 0x00D7_FFFF_FFFF - AP2 IO - 116GB
0x00D8_0000_0000 - 0x00F4_FFFF_FFFF - AP3 IO - 116GB
The DRAM address space is mapped differentrly for 1 or 2 interconnected
APs and 3 or 4 APs.
For up to 2 APs, 128GB is allocated for each memory controller channel:
0x0000_0000_0000 - 0x0040_3FFF_FFFF - AP0 DRAM
0x0040_4000_0000 - 0x0080_7FFF_FFFF - AP1 DRAM
For 3 to 4 APs, 64GB is allocated for each AP memory controller channel:
0x0000_0000_0000 - 0x0020_3FFF_FFFF - AP0 DRAM
0x0020_4000_0000 - 0x0040_7FFF_FFFF - AP1 DRAM
0x0040_8000_0000 - 0x0060_BFFF_FFFF - AP2 DRAM
0x0060_C000_0000 - 0x0080_FFFF_FFFF - AP3 DRAM
Extra 1GB per AP DRAM space is reserved for the control registers remapping.
Each AP IO address space includes 28GB region per every CP and single 4GB
region for direct-mapped SPI and/or STM.
For example, the following map is used for AP0 IO:
0x0081_0000_0000 - 0x0087_FFFF_FFFF - CP0
0x0088_0000_0000 - 0x008E_FFFF_FFFF - CP1
0x008F_0000_0000 - 0x0095_FFFF_FFFF - CP2
0x0096_0000_0000 - 0x009C_FFFF_FFFF - CP3
0x009D_0000_0000 - 0x009D_FFFF_FFFF - SPI-direct and STM
Every CP address space is divided into 4 regions:
4GB for the control registers access
8GB for PCI0
8GB for PCI1
8GB for PCI2
Change-Id: I6918e9fb8165c683ec6471f461b7b8bd714bef64
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/48369
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 9 |
1 files changed, 9 insertions, 0 deletions
@@ -56,6 +56,14 @@ ifeq ($(PLAT),$(filter $(PLAT),a80x0_ocp)) PCI_EP_SUPPORT := 1 endif +ifeq ($(PLAT),$(filter $(PLAT),a8xxy)) +ifeq (${PALLADIUM},1) +CP_NUM := 0 +else +CP_NUM := 2 +endif +endif + # Marvell images BOOT_IMAGE := boot-image.bin BOOT_ENC_IMAGE := boot-image-enc.bin @@ -637,6 +645,7 @@ endif $(eval $(call add_define,PALLADIUM)) $(eval $(call add_define,LLC_DISABLE)) $(eval $(call add_define,PCI_EP_SUPPORT)) +$(eval $(call add_define,CP_NUM)) ################################################################################ # Include BL specific makefiles |