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| author | Achin Gupta <achin.gupta@arm.com> | 2015-09-22 16:34:52 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2015-09-22 16:34:52 +0100 |
| commit | a6ef882c0e29f9459a927106fab36ea31587bf9a (patch) | |
| tree | 591ca75894d56b50f1f36547af388baf62153f8f /bl31 | |
| parent | 7dc28e9c6e577c5151d0a6df7165f7d21f509f5f (diff) | |
| parent | fd6007de64fd7e16f6d96972643434c04a77f1c6 (diff) | |
Merge pull request #394 from achingupta/ag/ccn_driver
Support for ARM CoreLink CCN interconnects
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 17 | ||||
| -rw-r--r-- | bl31/bl31.ld.S | 11 | ||||
| -rw-r--r-- | bl31/bl31_main.c | 3 |
3 files changed, 28 insertions, 3 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 5ba0f9cc..636b1d28 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -113,5 +113,22 @@ func bl31_entrypoint */ bl bl31_main + /* ------------------------------------------------------------- + * Clean the .data & .bss sections to main memory. This ensures + * that any global data which was initialised by the primary CPU + * is visible to secondary CPUs before they enable their data + * caches and participate in coherency. + * ------------------------------------------------------------- + */ + adr x0, __DATA_START__ + adr x1, __DATA_END__ + sub x1, x1, x0 + bl clean_dcache_range + + adr x0, __BSS_START__ + adr x1, __BSS_END__ + sub x1, x1, x0 + bl clean_dcache_range + b el3_exit endfunc bl31_entrypoint diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 0639d817..72507911 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -81,6 +81,12 @@ SECTIONS ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + .data . : { __DATA_START__ = .; *(.data*) @@ -165,6 +171,11 @@ SECTIONS } >RAM #endif + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; __BL31_END__ = .; __BSS_SIZE__ = SIZEOF(.bss); diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index a1a37105..a244a5cc 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -87,9 +87,6 @@ void bl31_main(void) INFO("BL3-1: Initializing runtime services\n"); runtime_svc_init(); - /* Clean caches before re-entering normal world */ - dcsw_op_all(DCCSW); - /* * All the cold boot actions on the primary cpu are done. We now need to * decide which is the next image (BL32 or BL33) and how to execute it. |