plat: marvell: align the sources with mainline TF-A

Following the acception of Marvell platform support in the mainline
TF-A code, some changes triggered by the TF-A team review should be
ported back.
This patch introduces changes (mostly cosmetic) that sync between
the mainline and LSP code bases.
- Limit line length to 80 characters for passing through Linux checkpatch
- Make all comment blocks comply the Linux kernel coduing style
- Arrange all includes in alphabetical order
- Rename plat_config.h to armada_common.h (a8k_common in the mainline,
  but we should take into account next platform support as well)
- Rename plat_private.h to marvell_plat_priv.h
- Rename plat_def.h to mvebu_def.h

Change-Id: Idd542c8a7d4ff8d8fb67c3601410308be5aed8e5
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/58282
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

7 files changed, 80 insertions, 23 deletions

diff --git a/docs/marvell/build.txt b/docs/marvell/build.txt
index 300c09f3..5646bdd0 100644
--- a/docs/marvell/build.txt
+++ b/docs/marvell/build.txt
@@ -1,17 +1,17 @@
-ATF Build Instructions
+TF-A Build Instructions
 ======================
 
-This section describes how to compile the ARM Trusted Firmware (ATF) project for Marvell's platforms.
+This section describes how to compile the ARM Trusted Firmware (TF-A) project for Marvell's platforms.
 
 Build Instructions
 ------------------
 (1) Set the cross compiler::
 
-		> export CROSS_COMPILE=/path/to/toolchain/aarch64-marvell-linux-gnu-
+		> export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu-
 
 (2) Set path for FIP images:
 
-	Set U-Boot image path (relatively to ATF root or absolute path)::
+	Set U-Boot image path (relatively to TF-A root or absolute path)::
 
 		> export BL33=path/to/u-boot.bin
 
@@ -37,7 +37,7 @@ Build Instructions
 
 		> make distclean
 
-(5) Build ATF:
+(5) Build TF-A:
 
 	There are several build options:
 
@@ -46,14 +46,16 @@ Build Instructions
 	- LOG_LEVEL: defines the level of logging which will be purged to the default output port.
 
 		LOG_LEVEL_NONE		0
-		LOG_LEVEL_NOTICE	10
-		LOG_LEVEL_ERROR		20
+		LOG_LEVEL_ERROR		10
+		LOG_LEVEL_NOTICE	20
 		LOG_LEVEL_WARNING	30
 		LOG_LEVEL_INFO		40
 		LOG_LEVEL_VERBOSE	50
 
 	- USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the
-		BL memory map or not. It should be set to 0.
+		BL memory map or not.
+
+	- LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
 
 	- MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted.
 
@@ -67,7 +69,7 @@ Build Instructions
 		Usage example: MV_DDR_PATH=path/to/mv_ddr
 		The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr
 		sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
-		is neccesary for A37x0.
+		is necessary for A37x0.
 
 	- DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0.
 		Supported Options:
@@ -114,7 +116,7 @@ Build Instructions
 		suitable for a8xxY SoC, where "Y" is a number of connected CPs and "xx" is a number of CPU cores.
 		Valid values with CP_NUM is in a range of 0 to 8.
 		The CPs defined by this parameter are evenly distributed across interconnected APs that in turn
-		are dynamically detected. For instance, if the CP_NUM=6 and the ATF detects 2 interconnected
+		are dynamically detected. For instance, if the CP_NUM=6 and the TF-A detects 2 interconnected
 		APs, each AP assumed to have 3 attached CPs. With the same amount of APs and CP_NUM=3, the AP0
 		will have 2 CPs connected and AP1 - a just single CP.
 
@@ -143,26 +145,26 @@ Build Instructions
 
 Special Build Flags
 --------------------
-	- PALLADIUM: Enables building ATF for palladium target. This mainly involves changing the UART baud rate
+	- PALLADIUM: Enables building TF-A for palladium target. This mainly involves changing the UART baud rate
 		and the timer frequency to a lower values to match palladium's setup.
 	- PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build
 		atf. In order to build uart recovery image this operation should be disabled for a70x0 and a80x0
-                because of hardware limitation(boot from secondary image can interrrupt uart recovery process).
+                because of hardware limitation(boot from secondary image can interrupt uart recovery process).
 		This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file
 
-(for more information about build options, please refer to section 'Summary of build options' in  ATF user-guide:
+(for more information about build options, please refer to section 'Summary of build options' in  TF-A user-guide:
  https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/user-guide.md)
 
 
 Build output
 -------------
-Marvell's ATF compilation generates 7 files:
+Marvell's TF-A compilation generates 7 files:
 	- ble.bin		- BLe image
 	- bl1.bin		- BL1 image
 	- bl2.bin		- BL2 image
 	- bl31.bin		- BL31 image
 	- fip.bin		- FIP image (contains BL2, BL31 & BL33 (U-Boot) images)
-	- boot-image.bin	- ATF image (contains BL1 and FIP images)
+	- boot-image.bin	- TF-A image (contains BL1 and FIP images)
 	- flash-image.bin	- Image which contains boot-image.bin and SPL image; should be placed on the boot flash/device.
 
 
diff --git a/docs/marvell/misc/mvebu-a8k-addr-map.txt b/docs/marvell/misc/mvebu-a8k-addr-map.txt
new file mode 100644
index 00000000..586e8b73
--- /dev/null
+++ b/docs/marvell/misc/mvebu-a8k-addr-map.txt
@@ -0,0 +1,47 @@
+Address decoding flow and address translation units of Marvell Armada 8K SoC family
+
++--------------------------------------------------------------------------------------------------+
+|                                                              +-------------+    +--------------+ |
+|                                                              | Memory      +-----   DRAM CS    | |
+|+------------+ +-----------+ +-----------+                    | Controller  |    +--------------+ |
+||  AP DMA    | |           | |           |                    +-------------+                     |
+||  SD/eMMC   | | CA72 CPUs | |  AP MSS   |                    +-------------+                     |
+||  MCI-0/1   | |           | |           |                    | Memory      |                     |
+|+------+-----+ +--+--------+ +--------+--+  +------------+    | Controller  |     +-------------+ |
+|       |          |                   |     |            +----- Translaton  |     |AP           | |
+|       |          |                   |     |            |    +-------------+     |Configuration| |
+|       |          |                   +-----+            +-------------------------Space        | |
+|       |          | +-------------+         |  CCU       |                        +-------------+ |
+|       |          | | MMU         +---------+  Windows   |   +-----------+        +-------------+ |
+|       |          +-| translation |         |  Lookup    +----           +---------   AP SPI    | |
+|       |            +-------------+         |            |   |           |        +-------------+ |
+|       |            +-------------+         |            |   |  IO       |        +-------------+ |
+|       +------------| SMMU        +---------+            |   |  Windows  +---------  AP MCI0/1  | |
+|                    | translation |         +------------+   |  Lookup   |        +-------------+ |
+|                    +---------+---+                          |           |        +-------------+ |
+|             -                |                              |           +---------   AP STM    | |
+|             +-----------------                              |           |        +-------------+ |
+| AP          |                |                              +-+---------+                        |
++---------------------------------------------------------------|----------------------------------+
++-------------|-------------------------------------------------|----------------------------------+
+| CP          |            +-------------+               +------+-----+      +-------------------+ |
+|             |            |             |               |            +-------   SB CFG Space    | |
+|             |            |   DIOB      |               |            |      +-------------------+ |
+|             |            |   Windows   -----------------  IOB       |      +-------------------+ |
+|             |            |   Control   |               |  Windows   +------| SB PCIe-0 - PCIe2 | |
+|             |            |             |               |  Lookup    |      +-------------------+ |
+|             |            +------+------+               |            |      +-------------------+ |
+|             |                   |                      |            +------+      SB NAND      | |
+|             |                   |                      +------+-----+      +-------------------+ |
+|             |                   |                             |                                  |
+|             |                   |                             |                                  |
+|   +------------------+   +------------+                +------+-----+      +-------------------+ |
+|   | Network Engine   |   |            |                |            +-------  SB SPI-0/SPI-1   | |
+|   | Security Engine  |   | PCIe, MSS  |                |  RUNIT     |      +-------------------+ |
+|   | SATA, USB        |   | DMA        |                |  Windows   |      +-------------------+ |
+|   | SD/eMMC          |   |            |                |  Lookup    +-------   SB Device Bus   | |
+|   | TDM, I2C         |   |            |                |            |      +-------------------+ |
+|   +------------------+   +------------+                +------------+                            |
+|                                                                                                  |
++--------------------------------------------------------------------------------------------------+
+
diff --git a/docs/marvell/misc/mvebu-amb.txt b/docs/marvell/misc/mvebu-amb.txt
index 1b22eeea..2a7a41ec 100644
--- a/docs/marvell/misc/mvebu-amb.txt
+++ b/docs/marvell/misc/mvebu-amb.txt
@@ -1,6 +1,8 @@
 AMB - AXI MBUS address decoding
 -------------------------------
 
+AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs.
+
 - The Runit offers a second level of address windows lookup. It is used to map transaction towards
 the CD BootROM, SPI0, SPI1 and Device bus (NOR).
 - The Runit contains eight configurable windows. Each window defines a contiguous,
diff --git a/docs/marvell/misc/mvebu-ccu.txt b/docs/marvell/misc/mvebu-ccu.txt
index 337a5c6c..97640276 100644
--- a/docs/marvell/misc/mvebu-ccu.txt
+++ b/docs/marvell/misc/mvebu-ccu.txt
@@ -1,6 +1,8 @@
 Marvell CCU address decoding bindings
 =====================================
 
+CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+
 The CCU node includes a description of the address decoding configuration.
 
 Mandatory functions:
diff --git a/docs/marvell/misc/mvebu-io-win.txt b/docs/marvell/misc/mvebu-io-win.txt
index 59e4b657..c83ad1fd 100644
--- a/docs/marvell/misc/mvebu-io-win.txt
+++ b/docs/marvell/misc/mvebu-io-win.txt
@@ -1,6 +1,8 @@
 Marvell IO WIN address decoding bindings
 =====================================
 
+IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+
 The IO WIN includes a description of the address decoding configuration.
 
 Transactions that are decoded by CCU windows as IO peripheral, have an additional
diff --git a/docs/marvell/misc/mvebu-iob.txt b/docs/marvell/misc/mvebu-iob.txt
index 6dea0a2e..97ec09d0 100644
--- a/docs/marvell/misc/mvebu-iob.txt
+++ b/docs/marvell/misc/mvebu-iob.txt
@@ -1,6 +1,8 @@
 Marvell IOB address decoding bindings
 =====================================
 
+IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+
 The IOB includes a description of the address decoding configuration.
 
 IOB supports up to n (in CP110 n=24) windows for external memory transaction.
diff --git a/docs/marvell/porting.txt b/docs/marvell/porting.txt
index e264421a..5f0ad3f7 100644
--- a/docs/marvell/porting.txt
+++ b/docs/marvell/porting.txt
@@ -1,13 +1,13 @@
-ATF Porting Guide
+TF-A Porting Guide
 =================
 
-This section describes how to port ATF to a customer board, assuming that the SoC being used is already supported
-in ATF.
+This section describes how to port TF-A to a customer board, assuming that the SoC being used is already supported
+in TF-A.
 
 
 Source Code Structure
 ---------------------
-- The cusomer platform specific code shall reside under "plat/marvell/<soc family>/<soc>_cust"
+- The customer platform specific code shall reside under "plat/marvell/<soc family>/<soc>_cust"
 	(e.g. 'plat/marvell/a8k/a7040_cust').
 - The platform name for build purposes is called "<soc>_cust" (e.g. a7040_cust).
 - The build system will reuse all files from within the soc directory, and take only the porting
@@ -47,7 +47,7 @@ Armada-70x0/Armada-80x0 Porting
 		In A7040-DB specific implementation (plat/marvell/a8k/a70x0/board/marvell_plat_config.c),
 		the image skip is implemented using GPIO: mpp 33 (SW5).
 
-		Before reseting the board make sure there is a valid image on the next flash address:
+		Before resetting the board make sure there is a valid image on the next flash address:
 			-tftp [valid address] flash-image.bin
 			-sf update [valid address] 0x2000000 [size]
 
@@ -56,10 +56,10 @@ Armada-70x0/Armada-80x0 Porting
 
   - DDR Porting (dram_port.c):
 	- This file defines the dram topology and parameters of the target board.
-	- The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (ATF).
-	- The DDR driver called mv_ddr is released separately apart from ATF sources.
+	- The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (TF-A).
+	- The DDR driver called mv_ddr is released separately apart from TF-A sources.
 	- The BLE and consequently, the DDR init code is executed at the early stage of the boot process.
-	- Each supported platform of the ATF has its own DDR porting file called dram_port.c located at
+	- Each supported platform of the TF-A has its own DDR porting file called dram_port.c located at
 	  ``atf/plat/marvell/a8k/<platform>/board`` directory.
 	- Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed porting description.
 	- The build target directory is "build/<platform>/release/ble".