cp110: comphy: remove unused defines

Change-Id: I6841d37e598f6032d60b1c7c8d58bb401e1d2556
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/51242
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

1 files changed, 0 insertions, 284 deletions

diff --git a/drivers/marvell/comphy.h b/drivers/marvell/comphy.h
index 5596e129..41c97670 100644
--- a/drivers/marvell/comphy.h
+++ b/drivers/marvell/comphy.h
@@ -48,10 +48,6 @@
 #define COMMON_PHY_PHY_MODE_OFFSET		15
 #define COMMON_PHY_PHY_MODE_MASK		(0x1 << COMMON_PHY_PHY_MODE_OFFSET)
 
-#define COMMON_PHY_CFG6_REG			0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET	18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK		(0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
 #define COMMON_SELECTOR_PHY_OFFSET		0x140
 #define COMMON_SELECTOR_PIPE_OFFSET		0x144
 
@@ -62,60 +58,11 @@
 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK		(0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET	25
 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK		(0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET		26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK			(0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET		27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK			(0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
 
 #define DFX_DEV_GEN_CTRL12			0x80
 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET		7
 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK		(0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
 
-#define MAX_LANE_OPTIONS			10
-#define MAX_UTMI_PHY_COUNT			3
-
-
-/* SerDes IP register */
-#define SD_EXTERNAL_CONFIG0_REG				0
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET		1
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK		(1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET	3
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK		(0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET	7
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK		(0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET		11
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK		(1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET		12
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK		(1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET	14
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK		(1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET		15
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK		(0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
-
-#define SD_EXTERNAL_CONFIG1_REG			0x4
-#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET	3
-#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK	(0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET	4
-#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK	(0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET	5
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK	(0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET	6
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK	(0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_CONFIG2_REG			0x8
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET	4
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK	(0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
-
-#define SD_EXTERNAL_STATUS0_REG			0x18
-#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET	2
-#define SD_EXTERNAL_STATUS0_PLL_TX_MASK		(0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
-#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET	3
-#define SD_EXTERNAL_STATUS0_PLL_RX_MASK		(0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
-#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET	4
-#define SD_EXTERNAL_STATUS0_RX_INIT_MASK	(0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET	6
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK	(0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
-
 /* HPIPE register */
 #define HPIPE_PWR_PLL_REG			0x4
 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET		0
@@ -123,42 +70,10 @@
 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET		5
 #define HPIPE_PWR_PLL_PHY_MODE_MASK		(0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
 
-#define HPIPE_KVCO_CALIB_CTRL_REG		0x8
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET	12
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK	(0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
-
-#define HPIPE_CAL_REG1_REG			0xc
-#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET	10
-#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK		(0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET	15
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK	(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-
-#define HPIPE_SQUELCH_FFE_SETTING_REG           0x018
-
 #define HPIPE_DFE_REG0				0x01C
 #define HPIPE_DFE_RES_FORCE_OFFSET		15
 #define HPIPE_DFE_RES_FORCE_MASK		(0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
 
-#define HPIPE_DFE_F3_F5_REG			0x028
-#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET		14
-#define HPIPE_DFE_F3_F5_DFE_EN_MASK		(0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
-#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET		15
-#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK		(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
-
-#define HPIPE_G1_SET_0_REG			0x034
-#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET		1
-#define HPIPE_G1_SET_0_G1_TX_AMP_MASK		(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET	7
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK		(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
-
-#define HPIPE_G1_SET_1_REG			0x038
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET	0
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK	(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET	3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK	(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET	10
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK	(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
-
 #define HPIPE_G2_SET_1_REG			0x040
 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET	0
 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK	(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
@@ -175,12 +90,6 @@
 #define HPIPE_G3_SETTING_BIT_OFFSET		13
 #define HPIPE_G3_SETTING_BIT_MASK		(0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
 
-#define HPIPE_LOOPBACK_REG			0x08c
-#define HPIPE_LOOPBACK_SEL_OFFSET		1
-#define HPIPE_LOOPBACK_SEL_MASK			(0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
-
-#define HPIPE_SYNC_PATTERN_REG                  0x090
-
 #define HPIPE_INTERFACE_REG			0x94
 #define HPIPE_INTERFACE_GEN_MAX_OFFSET		10
 #define HPIPE_INTERFACE_GEN_MAX_MASK		(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
@@ -189,20 +98,6 @@
 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET	14
 #define HPIPE_INTERFACE_LINK_TRAIN_MASK		(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
 
-#define HPIPE_ISOLATE_MODE_REG			0x98
-#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET	0
-#define HPIPE_ISOLATE_MODE_GEN_RX_MASK		(0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
-#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET	4
-#define HPIPE_ISOLATE_MODE_GEN_TX_MASK		(0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
-
-#define HPIPE_G1_SET_2_REG			0xf4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET	0
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK		(0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET	4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK	(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
-
-#define HPIPE_VTHIMPCAL_CTRL_REG                0x104
-
 #define HPIPE_VDD_CAL_CTRL_REG			0x114
 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET		5
 #define HPIPE_EXT_SELLV_RXSAMPL_MASK		(0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
@@ -229,36 +124,14 @@
 #define HPIPE_MISC_REFCLK_SEL_OFFSET		10
 #define HPIPE_MISC_REFCLK_SEL_MASK		(0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
 
-#define HPIPE_RX_CONTROL_1_REG			0x140
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET	11
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK	(0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET	12
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK	(0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_REG			0x148
-#define HPIPE_PWR_CTR_RST_DFE_OFFSET		0
-#define HPIPE_PWR_CTR_RST_DFE_MASK		(0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
-#define HPIPE_PWR_CTR_SFT_RST_OFFSET		10
-#define HPIPE_PWR_CTR_SFT_RST_MASK		(0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
-
-#define HPIPE_PLLINTP_REG1			0x150
-
 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG	0x16C
 #define HPIPE_SMAPLER_OFFSET			12
 #define HPIPE_SMAPLER_MASK			(0x1 << HPIPE_SMAPLER_OFFSET)
 
-#define HPIPE_TX_REG1_REG			0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET	5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK		(0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET		10
-#define HPIPE_TX_REG1_SLC_EN_MASK		(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
 #define HPIPE_PWR_CTR_DTL_REG			0x184
 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET	2
 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK		(0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
 
-#define HPIPE_RX_REG3				0x188
-
 #define HPIPE_FRAME_DET_CONTROL_REG		0x220
 #define HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET	12
 #define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK	(0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET)
@@ -279,9 +152,6 @@
 #define HPIPE_TRX_TRAIN_TIMER_OFFSET		0
 #define HPIPE_TRX_TRAIN_TIMER_MASK		(0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
 
-#define HPIPE_PCIE_REG1				0x288
-#define HPIPE_PCIE_REG3				0x290
-
 #define HPIPE_TX_TRAIN_CTRL_5_REG		0x2A4
 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET	11
 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK		(0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
@@ -315,28 +185,11 @@
 #define HPIPE_TX_NUM_OF_PRESET_MASK		(0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
 #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET		15
 #define HPIPE_TX_SWEEP_PRESET_EN_MASK		(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-
-#define HPIPE_G1_SETTINGS_3_REG			0x440
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET	9
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK	(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
-
-#define HPIPE_G1_SETTINGS_4_REG			0x444
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET	8
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK	(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
-
-#define HPIPE_G2_SETTINGS_3_REG			0x448
-
 #define HPIPE_G2_SETTINGS_4_REG			0x44C
 #define HPIPE_G2_DFE_RES_OFFSET			8
 #define HPIPE_G2_DFE_RES_MASK			(0x3 << HPIPE_G2_DFE_RES_OFFSET)
 
 #define HPIPE_G3_SETTING_3_REG			0x450
-#define HPIPE_G3_FFE_CAP_SEL_OFFSET		0
-#define HPIPE_G3_FFE_CAP_SEL_MASK		(0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G3_FFE_RES_SEL_OFFSET		4
-#define HPIPE_G3_FFE_RES_SEL_MASK		(0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
-#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET	7
-#define HPIPE_G3_FFE_SETTING_FORCE_MASK		(0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET	12
 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK		(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET	14
@@ -354,43 +207,19 @@
 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET		7
 #define HPIPE_DFE_CTRL_28_PIPE4_MASK		(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
 
-#define HPIPE_G1_SETTING_5_REG			0x538
-#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET	0
-#define HPIPE_G1_SETTING_5_G1_ICP_MASK		(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
-
 #define HPIPE_G3_SETTING_5_REG			0x548
 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET	0
 #define HPIPE_G3_SETTING_5_G3_ICP_MASK		(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
 
-#define HPIPE_LANE_CONFIG0_REG			0x600
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET	0
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK	(0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
-
-#define HPIPE_LANE_CONFIG1_REG			0x604
-#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET	9
-#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK		(0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET	10
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK	(0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
-
 #define HPIPE_LANE_STATUS1_REG			0x60C
 #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET	0
 #define HPIPE_LANE_STATUS1_PCLK_EN_MASK		(0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
 
 #define HPIPE_LANE_CFG4_REG                     0x620
-#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET		0
-#define HPIPE_LANE_CFG4_DFE_CTRL_MASK		(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
 #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET	3
 #define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK		(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET		6
-#define HPIPE_LANE_CFG4_DFE_OVER_MASK		(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
-#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET		7
-#define HPIPE_LANE_CFG4_SSC_CTRL_MASK		(0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
 
 #define HPIPE_LANE_EQU_CONFIG_0_REG		0x69C
-#define HPIPE_CFG_EQ_FS_OFFSET			0
-#define HPIPE_CFG_EQ_FS_MASK			(0x3f << HPIPE_CFG_EQ_FS_OFFSET)
-#define HPIPE_CFG_EQ_LF_OFFSET			6
-#define HPIPE_CFG_EQ_LF_MASK			(0x3f << HPIPE_CFG_EQ_LF_OFFSET)
 #define HPIPE_CFG_PHY_RC_EP_OFFSET		12
 #define HPIPE_CFG_PHY_RC_EP_MASK		(0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
 
@@ -402,114 +231,6 @@
 #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET		14
 #define HPIPE_CFG_EQ_BUNDLE_DIS_MASK		(0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET)
 
-#define HPIPE_LANE_PRESET_CFG0_REG		0x6a8
-#define HPIPE_CFG_CURSOR_PRESET0_OFFSET		0
-#define HPIPE_CFG_CURSOR_PRESET0_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET)
-#define HPIPE_CFG_CURSOR_PRESET1_OFFSET		6
-#define HPIPE_CFG_CURSOR_PRESET1_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG1_REG		0x6ac
-#define HPIPE_CFG_CURSOR_PRESET2_OFFSET		0
-#define HPIPE_CFG_CURSOR_PRESET2_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET)
-#define HPIPE_CFG_CURSOR_PRESET3_OFFSET		6
-#define HPIPE_CFG_CURSOR_PRESET3_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG2_REG		0x6b0
-#define HPIPE_CFG_CURSOR_PRESET4_OFFSET		0
-#define HPIPE_CFG_CURSOR_PRESET4_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET)
-#define HPIPE_CFG_CURSOR_PRESET5_OFFSET		6
-#define HPIPE_CFG_CURSOR_PRESET5_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG3_REG		0x6b4
-#define HPIPE_CFG_CURSOR_PRESET6_OFFSET		0
-#define HPIPE_CFG_CURSOR_PRESET6_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET)
-#define HPIPE_CFG_CURSOR_PRESET7_OFFSET		6
-#define HPIPE_CFG_CURSOR_PRESET7_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG4_REG		0x6b8
-#define HPIPE_CFG_CURSOR_PRESET8_OFFSET		0
-#define HPIPE_CFG_CURSOR_PRESET8_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET)
-#define HPIPE_CFG_CURSOR_PRESET9_OFFSET		6
-#define HPIPE_CFG_CURSOR_PRESET9_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG5_REG		0x6bc
-#define HPIPE_CFG_CURSOR_PRESET10_OFFSET	0
-#define HPIPE_CFG_CURSOR_PRESET10_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET)
-#define HPIPE_CFG_CURSOR_PRESET11_OFFSET	6
-#define HPIPE_CFG_CURSOR_PRESET11_MASK		(0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG6_REG		0x6c0
-#define HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET0_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG7_REG		0x6c4
-#define HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET1_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG8_REG		0x6c8
-#define HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET2_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG9_REG		0x6cc
-#define HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET3_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG10_REG		0x6d0
-#define HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET4_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG11_REG		0x6d4
-#define HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET5_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG12_REG		0x6d8
-#define HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET6_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG13_REG		0x6dc
-#define HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET7_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG14_REG		0x6e0
-#define HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET8_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG15_REG		0x6e4
-#define HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET9_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG16_REG		0x6e8
-#define HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET10_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET)
-
-#define HPIPE_LANE_PRESET_CFG17_REG		0x6ec
-#define HPIPE_CFG_PRE_CURSOR_PRESET11_OFFSET	0
-#define HPIPE_CFG_PRE_CURSOR_PRESET11_MASK	(0x3f << HPIPE_CFG_PRE_CURSOR_PRESET11_OFFSET)
-#define HPIPE_CFG_POST_CURSOR_PRESET11_OFFSET	6
-#define HPIPE_CFG_POST_CURSOR_PRESET11_MASK	(0x3f << HPIPE_CFG_POST_CURSOR_PRESET11_OFFSET)
-
 #define HPIPE_LANE_EQ_REMOTE_SETTING_REG	0x6f8
 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET	0
 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK	(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
@@ -528,10 +249,6 @@
 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET	9
 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK	(0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
 
-#define HPIPE_TST_MODE_CTRL_REG			0x708
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET	2
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK	(0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
-
 #define HPIPE_CLK_SRC_LO_REG			0x70c
 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET	1
 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK		(0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
@@ -550,7 +267,6 @@
 #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET	7
 #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK		(0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
 
-#define HPIPE_GLOBAL_MISC_CTRL                  0x718
 #define HPIPE_GLOBAL_PM_CTRL                    0x740
 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET	0
 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK	(0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)