diff options
| author | Ken Ma <make@marvell.com> | 2018-01-19 15:07:03 +0800 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2018-01-24 11:45:03 +0200 |
| commit | dd4267f35d7d606098c25a41ed8c06b605f42e7e (patch) | |
| tree | e3fa7b9c85c4954b06011ab1ee9ec1be7cfb8f1b /drivers | |
| parent | 31b8a71ceb2fd24a895ecb0969d22e616b676992 (diff) | |
errata: ap806: implement workaround for errata-id 3033912
ERRATA ID: RES-3033912 - Internal Address Space Init state causes
a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
[0x80_0000, 0xff_ffff] that cause accesses to the segment of
[0xf070_0000, 0xf07f_ffff] to act as RAZWI.
Change-Id: I8f38ad940d985be11ce0304d0b9dfd212ca4cb82
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/48747
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/marvell/mochi/apn806_setup.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 4a592650..443fce69 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -52,6 +52,8 @@ #define CCU_LTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x300) #define CCU_CLEAN_INV_WRITE_OFFSET 8 +#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + 0x90 + 4 * (win)) + #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) #define DVM_48BIT_VA_ENABLE (1 << 21) @@ -136,6 +138,20 @@ void ap806_generic_timer_init(void) } } +static void apn806_errata_wa_init(void) +{ + /* + * EERATA ID: RES-3033912 - Internal Address Space Init state causes + * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] + * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to + * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and + * [0x80_0000, 0xff_ffff] that cause accesses to the + * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. + */ + mmio_write_32(CCU_RGF(4), 0x37f9b809); + mmio_write_32(CCU_RGF(5), 0x7ffa0009); +} + void init_aurora2(void) { uint32_t reg; @@ -165,6 +181,8 @@ void init_aurora2(void) mmio_write_32(CCU_LTC_CR, reg); } #endif /* !LLC_DISABLE */ + + apn806_errata_wa_init(); } |