diff options
| author | orenbh <orenbh@marvell.com> | 2017-03-27 10:20:15 +0200 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-04-06 15:57:21 +0300 |
| commit | 04c2d8de8d06190952219b6c8c23d21d494e2e95 (patch) | |
| tree | 174ae95a57047e823eca08714b6669d619e5a045 /include | |
| parent | 5c456b372a450d414c0012bd8ec5a2ea46888745 (diff) | |
pm: a70x0: a80x0: update trace address definition
Modify ATF trace support address definition based on
MSS updated address mapping
Change-Id: I5702bd311f234bdfefa35d1691645e9630d9a415
Signed-off-by: orenbh <orenbh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38499
Reviewed-by: Haim Boot <hayim@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/plat/marvell/a8k/common/plat_pm_trace.h | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/include/plat/marvell/a8k/common/plat_pm_trace.h b/include/plat/marvell/a8k/common/plat_pm_trace.h index 813a3bdc..57c44ac3 100644 --- a/include/plat/marvell/a8k/common/plat_pm_trace.h +++ b/include/plat/marvell/a8k/common/plat_pm_trace.h @@ -64,37 +64,37 @@ struct pm_trace_ctrl { }; /* trace size definition */ -#define AP_MSS_ATF_CORE_INFO_SIZE (256) -#define AP_MSS_ATF_CORE_ENTRY_SIZE (8) -#define AP_MSS_ATF_TRACE_SIZE_MASK (0xFF) +#define AP_MSS_ATF_CORE_INFO_SIZE (256) +#define AP_MSS_ATF_CORE_ENTRY_SIZE (8) +#define AP_MSS_ATF_TRACE_SIZE_MASK (0xFF) /* trace address definition */ #define AP_MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110) -#define AP_MSS_ATF_CORE_0_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x522050) -#define AP_MSS_ATF_CORE_1_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x522060) -#define AP_MSS_ATF_CORE_2_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x522070) -#define AP_MSS_ATF_CORE_3_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x522080) +#define AP_MSS_ATF_CORE_0_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520140) +#define AP_MSS_ATF_CORE_1_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520150) +#define AP_MSS_ATF_CORE_2_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520160) +#define AP_MSS_ATF_CORE_3_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520170) #define AP_MSS_ATF_CORE_CTRL_BASE (AP_MSS_ATF_CORE_0_CTRL_BASE) -#define AP_MSS_ATF_CORE_0_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5220D0) -#define AP_MSS_ATF_CORE_0_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5220D4) -#define AP_MSS_ATF_CORE_1_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5228D0) -#define AP_MSS_ATF_CORE_1_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5228D4) -#define AP_MSS_ATF_CORE_2_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5230D0) -#define AP_MSS_ATF_CORE_2_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5230D4) -#define AP_MSS_ATF_CORE_3_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5238D0) -#define AP_MSS_ATF_CORE_3_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5238D4) +#define AP_MSS_ATF_CORE_0_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5201C0) +#define AP_MSS_ATF_CORE_0_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5201C4) +#define AP_MSS_ATF_CORE_1_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5209C0) +#define AP_MSS_ATF_CORE_1_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5209C4) +#define AP_MSS_ATF_CORE_2_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5211C0) +#define AP_MSS_ATF_CORE_2_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5211C4) +#define AP_MSS_ATF_CORE_3_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5219C0) +#define AP_MSS_ATF_CORE_3_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5219C4) #define AP_MSS_ATF_CORE_INFO_BASE (AP_MSS_ATF_CORE_0_INFO_BASE) /* trace info definition */ -#define TRACE_PWR_DOMAIN_OFF (0x10000) -#define TRACE_PWR_DOMAIN_SUSPEND (0x20000) -#define TRACE_PWR_DOMAIN_SUSPEND_FINISH (0x30000) -#define TRACE_PWR_DOMAIN_ON (0x40000) -#define TRACE_PWR_DOMAIN_ON_FINISH (0x50000) +#define TRACE_PWR_DOMAIN_OFF (0x10000) +#define TRACE_PWR_DOMAIN_SUSPEND (0x20000) +#define TRACE_PWR_DOMAIN_SUSPEND_FINISH (0x30000) +#define TRACE_PWR_DOMAIN_ON (0x40000) +#define TRACE_PWR_DOMAIN_ON_FINISH (0x50000) -#define TRACE_PWR_DOMAIN_ON_MASK (0xFF) +#define TRACE_PWR_DOMAIN_ON_MASK (0xFF) #if defined(SCP_IMAGE) && defined(PM_TRACE_ENABLE) |