diff options
| author | Marcin Wojtas <mw@semihalf.com> | 2017-03-29 23:28:28 +0200 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-04-04 17:47:23 +0300 |
| commit | 9a0b444a2b7a385a65fd0e8396ad278a4188bda3 (patch) | |
| tree | 0099873dbccc3403b03036e6070e130ad9ecac05 /include | |
| parent | 80316c829d0c56b67eb60c39fe3fd6266b314860 (diff) | |
fix: cp110: enable optional RTC reconfiguration
This commit enables optional reset of the RTC, in case
its registers' contents did not sustain the reboot or power-off/on
sequence. Without it, further usage of RTC is impossible (e.g.
writing values to RTC_TIME register will not succeed).
JIRA: A7K8K-1243
The reset is performed only if Clock Correction register
does not comprise MVEBU_RTC_NOMINAL_TIMING, what helps to
distinguish, whether the software configured RTC before or it comprises
the default value.
Change-Id: I9d6288ac85a453c545c1ec0b773b32144aea1759
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38377
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/marvell/mochi/cp110_setup.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 6ccbaaa5..d49f4a97 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -34,6 +34,8 @@ #ifndef __PLAT_CP110_H__ #define __PLAT_CP110_H__ +#include <apn806_setup.h> + #define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_BASE(0) + 0x40) #define MVEBU_DEVICE_ID_OFFSET (0) #define MVEBU_DEVICE_ID_MASK (0xffff << MVEBU_DEVICE_ID_OFFSET) @@ -42,6 +44,32 @@ #define MVEBU_70X0_DEV_ID (0x7040) #define MVEBU_80X0_DEV_ID (0x8040) +/******************************************************************************* + * RTC Configuration + ******************************************************************************/ +#define MVEBU_RTC_BASE(cp_index) (MVEBU_CP_REGS_BASE(cp_index) + 0x284000) +#define MVEBU_RTC_STATUS_REG 0x0 +#define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 +#define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 +#define MVEBU_RTC_TIME_REG 0xC +#define MVEBU_RTC_IRQ_1_CONFIG_REG 0x4 +#define MVEBU_RTC_IRQ_2_CONFIG_REG 0x8 +#define MVEBU_RTC_ALARM_1_REG 0x10 +#define MVEBU_RTC_ALARM_2_REG 0x14 +#define MVEBU_RTC_CCR_REG 0x18 +#define MVEBU_RTC_NOMINAL_TIMING 0x2000 +#define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF +#define MVEBU_RTC_TEST_CONFIG_REG 0x1C +#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG_OFFS 0x0 +#define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF +#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF +#define MVEBU_RTC_WRCLK_SETUP_OFFS 16 +#define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 +#define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 +#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG_OFFS 0x84 +#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF +#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F + static inline uint32_t cp110_device_id_get(void) { /* Returns: |