diff options
| author | Victor Gu <xigu@marvell.com> | 2017-03-14 19:06:29 +0800 |
|---|---|---|
| committer | Hua Jing <jinghua@marvell.com> | 2017-04-21 08:50:32 +0300 |
| commit | c282885acfc73ba1b5db15b4a82cae501cb12f91 (patch) | |
| tree | 94fdac7524573eae772e239a1aacaaea508790c0 /include | |
| parent | ceccdadde477ca176b60f4b7efdb7999835b0e7f (diff) | |
gicv3: arm: support SPI and PPI irq save and restore
During suspend and resume, some SoC will issue warm reset
and the SPI and PPI irq states are cleared, so IO devices can
not continue to work after resume.
Thus the SPI and PPI irq states should be saved and restored.
This patch adds the SPI and PPI irq state PM support in ARM GICv3 driver.
Change-Id: Ief459375b5cd4f02ba2df015eed2f72d208cf0d1
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37430
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Haim Boot <hayim@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Signed-off-by: zachary <zhangzg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38075
Tested-by: Hua Jing <jinghua@marvell.com>
Signed-off-by: zachary <zhangzg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38608
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/arm/gic_common.h | 2 | ||||
| -rw-r--r-- | include/drivers/arm/gicv3.h | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h index dd8efdc7..be503faa 100644 --- a/include/drivers/arm/gic_common.h +++ b/include/drivers/arm/gic_common.h @@ -65,6 +65,7 @@ #define GICD_ISACTIVER 0x300 #define GICD_ICACTIVER 0x380 #define GICD_IPRIORITYR 0x400 +#define GICD_ITARGETSR 0x800 #define GICD_ICFGR 0xc00 #define GICD_NSACR 0xe00 @@ -93,6 +94,7 @@ #define ISACTIVER_SHIFT 5 #define ICACTIVER_SHIFT ISACTIVER_SHIFT #define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 #define ICFGR_SHIFT 4 #define NSACR_SHIFT 4 diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 0f6034c0..4fdbf0bc 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -104,6 +104,8 @@ #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) +#define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + 0x300) +#define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + 0x380) #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) @@ -267,7 +269,10 @@ unsigned int gicv3_get_pending_interrupt_type(void); unsigned int gicv3_get_pending_interrupt_id(void); unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num); - +void gicv3_irq_save(uintptr_t gicd_base); +void gicv3_irq_restore(uintptr_t gicd_base); +void gicv3_irq_pcpu_save(uintptr_t gicr_base, uint32_t proc_num); +void gicv3_irq_pcpu_restore(uintptr_t gicr_base, uint32_t proc_num); #endif /* __ASSEMBLY__ */ #endif /* __GICV3_H__ */ |