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authorwangwen <wangwen@marvell.com>2017-07-03 18:20:23 +0800
committerKostya Porotchkin <kostap@marvell.com>2017-08-01 13:59:02 +0300
commit32962e938024056377e6c6f10fa1f5f03910343b (patch)
tree471a4a15b824434abce9855653fd25020506d12f /include
parent32a0e657928694b06dc2842d8c23a49a5fb4273f (diff)
Define write function for ICC_SGI1R_EL1
GICv3 driver has no ICC_SGI1R_EL1 write function, so add write function for ICC_SGI1R_EL1 Change-Id: I71084673f960f17453ea850bfd4b4bb48e682445 Signed-off-by: wangwen <wangwen@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41098 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'include')
-rw-r--r--include/lib/aarch64/arch.h1
-rw-r--r--include/lib/aarch64/arch_helpers.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index fb8cbc0b..a074d7f8 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -96,6 +96,7 @@
#define ICC_IAR1_EL1 S3_0_c12_c12_0
#define ICC_EOIR0_EL1 S3_0_c12_c8_1
#define ICC_EOIR1_EL1 S3_0_c12_c12_1
+#define ICC_SGI1R_EL1 S3_0_c12_c11_5
/*******************************************************************************
* Generic timer memory mapped registers & offsets
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 4d936ad5..ee3d9347 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -291,6 +291,7 @@ DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
+DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi1r_el1, ICC_SGI1R_EL1)
#define IS_IN_EL(x) \