diff options
| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2017-11-30 14:53:53 +0000 |
|---|---|---|
| committer | Igal Liberman <igall@marvell.com> | 2018-01-22 14:19:46 +0200 |
| commit | 5378d30323828d32243a867b245d855562e0829b (patch) | |
| tree | 4b60e06d795a2e929038b1baf390c8db947d8fe5 /include | |
| parent | ced0a35b6444fd36fe62d597e1ff4486fd352ffc (diff) | |
Workaround for CVE-2017-5715 on Cortex A57 and A72
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling
and enabling the MMU. To achieve this without performing any branch
instruction, a per-cpu vbar is installed which executes the workaround
and then branches off to the corresponding vector entry in the main
vector table. A side effect of this change is that the main vbar is
configured before any reset handling. This is to allow the per-cpu
reset function to override the vbar setting.
This workaround is enabled by default on the affected CPUs.
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Change-Id: I135c4173b4f5a16186c8b2e85dc5adb21e041b0b
[Resolve conflicts]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/48855
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/common/aarch64/el3_common_macros.S | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S index 9b22a734..be82bd1e 100644 --- a/include/common/aarch64/el3_common_macros.S +++ b/include/common/aarch64/el3_common_macros.S @@ -37,7 +37,7 @@ /* * Helper macro to initialise EL3 registers we care about. */ - .macro el3_arch_init_common _exception_vectors + .macro el3_arch_init_common /* --------------------------------------------------------------------- * Enable the instruction cache, stack pointer and data access alignment * checks @@ -62,14 +62,6 @@ #endif /* IMAGE_BL31 */ /* --------------------------------------------------------------------- - * Set the exception vectors. - * --------------------------------------------------------------------- - */ - adr x0, \_exception_vectors - msr vbar_el3, x0 - isb - - /* --------------------------------------------------------------------- * Early set RES1 bits in SCR_EL3. Set EA bit to catch both * External Aborts and SError Interrupts in EL3 and also the SIF bit * to disable instruction fetches from Non-secure memory. @@ -180,6 +172,14 @@ .endif /* _warm_boot_mailbox */ /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, \_exception_vectors + msr vbar_el3, x0 + isb + + /* --------------------------------------------------------------------- * It is a cold boot. * Perform any processor specific actions upon reset e.g. cache, TLB * invalidations etc. @@ -187,7 +187,7 @@ */ bl reset_handler - el3_arch_init_common \_exception_vectors + el3_arch_init_common .if \_secondary_cold_boot /* ------------------------------------------------------------- |