diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-05 14:54:46 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-14 15:00:13 -0700 |
| commit | fb7d32e5881ef2445e8fe2305005f5590d4a7cfa (patch) | |
| tree | 24c77f58069dddfc1e8c530d06f9bf94bc77f613 /lib/cpus/aarch32 | |
| parent | 6311f63de02ee04d93016242977ade4727089de8 (diff) | |
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'lib/cpus/aarch32')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a53.S | 12 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a57.S | 22 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a72.S | 28 |
3 files changed, 31 insertions, 31 deletions
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index cdc8cacb..3d5f833a 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S @@ -15,9 +15,9 @@ * --------------------------------------------- */ func cortex_a53_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A53_ECTLR + bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A53_ECTLR isb dsb sy bx lr @@ -32,9 +32,9 @@ func cortex_a53_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A53_ECTLR + orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A53_ECTLR isb bx lr endfunc cortex_a53_reset_func diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index 3fc0a6d1..ed478463 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -16,9 +16,9 @@ * --------------------------------------------- */ func cortex_a57_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A57_ECTLR bx lr endfunc cortex_a57_disable_smp @@ -28,11 +28,11 @@ endfunc cortex_a57_disable_smp * --------------------------------------------- */ func cortex_a57_disable_l2_prefetch - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ - CPUECTLR_L2_DPFTCH_DIST_MASK) - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT + bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ + CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) + stcopr16 r0, r1, CORTEX_A57_ECTLR isb dsb ish bx lr @@ -59,9 +59,9 @@ func cortex_a57_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A57_ECTLR isb bx lr endfunc cortex_a57_reset_func diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 9d39a538..cdd83adf 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -15,11 +15,11 @@ * --------------------------------------------- */ func cortex_a72_disable_l2_prefetch - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ - CPUECTLR_L2_DPFTCH_DIST_MASK) - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT + bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ + CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) + stcopr16 r0, r1, CORTEX_A72_ECTLR isb bx lr endfunc cortex_a72_disable_l2_prefetch @@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch * --------------------------------------------- */ func cortex_a72_disable_hw_prefetcher - ldcopr16 r0, r1, CPUACTLR - orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH - stcopr16 r0, r1, CPUACTLR + ldcopr16 r0, r1, CORTEX_A72_ACTLR + orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH + stcopr16 r0, r1, CORTEX_A72_ACTLR isb dsb ish bx lr @@ -43,9 +43,9 @@ endfunc cortex_a72_disable_hw_prefetcher * --------------------------------------------- */ func cortex_a72_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A72_ECTLR bx lr endfunc cortex_a72_disable_smp @@ -70,9 +70,9 @@ func cortex_a72_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A72_ECTLR isb bx lr endfunc cortex_a72_reset_func |