diff options
| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2017-11-30 14:53:53 +0000 |
|---|---|---|
| committer | Igal Liberman <igall@marvell.com> | 2018-01-22 14:19:46 +0200 |
| commit | 5378d30323828d32243a867b245d855562e0829b (patch) | |
| tree | 4b60e06d795a2e929038b1baf390c8db947d8fe5 /lib/cpus/aarch64/cortex_a57.S | |
| parent | ced0a35b6444fd36fe62d597e1ff4486fd352ffc (diff) | |
Workaround for CVE-2017-5715 on Cortex A57 and A72
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling
and enabling the MMU. To achieve this without performing any branch
instruction, a per-cpu vbar is installed which executes the workaround
and then branches off to the corresponding vector entry in the main
vector table. A side effect of this change is that the main vbar is
configured before any reset handling. This is to allow the per-cpu
reset function to override the vbar setting.
This workaround is enabled by default on the affected CPUs.
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Change-Id: I135c4173b4f5a16186c8b2e85dc5adb21e041b0b
[Resolve conflicts]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/48855
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Diffstat (limited to 'lib/cpus/aarch64/cortex_a57.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index d6b181d0..d1ed5158 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -361,6 +361,11 @@ func cortex_a57_reset_func bl errata_a57_833471_wa #endif +#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 + adr x0, workaround_mmu_runtime_exceptions + msr vbar_el3, x0 +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- |