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| author | Eleanor Bonnici <Eleanor.bonnici@arm.com> | 2017-08-02 18:33:41 +0100 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2018-04-16 14:05:18 +0300 |
| commit | d1f581f1aae5b7fc75966cd00d4c7e13514a2f3f (patch) | |
| tree | 047802644e9e05cf9ca70636ee3974a60d3a99af /lib/cpus/aarch64/cortex_a73.S | |
| parent | 7c3a542da2128e4c2d09c191b00b6e00c3c4fc50 (diff) | |
Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53228
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'lib/cpus/aarch64/cortex_a73.S')
0 files changed, 0 insertions, 0 deletions