plat: marvell: a8k: allow to load scp_bl2 firmware that doesn't contain PM FW

Hitherto if the SCP_BL2 path was defined, Marvell platform code
(plat/marvell/a8k/common/a8k_common.mk via
 plat/marvell/a8k/common/mss/mss_common.mk) was defining SCP_IMAGE, which was
used in power management related code(mainly in plat_pm.c) for choosing proper
PM related code. Therefore there were two different situation:
1) The SCP_BL2 was not defined, then the ATF used its own PM related code
2) The SCP_BL2 was defined and ATF assumed that during SCP_BL2 stage the
firmware with PM support was loaded into MSS AP CM3 and PM was managed mainly
via IPC messages between ATF and MSS AP CM3 firmware.

Now in some cases the firmware for MSS AP CM3 does not support PM therefore
it causes some issue: during Linux boot only one CPU was brought out from reset
and all secondary CPUs remained down.

After this change the Marvell platform code can verify if the firmware loaded to
MSS AP CM3 has PM support at runtime and does not make assumption basing on
SCP_BL2 definition anymore.

In other words all preprocessor condition of SCP_IMAGE was replaced by runtime
condition that allows to really distinguish between situation where we are
running PM firmware or not, so three different scenario are possible and handled
correctly now:
1) The SCP_BL2 is not used at all then the ATF uses its own PM related code.
2) The SCP_BL2 contains firmware for MSS AP CM3 and it supports PM, then ATF
manage PM mainly via IPC messages between ATF and MSS AP CM3 firmware.
3) The SCP_BL2 does not contain firmware for MSS AP CM3 or it contain firmware
that does not support PM, then ATF uses its own PM related code.

Change-Id: I26da4db968966cb5e61714ff192fb645a3a57875
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/43573
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/44773
Tested-by: Kostya Porotchkin <kostap@marvell.com>

1 files changed, 14 insertions, 10 deletions

diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index ee016d5d..b8f901ef 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -13,6 +13,7 @@
 #include <runtime_instr.h>
 #include <string.h>
 #include "psci_private.h"
+#include <plat_marvell.h>
 
 /******************************************************************************
  * Construct the psci_power_state to request power OFF at all power levels.
@@ -94,6 +95,19 @@ int psci_do_cpu_off(unsigned int end_pwrlvl)
 		PMF_CACHE_MAINT);
 #endif
 
+#ifdef SCP_IMAGE
+	if (is_pm_fw_running()) {
+		/*
+		 * MSS implementation does not support cluster power down
+		 * in case of Hot plug, therefore we defined MPIDR_AFFLVL1
+		 * state to PSCI_LOCAL_STATE_RUN. resulting in max off level
+		 * set to CPU level
+		 */
+		state_info.pwr_domain_state[MPIDR_AFFLVL1] =
+							   PSCI_LOCAL_STATE_RUN;
+	}
+#endif
+
 	/*
 	 * Arch. management. Initiate power down sequence.
 	 */
@@ -105,16 +119,6 @@ int psci_do_cpu_off(unsigned int end_pwrlvl)
 		PMF_NO_CACHE_MAINT);
 #endif
 
-#ifdef SCP_IMAGE
-	/*
-	 * MSS implementation does not support cluster power down
-	 * in case of Hot plug, therefore we defined MPIDR_AFFLVL1
-	 * state to PSCI_LOCAL_STATE_RUN. resulting in max off level
-	 * set to CPU level
-	 */
-	state_info.pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
-#endif
-
 	/*
 	 * Plat. management: Perform platform specific actions to turn this
 	 * cpu off e.g. exit cpu coherency, program the power controller etc.