diff options
| author | Evan Wang <xswang@marvell.com> | 2017-05-05 09:23:24 +0800 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-05-08 11:13:34 +0300 |
| commit | 13e515390c33384d974db86b5bfa433f774fa2c5 (patch) | |
| tree | f00f98da122faf16ffe703b1cbca8fb4e5e7656a /plat/marvell/a3700/common/plat_pm.c | |
| parent | e107cbc4a297d3688d71ab77bad8fe028b696bce (diff) | |
fix: pm: a3700: reinit CPU decode window in resume sequence
In order to support 4GB DRAM the CPU decode window changed
from default configuration, and the PCIe decode window is
also changed with less than 2GB DRAM to align with 4GB
DRAM. So PCIe will not work well with default CPU decode
window configuration and it needs init again in callback
of pwr_domain_suspend_finish().
JIRA number: A3700-1157
Change-Id: I938070589890215b8d8aaffed4f23ba592184c3e
Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39167
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Ken Ma <make@marvell.com>
Diffstat (limited to 'plat/marvell/a3700/common/plat_pm.c')
| -rw-r--r-- | plat/marvell/a3700/common/plat_pm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/a3700/common/plat_pm.c index 23fa9915..fc0c5ff2 100644 --- a/plat/marvell/a3700/common/plat_pm.c +++ b/plat/marvell/a3700/common/plat_pm.c @@ -701,6 +701,9 @@ void a3700_pwr_domain_suspend_finish(const psci_power_state_t *target_state) */ plat_marvell_interconnect_enter_coherency(); + /* CPU address decoder windows initialization. */ + cpu_wins_init(); + /* fetch CPU-DRAM window mapping information by reading * CPU-DRAM decode windows (only the enabled ones) */ |